1 Marvell Berlin SoC Family Device Tree Bindings
2 ---------------------------------------------------------------
4 Work in progress statement:
6 Device tree files and bindings applying to Marvell Berlin SoCs and boards are
7 considered "unstable". Any Marvell Berlin device tree binding may change at any
8 time. Be sure to use a device tree binary and a kernel image generated from the
11 Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
14 ---------------------------------------------------------------
16 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
17 shall have the following properties:
19 * Required root node properties:
20 compatible: must contain "marvell,berlin"
22 In addition, the above compatible shall be extended with the specific
23 SoC and board used. Currently known SoC compatibles are:
24 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
25 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
26 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
27 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
28 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
33 model = "Sony NSZ-GS7";
34 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
39 * Marvell Berlin CPU control bindings
41 CPU control register allows various operations on CPUs, like resetting them
45 - compatible: should be "marvell,berlin-cpu-ctrl"
46 - reg: address and length of the register set
51 compatible = "marvell,berlin-cpu-ctrl";
52 reg = <0xf7dd0000 0x10000>;
55 * Marvell Berlin2 chip control binding
57 Marvell Berlin SoCs have a chip control register set providing several
58 individual registers dealing with pinmux, padmux, clock, reset, and secondary
59 CPU boot address. Unfortunately, the individual registers are spread among the
60 chip control registers, so there should be a single DT node only providing the
61 different functions which are described below.
64 - compatible: shall be one of
65 "marvell,berlin2-chip-ctrl" for BG2
66 "marvell,berlin2cd-chip-ctrl" for BG2CD
67 "marvell,berlin2q-chip-ctrl" for BG2Q
68 - reg: address and length of following register sets for
69 BG2/BG2CD: chip control register set
70 BG2Q: chip control register set and cpu pll registers
72 * Marvell Berlin2 system control binding
74 Marvell Berlin SoCs have a system control register set providing several
75 individual registers dealing with pinmux, padmux, and reset.
78 - compatible: should be one of
79 "marvell,berlin2-system-ctrl" for BG2
80 "marvell,berlin2cd-system-ctrl" for BG2CD
81 "marvell,berlin2q-system-ctrl" for BG2Q
82 - reg: address and length of the system control register set
84 * Clock provider binding
86 As clock related registers are spread among the chip control registers, the
87 chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
88 SoCs share the same IP for PLLs and clocks, with some minor differences in
89 features and register layout.
92 - #clock-cells: shall be set to 1
93 - clocks: clock specifiers referencing the core clock input clocks
94 - clock-names: array of strings describing the input clock specifiers above.
95 Allowed clock-names for the reference clocks are
96 "refclk" for the SoCs osciallator input on all SoCs,
97 and SoC-specific input clocks for
98 BG2/BG2CD: "video_ext0" for the external video clock input
100 Clocks provided by core clocks shall be referenced by a clock specifier
101 indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
102 for the corresponding index mapping.
104 * Pin controller binding
106 Pin control registers are part of both register sets, chip control and system
107 control. The pins controlled are organized in groups, so no actual pin
108 information is needed.
110 A pin-controller node should contain subnodes representing the pin group
111 configurations, one per function. Each subnode has the group name and the muxing
114 Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
115 a 'function' in the pin-controller subsystem.
117 Required subnode-properties:
118 - groups: a list of strings describing the group names.
119 - function: a string describing the function used to mux the groups.
121 * Reset controller binding
123 A reset controller is part of the chip control registers set. The chip control
124 node also provides the reset. The register set is not at the same offset between
128 - #reset-cells: must be set to 2
132 chip: chip-control@ea0000 {
133 compatible = "marvell,berlin2-chip-ctrl";
136 reg = <0xea0000 0x400>;
137 clocks = <&refclk>, <&externaldev 0>;
138 clock-names = "refclk", "video_ext0";
140 spi1_pmux: spi1-pmux {
146 sysctrl: system-controller@d000 {
147 compatible = "marvell,berlin2-system-ctrl";
148 reg = <0xd000 0x100>;
150 uart0_pmux: uart0-pmux {
155 uart1_pmux: uart1-pmux {
160 uart2_pmux: uart2-pmux {