1 Marvell Berlin SoC Family Device Tree Bindings
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4 Work in progress statement:
6 Device tree files and bindings applying to Marvell Berlin SoCs and boards are
7 considered "unstable". Any Marvell Berlin device tree binding may change at any
8 time. Be sure to use a device tree binary and a kernel image generated from the
11 Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
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16 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
17 shall have the following properties:
19 * Required root node properties:
20 compatible: must contain "marvell,berlin"
22 In addition, the above compatible shall be extended with the specific
23 SoC and board used. Currently known SoC compatibles are:
24 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
25 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
26 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
27 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
28 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
33 model = "Sony NSZ-GS7";
34 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
39 * Marvell Berlin CPU control bindings
41 CPU control register allows various operations on CPUs, like resetting them
45 - compatible: should be "marvell,berlin-cpu-ctrl"
46 - reg: address and length of the register set
51 compatible = "marvell,berlin-cpu-ctrl";
52 reg = <0xf7dd0000 0x10000>;
55 * Marvell Berlin2 chip control binding
57 Marvell Berlin SoCs have a chip control register set providing several
58 individual registers dealing with pinmux, padmux, clock, reset, and secondary
59 CPU boot address. Unfortunately, the individual registers are spread among the
60 chip control registers, so there should be a single DT node only providing the
61 different functions which are described below.
65 * the first value should be one of:
66 "marvell,berlin2-chip-ctrl" for BG2
67 "marvell,berlin2cd-chip-ctrl" for BG2CD
68 "marvell,berlin2q-chip-ctrl" for BG2Q
69 * the second and third values must be:
70 "simple-mfd", "syscon"
71 - reg: address and length of following register sets for
72 BG2/BG2CD: chip control register set
73 BG2Q: chip control register set and cpu pll registers
75 * Marvell Berlin2 system control binding
77 Marvell Berlin SoCs have a system control register set providing several
78 individual registers dealing with pinmux, padmux, and reset.
82 * the first value should be one of:
83 "marvell,berlin2-system-ctrl" for BG2
84 "marvell,berlin2cd-system-ctrl" for BG2CD
85 "marvell,berlin2q-system-ctrl" for BG2Q
86 * the second and third values must be:
87 "simple-mfd", "syscon"
88 - reg: address and length of the system control register set
90 * Clock provider binding
92 As clock related registers are spread among the chip control registers, the
93 chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
94 SoCs share the same IP for PLLs and clocks, with some minor differences in
95 features and register layout.
98 - #clock-cells: shall be set to 1
99 - clocks: clock specifiers referencing the core clock input clocks
100 - clock-names: array of strings describing the input clock specifiers above.
101 Allowed clock-names for the reference clocks are
102 "refclk" for the SoCs osciallator input on all SoCs,
103 and SoC-specific input clocks for
104 BG2/BG2CD: "video_ext0" for the external video clock input
106 Clocks provided by core clocks shall be referenced by a clock specifier
107 indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
108 for the corresponding index mapping.
110 * Pin controller binding
112 Pin control registers are part of both register sets, chip control and system
113 control. The pins controlled are organized in groups, so no actual pin
114 information is needed.
116 A pin-controller node should contain subnodes representing the pin group
117 configurations, one per function. Each subnode has the group name and the muxing
120 Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
121 a 'function' in the pin-controller subsystem.
123 Required subnode-properties:
124 - groups: a list of strings describing the group names.
125 - function: a string describing the function used to mux the groups.
129 chip: chip-control@ea0000 {
130 compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon";
132 reg = <0xea0000 0x400>;
133 clocks = <&refclk>, <&externaldev 0>;
134 clock-names = "refclk", "video_ext0";
136 spi1_pmux: spi1-pmux {
142 sysctrl: system-controller@d000 {
143 compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon";
144 reg = <0xd000 0x100>;
146 uart0_pmux: uart0-pmux {
151 uart1_pmux: uart1-pmux {
156 uart2_pmux: uart2-pmux {