1 Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
3 DisplayPort is industry standard to accommodate the growing board adoption
4 of digital display technology within the PC and CE industries.
5 It consolidates the internal and external connection methods to reduce device
6 complexity and cost. It also supports necessary features for important cross
7 industry applications and provides performance scalability to enable the next
8 generation of displays that feature higher color depths, refresh rates, and
11 eDP (embedded display port) device is compliant with Embedded DisplayPort
13 - DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
14 - DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
16 eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
18 The Exynos display port interface should be configured based on
19 the type of panel connected to it.
23 -dptx-phy node(defined inside dp-controller node)
25 For the DP-PHY initialization, we use the dptx-phy node.
26 Required properties for dptx-phy: deprecated, use phys and phy-names
28 Base address of DP PHY register.
29 -samsung,enable-mask: deprecated
30 The bit-mask used to enable/disable DP PHY.
32 For the Panel initialization, we read data from dp-controller node.
33 Required properties for dp-controller:
35 should be "samsung,exynos5-dp".
37 physical base address of the controller and length
38 of memory mapped region.
40 interrupt combiner values.
42 from common clock binding: handle to dp clock.
44 from common clock binding: Shall be "dp".
46 phandle to Interrupt combiner node.
48 from general PHY binding: the phandle for the PHY device.
50 from general PHY binding: Should be "dp".
52 input video data format.
53 COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
54 -samsung,dynamic-range:
55 dynamic range for input video data.
58 YCbCr co-efficients for input video.
59 COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
61 number of bits per colour component.
62 COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
64 link rate supported by the panel.
65 LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
67 number of lanes supported by the panel.
68 LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
69 - display-timings: timings for the connected panel as described by
70 Documentation/devicetree/bindings/display/display-timing.txt
72 Optional properties for dp-controller:
75 Progressive if defined, Interlaced if not defined
77 VSYNC polarity configuration.
78 High if defined, Low if not defined
80 HSYNC polarity configuration.
81 High if defined, Low if not defined
84 Indicates which GPIO should be used for hotplug
87 Device node can contain video interface port nodes according to [1].
88 The following are properties specific to those nodes:
90 endpoint node connected to bridge or panel node:
91 - remote-endpoint: specifies the endpoint in panel or bridge node.
92 This node is required in all kinds of exynos dp
93 to represent the connection between dp and bridge
96 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
100 SOC specific portion:
102 compatible = "samsung,exynos5-dp";
103 reg = <0x145b0000 0x10000>;
105 interrupt-parent = <&combiner>;
106 clocks = <&clock 342>;
113 Board Specific portion:
115 samsung,color-space = <0>;
116 samsung,dynamic-range = <0>;
117 samsung,ycbcr-coeff = <0>;
118 samsung,color-depth = <1>;
119 samsung,link-rate = <0x0a>;
120 samsung,lane-count = <4>;
123 native-mode = <&lcd_timing>;
124 lcd_timing: 1366x768 {
125 clock-frequency = <70589280>;
140 remote-endpoint = <&dp_in>;
149 remote-endpoint = <&dp_out>;