1 Specifying GPIO information for devices
2 ============================================
7 Nodes that makes use of GPIOs should specify them using one or more
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
18 for compatibility reasons (resolving to the "gpios" property), it is not allowed
19 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
20 bindings use it, but are only supported for compatibility reasons and should not
21 be used for newer bindings since it has been deprecated.
23 GPIO properties can contain one or more GPIO phandles, but only in exceptional
24 cases should they contain more than one. If your device uses several GPIOs with
25 distinct functions, reference each of them under its own property, giving it a
26 meaningful name. The only case where an array of GPIOs is accepted is when
27 several GPIOs serve the same function (e.g. a parallel data line).
29 The exact purpose of each gpios property must be documented in the device tree
30 binding of the device.
32 The following example could be used to describe GPIO pins used as device enable
33 and bit-banged data signals:
45 enable-gpios = <&gpio2 2>;
46 data-gpios = <&gpio1 12 0>,
51 Note that gpio-specifier length is controller dependent. In the
52 above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
55 gpio-specifier may encode: bank, pin position inside the bank,
56 whether pin is open-drain and whether pin is logically inverted.
58 Exact meaning of each specifier cell is controller specific, and must
59 be documented in the device tree binding for the device.
61 Most controllers are however specifying a generic flag bitfield
62 in the last cell, so for these, use the macros defined in
63 include/dt-bindings/gpio/gpio.h whenever possible:
65 Example of a node using GPIOs:
68 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
71 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
72 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
74 Optional standard bitfield specifiers for the last cell:
76 - Bit 0: 0 means active high, 1 means active low
77 - Bit 1: 1 means single-ended wiring, see:
78 https://en.wikipedia.org/wiki/Single-ended_triode
79 When used with active-low, this means open drain/collector, see:
80 https://en.wikipedia.org/wiki/Open_collector
81 When used with active-high, this means open source/emitter
83 1.1) GPIO specifier best practices
84 ----------------------------------
86 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
87 high or active-low. If it does, the following best practices should be
90 The gpio-specifier's polarity flag should represent the physical level at the
91 GPIO controller that achieves (or represents, for inputs) a logically asserted
92 value at the device. The exact definition of logically asserted should be
93 defined by the binding for the device. If the board inverts the signal between
94 the GPIO controller and the device, then the gpio-specifier will represent the
95 opposite physical level than the signal at the device's pin.
97 When the device's signal polarity is configurable, the binding for the
100 a) Define a single static polarity for the signal, with the expectation that
101 any software using that binding would statically program the device to use
102 that signal polarity.
104 The static choice of polarity may be either:
106 a1) (Preferred) Dictated by a binding-specific DT property.
110 a2) Defined statically by the DT binding itself.
112 In particular, the polarity cannot be derived from the gpio-specifier, since
113 that would prevent the DT from separately representing the two orthogonal
114 concepts of configurable signal polarity in the device, and possible board-
115 level signal inversion.
119 b) Pick a single option for device signal polarity, and document this choice
120 in the binding. The gpio-specifier should represent the polarity of the signal
121 (at the GPIO controller) assuming that the device is configured for this
122 particular signal polarity choice. If software chooses to program the device
123 to generate or receive a signal of the opposite polarity, software will be
124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
127 2) gpio-controller nodes
128 ------------------------
130 Every GPIO controller node must contain both an empty "gpio-controller"
131 property, and a #gpio-cells integer property, which indicates the number of
132 cells in a gpio-specifier.
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
135 instance of a hardware IP core on a silicon die, usually exposed to the
136 programmer as a coherent range of I/O addresses. Usually each such bank is
137 exposed in the device tree as an individual gpio-controller node, reflecting
138 the fact that the hardware was synthesized by reusing the same IP block a
141 Optionally, a GPIO controller may have a "ngpios" property. This property
142 indicates the number of in-use slots of available slots for GPIOs. The
143 typical example is something like this: the hardware register is 32 bits
144 wide, but only 18 of the bits have a physical counterpart. The driver is
145 generally written so that all 32 bits can be used, but the IP block is reused
146 in a lot of designs, some using all 32 bits, some using 18 and some using
147 12. In this case, setting "ngpios = <18>;" informs the driver that only the
148 first 18 GPIOs, at local offset 0 .. 17, are in use.
150 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
151 additional bitmask is needed to specify which GPIOs are actually in use,
152 and which are dummies. The bindings for this case has not yet been
153 specified, but should be specified if/when such hardware appears.
157 gpio-controller@00000000 {
159 reg = <0x00000000 0x1000>;
165 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
166 providing automatic GPIO request and configuration as part of the
167 gpio-controller's driver probe function.
169 Each GPIO hog definition is represented as a child node of the GPIO controller.
171 - gpio-hog: A property specifying that this child node represent a GPIO hog.
172 - gpios: Store the GPIO information (id, flags, ...). Shall contain the
173 number of cells specified in its parent node (GPIO controller
175 Only one of the following properties scanned in the order shown below.
176 This means that when multiple properties are present they will be searched
177 in the order presented below and the first match is taken as the intended
179 - input: A property specifying to set the GPIO direction as input.
180 - output-low A property specifying to set the GPIO direction as output with
182 - output-high A property specifying to set the GPIO direction as output with
186 - line-name: The GPIO label name. If not present the node name is used.
188 Example of two SOC GPIO banks defined as gpio-controller nodes:
190 qe_pio_a: gpio-controller@1400 {
191 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
200 line-name = "foo-bar-gpio";
204 qe_pio_e: gpio-controller@1460 {
205 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
211 2.1) gpio- and pin-controller interaction
212 -----------------------------------------
214 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
215 on the package via a pin controller. This allows muxing those pins between
216 GPIO and other functions.
218 It is useful to represent which GPIOs correspond to which pins on which pin
219 controllers. The gpio-ranges property described below represents this, and
220 contains information structures as follows:
222 gpio-range-list ::= <single-gpio-range> [gpio-range-list]
223 single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
224 numeric-gpio-range ::=
225 <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
226 named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
227 pinctrl-phandle : phandle to pin controller node
228 gpio-base : Base GPIO ID in the GPIO controller
229 pinctrl-base : Base pinctrl pin ID in the pin controller
230 count : The number of GPIOs/pins in this range
232 The "pin controller node" mentioned above must conform to the bindings
233 described in ../pinctrl/pinctrl-bindings.txt.
235 In case named gpio ranges are used (ranges with both <pinctrl-base> and
236 <count> set to 0), the property gpio-ranges-group-names contains one string
237 for every single-gpio-range in gpio-ranges:
238 gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
239 gpiorange-name : Name of the pingroup associated to the GPIO range in
240 the respective pin controller.
242 Elements of gpiorange-names-list corresponding to numeric ranges contain
243 the empty string. Elements of gpiorange-names-list corresponding to named
244 ranges contain the name of a pin group defined in the respective pin
245 controller. The number of pins/GPIOs in the range is the number of pins in
248 Previous versions of this binding required all pin controller nodes that
249 were referenced by any gpio-ranges property to contain a property named
250 #gpio-range-cells with value <3>. This requirement is now deprecated.
251 However, that property may still exist in older device trees for
252 compatibility reasons, and would still be required even in new device
253 trees that need to be compatible with older software.
257 qe_pio_e: gpio-controller@1460 {
259 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
262 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
265 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
266 pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
271 gpio_pio_i: gpio-controller@14B0 {
273 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
276 gpio-ranges = <&pinctrl1 0 20 10>,
280 gpio-ranges-group-names = "",
286 Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
287 ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
288 are named "foo" and "bar".