1 PINCTRL (PIN CONTROL) subsystem
2 This document outlines the pin control subsystem in Linux
4 This subsystem deals with:
6 - Enumerating and naming controllable pins
8 - Multiplexing of pins, pads, fingers (etc) see below for details
10 - Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Definition of PIN CONTROLLER:
19 - A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
21 set drive strength etc for individual pins or groups of pins.
25 - PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
32 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33 pin control framework, and this descriptor contains an array of pin descriptors
34 describing the pins handled by this specific pin controller.
36 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
56 To register a pin controller and name all the pins on this package we can do
59 #include <linux/pinctrl/pinctrl.h>
61 const struct pinctrl_pin_desc foo_pins[] = {
66 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
71 static struct pinctrl_desc foo_desc = {
74 .npins = ARRAY_SIZE(foo_pins),
79 int __init foo_probe(void)
81 struct pinctrl_dev *pctl;
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
85 pr_err("could not register foo pin driver\n");
88 To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89 selected drivers, you need to select them from your machine's Kconfig entry,
90 since these are so tightly integrated with the machines they are used on.
91 See for example arch/arm/mach-u300/Kconfig for an example.
93 Pins usually have fancier names than this. You can find these in the dataheet
94 for your chip. Notice that the core pinctrl.h file provides a fancy macro
95 called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
96 the pins from 0 in the upper left corner to 63 in the lower right corner.
97 This enumeration was arbitrarily chosen, in practice you need to think
98 through your numbering system so that it matches the layout of registers
99 and such things in your driver, or the code may become complicated. You must
100 also consider matching of offsets to the GPIO ranges that may be handled by
103 For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104 like this, walking around the edge of the chip, which seems to be industry
105 standard too (all these pads had names, too):
119 Many controllers need to deal with groups of pins, so the pin controller
120 subsystem has a mechanism for enumerating groups of pins and retrieving the
121 actual enumerated pins that are part of a certain group.
123 For example, say that we have a group of pins dealing with an SPI interface
124 on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
127 These two groups are presented to the pin control subsystem by implementing
128 some generic pinctrl_ops like this:
130 #include <linux/pinctrl/pinctrl.h>
134 const unsigned int *pins;
135 const unsigned num_pins;
138 static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139 static const unsigned int i2c0_pins[] = { 24, 25 };
141 static const struct foo_group foo_groups[] = {
145 .num_pins = ARRAY_SIZE(spi0_pins),
150 .num_pins = ARRAY_SIZE(i2c0_pins),
155 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
157 return ARRAY_SIZE(foo_groups);
160 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
163 return foo_groups[selector].name;
166 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167 unsigned ** const pins,
168 unsigned * const num_pins)
170 *pins = (unsigned *) foo_groups[selector].pins;
171 *num_pins = foo_groups[selector].num_pins;
175 static struct pinctrl_ops foo_pctrl_ops = {
176 .get_groups_count = foo_get_groups_count,
177 .get_group_name = foo_get_group_name,
178 .get_group_pins = foo_get_group_pins,
182 static struct pinctrl_desc foo_desc = {
184 .pctlops = &foo_pctrl_ops,
187 The pin control subsystem will call the .get_groups_count() function to
188 determine total number of legal selectors, then it will call the other functions
189 to retrieve the name and pins of the group. Maintaining the data structure of
190 the groups is up to the driver, this is just a simple example - in practice you
191 may need more entries in your group structure, for example specific register
192 ranges associated with each group and so on.
198 Pins can sometimes be software-configured in an various ways, mostly related
199 to their electronic properties when used as inputs or outputs. For example you
200 may be able to make an output pin high impedance, or "tristate" meaning it is
201 effectively disconnected. You may be able to connect an input pin to VDD or GND
202 using a certain resistor value - pull up and pull down - so that the pin has a
203 stable value when nothing is driving the rail it is connected to, or when it's
206 Pin configuration can be programmed either using the explicit APIs described
207 immediately below, or by adding configuration entries into the mapping table;
208 see section "Board/machine configuration" below.
210 For example, a platform may do the following to pull up a pin to VDD:
212 #include <linux/pinctrl/consumer.h>
214 ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
216 The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
217 above, is entirely defined by the pin controller driver.
219 The pin configuration driver implements callbacks for changing pin
220 configuration in the pin controller ops like this:
222 #include <linux/pinctrl/pinctrl.h>
223 #include <linux/pinctrl/pinconf.h>
224 #include "platform_x_pindefs.h"
226 static int foo_pin_config_get(struct pinctrl_dev *pctldev,
228 unsigned long *config)
230 struct my_conftype conf;
232 ... Find setting for pin @ offset ...
234 *config = (unsigned long) conf;
237 static int foo_pin_config_set(struct pinctrl_dev *pctldev,
239 unsigned long config)
241 struct my_conftype *conf = (struct my_conftype *) config;
244 case PLATFORM_X_PULL_UP:
250 static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
252 unsigned long *config)
257 static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
259 unsigned long config)
264 static struct pinconf_ops foo_pconf_ops = {
265 .pin_config_get = foo_pin_config_get,
266 .pin_config_set = foo_pin_config_set,
267 .pin_config_group_get = foo_pin_config_group_get,
268 .pin_config_group_set = foo_pin_config_group_set,
271 /* Pin config operations are handled by some pin controller */
272 static struct pinctrl_desc foo_desc = {
274 .confops = &foo_pconf_ops,
277 Since some controllers have special logic for handling entire groups of pins
278 they can exploit the special whole-group pin control function. The
279 pin_config_group_set() callback is allowed to return the error code -EAGAIN,
280 for groups it does not want to handle, or if it just wants to do some
281 group-level handling and then fall through to iterate over all pins, in which
282 case each individual pin will be treated by separate pin_config_set() calls as
286 Interaction with the GPIO subsystem
287 ===================================
289 The GPIO drivers may want to perform operations of various types on the same
290 physical pins that are also registered as pin controller pins.
292 First and foremost, the two subsystems can be used as completely orthogonal,
293 see the section named "pin control requests from drivers" and
294 "drivers needing both pin control and GPIOs" below for details. But in some
295 situations a cross-subsystem mapping between pins and GPIOs is needed.
297 Since the pin controller subsystem have its pinspace local to the pin
298 controller we need a mapping so that the pin control subsystem can figure out
299 which pin controller handles control of a certain GPIO pin. Since a single
300 pin controller may be muxing several GPIO ranges (typically SoCs that have
301 one set of pins but internally several GPIO silicon blocks, each modeled as
302 a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
305 struct gpio_chip chip_a;
306 struct gpio_chip chip_b;
308 static struct pinctrl_gpio_range gpio_range_a = {
317 static struct pinctrl_gpio_range gpio_range_b = {
327 struct pinctrl_dev *pctl;
329 pinctrl_add_gpio_range(pctl, &gpio_range_a);
330 pinctrl_add_gpio_range(pctl, &gpio_range_b);
333 So this complex system has one pin controller handling two different
334 GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
335 "chip b" have different .pin_base, which means a start pin number of the
338 The GPIO range of "chip a" starts from the GPIO base of 32 and actual
339 pin range also starts from 32. However "chip b" has different starting
340 offset for the GPIO range and pin range. The GPIO range of "chip b" starts
341 from GPIO number 48, while the pin range of "chip b" starts from 64.
343 We can convert a gpio number to actual pin number using this "pin_base".
344 They are mapped in the global GPIO pin space at:
347 - GPIO range : [32 .. 47]
348 - pin range : [32 .. 47]
350 - GPIO range : [48 .. 55]
351 - pin range : [64 .. 71]
353 The above examples assume the mapping between the GPIOs and pins is
354 linear. If the mapping is sparse or haphazard, an array of arbitrary pin
355 numbers can be encoded in the range like this:
357 static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
359 static struct pinctrl_gpio_range gpio_range = {
364 .npins = ARRAY_SIZE(range_pins),
368 In this case the pin_base property will be ignored.
370 When GPIO-specific functions in the pin control subsystem are called, these
371 ranges will be used to look up the appropriate pin controller by inspecting
372 and matching the pin to the pin ranges across all controllers. When a
373 pin controller handling the matching range is found, GPIO-specific functions
374 will be called on that specific pin controller.
376 For all functionalities dealing with pin biasing, pin muxing etc, the pin
377 controller subsystem will look up the corresponding pin number from the passed
378 in gpio number, and use the range's internals to retrive a pin number. After
379 that, the subsystem passes it on to the pin control driver, so the driver
380 will get an pin number into its handled number range. Further it is also passed
381 the range ID value, so that the pin controller knows which range it should
384 Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
385 section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
386 pinctrl and gpio drivers.
392 These calls use the pinmux_* naming prefix. No other calls should use that
399 PINMUX, also known as padmux, ballmux, alternate functions or mission modes
400 is a way for chip vendors producing some kind of electrical packages to use
401 a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
402 functions, depending on the application. By "application" in this context
403 we usually mean a way of soldering or wiring the package into an electronic
404 system, even though the framework makes it possible to also change the function
407 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
411 8 | o | o o o o o o o
413 7 | o | o o o o o o o
415 6 | o | o o o o o o o
417 5 | o | o | o o o o o o
419 4 o o o o o o | o | o
421 3 o o o o o o | o | o
423 2 o o o o o o | o | o
424 +-------+-------+-------+---+---+
425 1 | o o | o o | o o | o | o |
426 +-------+-------+-------+---+---+
428 This is not tetris. The game to think of is chess. Not all PGA/BGA packages
429 are chessboard-like, big ones have "holes" in some arrangement according to
430 different design patterns, but we're using this as a simple example. Of the
431 pins you see some will be taken by things like a few VCC and GND to feed power
432 to the chip, and quite a few will be taken by large ports like an external
433 memory interface. The remaining pins will often be subject to pin multiplexing.
435 The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
436 its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
437 pinctrl_register_pins() and a suitable data set as shown earlier.
439 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
440 (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
441 some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
442 be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
443 we cannot use the SPI port and I2C port at the same time. However in the inside
444 of the package the silicon performing the SPI logic can alternatively be routed
445 out on pins { G4, G3, G2, G1 }.
447 On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
448 special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
449 consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
450 { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
451 port on pins { G4, G3, G2, G1 } of course.
453 This way the silicon blocks present inside the chip can be multiplexed "muxed"
454 out on different pin ranges. Often contemporary SoC (systems on chip) will
455 contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
456 different pins by pinmux settings.
458 Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
459 common to be able to use almost any pin as a GPIO pin if it is not currently
460 in use by some other I/O port.
466 The purpose of the pinmux functionality in the pin controller subsystem is to
467 abstract and provide pinmux settings to the devices you choose to instantiate
468 in your machine configuration. It is inspired by the clk, GPIO and regulator
469 subsystems, so devices will request their mux setting, but it's also possible
470 to request a single pin for e.g. GPIO.
474 - FUNCTIONS can be switched in and out by a driver residing with the pin
475 control subsystem in the drivers/pinctrl/* directory of the kernel. The
476 pin control driver knows the possible functions. In the example above you can
477 identify three pinmux functions, one for spi, one for i2c and one for mmc.
479 - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
480 In this case the array could be something like: { spi0, i2c0, mmc0 }
481 for the three available functions.
483 - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
484 function is *always* associated with a certain set of pin groups, could
485 be just a single one, but could also be many. In the example above the
486 function i2c is associated with the pins { A5, B5 }, enumerated as
487 { 24, 25 } in the controller pin space.
489 The Function spi is associated with pin groups { A8, A7, A6, A5 }
490 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
491 { 38, 46, 54, 62 } respectively.
493 Group names must be unique per pin controller, no two groups on the same
494 controller may have the same name.
496 - The combination of a FUNCTION and a PIN GROUP determine a certain function
497 for a certain set of pins. The knowledge of the functions and pin groups
498 and their machine-specific particulars are kept inside the pinmux driver,
499 from the outside only the enumerators are known, and the driver core can:
501 - Request the name of a function with a certain selector (>= 0)
502 - A list of groups associated with a certain function
503 - Request that a certain group in that list to be activated for a certain
506 As already described above, pin groups are in turn self-descriptive, so
507 the core will retrieve the actual pin range in a certain group from the
510 - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
511 device by the board file, device tree or similar machine setup configuration
512 mechanism, similar to how regulators are connected to devices, usually by
513 name. Defining a pin controller, function and group thus uniquely identify
514 the set of pins to be used by a certain device. (If only one possible group
515 of pins is available for the function, no group name need to be supplied -
516 the core will simply select the first and only group available.)
518 In the example case we can define that this particular machine shall
519 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
520 fi2c0 group gi2c0, on the primary pin controller, we get mappings
524 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
525 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
528 Every map must be assigned a state name, pin controller, device and
529 function. The group is not compulsory - if it is omitted the first group
530 presented by the driver as applicable for the function will be selected,
531 which is useful for simple cases.
533 It is possible to map several groups to the same combination of device,
534 pin controller and function. This is for cases where a certain function on
535 a certain pin controller may use different sets of pins in different
538 - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
539 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
540 other device mux setting or GPIO pin request has already taken your physical
541 pin, you will be denied the use of it. To get (activate) a new setting, the
542 old one has to be put (deactivated) first.
544 Sometimes the documentation and hardware registers will be oriented around
545 pads (or "fingers") rather than pins - these are the soldering surfaces on the
546 silicon inside the package, and may or may not match the actual number of
547 pins/balls underneath the capsule. Pick some enumeration that makes sense to
548 you. Define enumerators only for the pins you can control if that makes sense.
552 We assume that the number of possible function maps to pin groups is limited by
553 the hardware. I.e. we assume that there is no system where any function can be
554 mapped to any pin, like in a phone exchange. So the available pins groups for
555 a certain function will be limited to a few choices (say up to eight or so),
556 not hundreds or any amount of choices. This is the characteristic we have found
557 by inspecting available pinmux hardware, and a necessary assumption since we
558 expect pinmux drivers to present *all* possible function vs pin group mappings
565 The pinmux core takes care of preventing conflicts on pins and calling
566 the pin controller driver to execute different settings.
568 It is the responsibility of the pinmux driver to impose further restrictions
569 (say for example infer electronic limitations due to load etc) to determine
570 whether or not the requested function can actually be allowed, and in case it
571 is possible to perform the requested mux setting, poke the hardware so that
574 Pinmux drivers are required to supply a few callback functions, some are
575 optional. Usually the enable() and disable() functions are implemented,
576 writing values into some certain registers to activate a certain mux setting
579 A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
580 into some register named MUX to select a certain function with a certain
581 group of pins would work something like this:
583 #include <linux/pinctrl/pinctrl.h>
584 #include <linux/pinctrl/pinmux.h>
588 const unsigned int *pins;
589 const unsigned num_pins;
592 static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
593 static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
594 static const unsigned i2c0_pins[] = { 24, 25 };
595 static const unsigned mmc0_1_pins[] = { 56, 57 };
596 static const unsigned mmc0_2_pins[] = { 58, 59 };
597 static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
599 static const struct foo_group foo_groups[] = {
601 .name = "spi0_0_grp",
603 .num_pins = ARRAY_SIZE(spi0_0_pins),
606 .name = "spi0_1_grp",
608 .num_pins = ARRAY_SIZE(spi0_1_pins),
613 .num_pins = ARRAY_SIZE(i2c0_pins),
616 .name = "mmc0_1_grp",
618 .num_pins = ARRAY_SIZE(mmc0_1_pins),
621 .name = "mmc0_2_grp",
623 .num_pins = ARRAY_SIZE(mmc0_2_pins),
626 .name = "mmc0_3_grp",
628 .num_pins = ARRAY_SIZE(mmc0_3_pins),
633 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
635 return ARRAY_SIZE(foo_groups);
638 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
641 return foo_groups[selector].name;
644 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
645 unsigned ** const pins,
646 unsigned * const num_pins)
648 *pins = (unsigned *) foo_groups[selector].pins;
649 *num_pins = foo_groups[selector].num_pins;
653 static struct pinctrl_ops foo_pctrl_ops = {
654 .get_groups_count = foo_get_groups_count,
655 .get_group_name = foo_get_group_name,
656 .get_group_pins = foo_get_group_pins,
659 struct foo_pmx_func {
661 const char * const *groups;
662 const unsigned num_groups;
665 static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
666 static const char * const i2c0_groups[] = { "i2c0_grp" };
667 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
670 static const struct foo_pmx_func foo_functions[] = {
673 .groups = spi0_groups,
674 .num_groups = ARRAY_SIZE(spi0_groups),
678 .groups = i2c0_groups,
679 .num_groups = ARRAY_SIZE(i2c0_groups),
683 .groups = mmc0_groups,
684 .num_groups = ARRAY_SIZE(mmc0_groups),
688 int foo_get_functions_count(struct pinctrl_dev *pctldev)
690 return ARRAY_SIZE(foo_functions);
693 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
695 return foo_functions[selector].name;
698 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
699 const char * const **groups,
700 unsigned * const num_groups)
702 *groups = foo_functions[selector].groups;
703 *num_groups = foo_functions[selector].num_groups;
707 int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
710 u8 regbit = (1 << selector + group);
712 writeb((readb(MUX)|regbit), MUX)
716 void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
719 u8 regbit = (1 << selector + group);
721 writeb((readb(MUX) & ~(regbit)), MUX)
725 struct pinmux_ops foo_pmxops = {
726 .get_functions_count = foo_get_functions_count,
727 .get_function_name = foo_get_fname,
728 .get_function_groups = foo_get_groups,
729 .enable = foo_enable,
730 .disable = foo_disable,
733 /* Pinmux operations are handled by some pin controller */
734 static struct pinctrl_desc foo_desc = {
736 .pctlops = &foo_pctrl_ops,
737 .pmxops = &foo_pmxops,
740 In the example activating muxing 0 and 1 at the same time setting bits
741 0 and 1, uses one pin in common so they would collide.
743 The beauty of the pinmux subsystem is that since it keeps track of all
744 pins and who is using them, it will already have denied an impossible
745 request like that, so the driver does not need to worry about such
746 things - when it gets a selector passed in, the pinmux subsystem makes
747 sure no other device or GPIO assignment is already using the selected
748 pins. Thus bits 0 and 1 in the control register will never be set at the
751 All the above functions are mandatory to implement for a pinmux driver.
754 Pin control interaction with the GPIO subsystem
755 ===============================================
757 Note that the following implies that the use case is to use a certain pin
758 from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
759 and similar functions. There are cases where you may be using something
760 that your datasheet calls "GPIO mode" but actually is just an electrical
761 configuration for a certain device. See the section below named
762 "GPIO mode pitfalls" for more details on this scenario.
764 The public pinmux API contains two functions named pinctrl_request_gpio()
765 and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
766 gpiolib-based drivers as part of their gpio_request() and
767 gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
768 shall only be called from within respective gpio_direction_[input|output]
769 gpiolib implementation.
771 NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
772 controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
773 that driver request proper muxing and other control for its pins.
775 The function list could become long, especially if you can convert every
776 individual pin into a GPIO pin independent of any other pins, and then try
777 the approach to define every pin as a function.
779 In this case, the function array would become 64 entries for each GPIO
780 setting and then the device functions.
782 For this reason there are two functions a pin control driver can implement
783 to enable only GPIO on an individual pin: .gpio_request_enable() and
784 .gpio_disable_free().
786 This function will pass in the affected GPIO range identified by the pin
787 controller core, so you know which GPIO pins are being affected by the request
790 If your driver needs to have an indication from the framework of whether the
791 GPIO pin shall be used for input or output you can implement the
792 .gpio_set_direction() function. As described this shall be called from the
793 gpiolib driver and the affected GPIO range, pin offset and desired direction
794 will be passed along to this function.
796 Alternatively to using these special functions, it is fully allowed to use
797 named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
798 obtain the function "gpioN" where "N" is the global GPIO pin number if no
799 special GPIO-handler is registered.
805 Sometime the developer may be confused by a datasheet talking about a pin
806 being possible to set into "GPIO mode". It appears that what hardware
807 engineers mean with "GPIO mode" is not necessarily the use case that is
808 implied in the kernel interface <linux/gpio.h>: a pin that you grab from
809 kernel code and then either listen for input or drive high/low to
810 assert/deassert some external line.
812 Rather hardware engineers think that "GPIO mode" means that you can
813 software-control a few electrical properties of the pin that you would
814 not be able to control if the pin was in some other mode, such as muxed in
817 Example: a pin is usually muxed in to be used as a UART TX line. But during
818 system sleep, we need to put this pin into "GPIO mode" and ground it.
820 If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
821 to think that you need to come up with something real complex, that the
822 pin shall be used for UART TX and GPIO at the same time, that you will grab
823 a pin control handle and set it to a certain state to enable UART TX to be
824 muxed in, then twist it over to GPIO mode and use gpio_direction_output()
825 to drive it low during sleep, then mux it over to UART TX again when you
826 wake up and maybe even gpio_request/gpio_free as part of this cycle. This
827 all gets very complicated.
829 The solution is to not think that what the datasheet calls "GPIO mode"
830 has to be handled by the <linux/gpio.h> interface. Instead view this as
831 a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
832 and you find this in the documentation:
834 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
835 1 to indicate high level, argument 0 to indicate low level.
837 So it is perfectly possible to push a pin into "GPIO mode" and drive the
838 line low as part of the usual pin control map. So for example your UART
839 driver may look like this:
841 #include <linux/pinctrl/consumer.h>
843 struct pinctrl *pinctrl;
844 struct pinctrl_state *pins_default;
845 struct pinctrl_state *pins_sleep;
847 pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
848 pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
851 retval = pinctrl_select_state(pinctrl, pins_default);
853 retval = pinctrl_select_state(pinctrl, pins_sleep);
855 And your machine configuration may look like this:
856 --------------------------------------------------
858 static unsigned long uart_default_mode[] = {
859 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
862 static unsigned long uart_sleep_mode[] = {
863 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
866 static struct pinctrl_map __initdata pinmap[] = {
867 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
869 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
870 "UART_TX_PIN", uart_default_mode),
871 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
872 "u0_group", "gpio-mode"),
873 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
874 "UART_TX_PIN", uart_sleep_mode),
878 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
881 Here the pins we want to control are in the "u0_group" and there is some
882 function called "u0" that can be enabled on this group of pins, and then
883 everything is UART business as usual. But there is also some function
884 named "gpio-mode" that can be mapped onto the same pins to move them into
887 This will give the desired effect without any bogus interaction with the
888 GPIO subsystem. It is just an electrical configuration used by that device
889 when going to sleep, it might imply that the pin is set into something the
890 datasheet calls "GPIO mode" but that is not the point: it is still used
891 by that UART device to control the pins that pertain to that very UART
892 driver, putting them into modes needed by the UART. GPIO in the Linux
893 kernel sense are just some 1-bit line, and is a different use case.
895 How the registers are poked to attain the push/pull and output low
896 configuration and the muxing of the "u0" or "gpio-mode" group onto these
897 pins is a question for the driver.
899 Some datasheets will be more helpful and refer to the "GPIO mode" as
900 "low power mode" rather than anything to do with GPIO. This often means
901 the same thing electrically speaking, but in this latter case the
902 software engineers will usually quickly identify that this is some
903 specific muxing/configuration rather than anything related to the GPIO
907 Board/machine configuration
908 ==================================
910 Boards and machines define how a certain complete running system is put
911 together, including how GPIOs and devices are muxed, how regulators are
912 constrained and how the clock tree looks. Of course pinmux settings are also
915 A pin controller configuration for a machine looks pretty much like a simple
916 regulator configuration, so for the example array above we want to enable i2c
917 and spi on the second function mapping:
919 #include <linux/pinctrl/machine.h>
921 static const struct pinctrl_map mapping[] __initconst = {
923 .dev_name = "foo-spi.0",
924 .name = PINCTRL_STATE_DEFAULT,
925 .type = PIN_MAP_TYPE_MUX_GROUP,
926 .ctrl_dev_name = "pinctrl-foo",
927 .data.mux.function = "spi0",
930 .dev_name = "foo-i2c.0",
931 .name = PINCTRL_STATE_DEFAULT,
932 .type = PIN_MAP_TYPE_MUX_GROUP,
933 .ctrl_dev_name = "pinctrl-foo",
934 .data.mux.function = "i2c0",
937 .dev_name = "foo-mmc.0",
938 .name = PINCTRL_STATE_DEFAULT,
939 .type = PIN_MAP_TYPE_MUX_GROUP,
940 .ctrl_dev_name = "pinctrl-foo",
941 .data.mux.function = "mmc0",
945 The dev_name here matches to the unique device name that can be used to look
946 up the device struct (just like with clockdev or regulators). The function name
947 must match a function provided by the pinmux driver handling this pin range.
949 As you can see we may have several pin controllers on the system and thus
950 we need to specify which one of them that contain the functions we wish
953 You register this pinmux mapping to the pinmux subsystem by simply:
955 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
957 Since the above construct is pretty common there is a helper macro to make
958 it even more compact which assumes you want to use pinctrl-foo and position
959 0 for mapping, for example:
961 static struct pinctrl_map __initdata mapping[] = {
962 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
965 The mapping table may also contain pin configuration entries. It's common for
966 each pin/group to have a number of configuration entries that affect it, so
967 the table entries for configuration reference an array of config parameters
968 and values. An example using the convenience macros is shown below:
970 static unsigned long i2c_grp_configs[] = {
975 static unsigned long i2c_pin_configs[] = {
980 static struct pinctrl_map __initdata mapping[] = {
981 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
982 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
983 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
984 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
987 Finally, some devices expect the mapping table to contain certain specific
988 named states. When running on hardware that doesn't need any pin controller
989 configuration, the mapping table must still contain those named states, in
990 order to explicitly indicate that the states were provided and intended to
991 be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
992 a named state without causing any pin controller to be programmed:
994 static struct pinctrl_map __initdata mapping[] = {
995 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1002 As it is possible to map a function to different groups of pins an optional
1003 .group can be specified like this:
1007 .dev_name = "foo-spi.0",
1008 .name = "spi0-pos-A",
1009 .type = PIN_MAP_TYPE_MUX_GROUP,
1010 .ctrl_dev_name = "pinctrl-foo",
1012 .group = "spi0_0_grp",
1015 .dev_name = "foo-spi.0",
1016 .name = "spi0-pos-B",
1017 .type = PIN_MAP_TYPE_MUX_GROUP,
1018 .ctrl_dev_name = "pinctrl-foo",
1020 .group = "spi0_1_grp",
1024 This example mapping is used to switch between two positions for spi0 at
1025 runtime, as described further below under the heading "Runtime pinmuxing".
1027 Further it is possible for one named state to affect the muxing of several
1028 groups of pins, say for example in the mmc0 example above, where you can
1029 additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1030 three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1031 case), we define a mapping like this:
1035 .dev_name = "foo-mmc.0",
1037 .type = PIN_MAP_TYPE_MUX_GROUP,
1038 .ctrl_dev_name = "pinctrl-foo",
1040 .group = "mmc0_1_grp",
1043 .dev_name = "foo-mmc.0",
1045 .type = PIN_MAP_TYPE_MUX_GROUP,
1046 .ctrl_dev_name = "pinctrl-foo",
1048 .group = "mmc0_1_grp",
1051 .dev_name = "foo-mmc.0",
1053 .type = PIN_MAP_TYPE_MUX_GROUP,
1054 .ctrl_dev_name = "pinctrl-foo",
1056 .group = "mmc0_2_grp",
1059 .dev_name = "foo-mmc.0",
1061 .type = PIN_MAP_TYPE_MUX_GROUP,
1062 .ctrl_dev_name = "pinctrl-foo",
1064 .group = "mmc0_1_grp",
1067 .dev_name = "foo-mmc.0",
1069 .type = PIN_MAP_TYPE_MUX_GROUP,
1070 .ctrl_dev_name = "pinctrl-foo",
1072 .group = "mmc0_2_grp",
1075 .dev_name = "foo-mmc.0",
1077 .type = PIN_MAP_TYPE_MUX_GROUP,
1078 .ctrl_dev_name = "pinctrl-foo",
1080 .group = "mmc0_3_grp",
1084 The result of grabbing this mapping from the device with something like
1085 this (see next paragraph):
1087 p = devm_pinctrl_get(dev);
1088 s = pinctrl_lookup_state(p, "8bit");
1089 ret = pinctrl_select_state(p, s);
1093 p = devm_pinctrl_get_select(dev, "8bit");
1095 Will be that you activate all the three bottom records in the mapping at
1096 once. Since they share the same name, pin controller device, function and
1097 device, and since we allow multiple groups to match to a single device, they
1098 all get selected, and they all get enabled and disable simultaneously by the
1102 Pin control requests from drivers
1103 =================================
1105 When a device driver is about to probe the device core will automatically
1106 attempt to issue pinctrl_get_select_default() on these devices.
1107 This way driver writers do not need to add any of the boilerplate code
1108 of the type found below. However when doing fine-grained state selection
1109 and not using the "default" state, you may have to do some device driver
1110 handling of the pinctrl handles and states.
1112 So if you just want to put the pins for a certain device into the default
1113 state and be done with it, there is nothing you need to do besides
1114 providing the proper mapping table. The device core will take care of
1117 Generally it is discouraged to let individual drivers get and enable pin
1118 control. So if possible, handle the pin control in platform code or some other
1119 place where you have access to all the affected struct device * pointers. In
1120 some cases where a driver needs to e.g. switch between different mux mappings
1121 at runtime this is not possible.
1123 A typical case is if a driver needs to switch bias of pins from normal
1124 operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1125 PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1126 current in sleep mode.
1128 A driver may request a certain control state to be activated, usually just the
1129 default state like this:
1131 #include <linux/pinctrl/consumer.h>
1135 struct pinctrl_state *s;
1141 /* Allocate a state holder named "foo" etc */
1142 struct foo_state *foo = ...;
1144 foo->p = devm_pinctrl_get(&device);
1145 if (IS_ERR(foo->p)) {
1146 /* FIXME: clean up "foo" here */
1147 return PTR_ERR(foo->p);
1150 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1151 if (IS_ERR(foo->s)) {
1152 /* FIXME: clean up "foo" here */
1156 ret = pinctrl_select_state(foo->s);
1158 /* FIXME: clean up "foo" here */
1163 This get/lookup/select/put sequence can just as well be handled by bus drivers
1164 if you don't want each and every driver to handle it and you know the
1165 arrangement on your bus.
1167 The semantics of the pinctrl APIs are:
1169 - pinctrl_get() is called in process context to obtain a handle to all pinctrl
1170 information for a given client device. It will allocate a struct from the
1171 kernel memory to hold the pinmux state. All mapping table parsing or similar
1172 slow operations take place within this API.
1174 - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1175 to be called automatically on the retrieved pointer when the associated
1176 device is removed. It is recommended to use this function over plain
1179 - pinctrl_lookup_state() is called in process context to obtain a handle to a
1180 specific state for a the client device. This operation may be slow too.
1182 - pinctrl_select_state() programs pin controller hardware according to the
1183 definition of the state as given by the mapping table. In theory this is a
1184 fast-path operation, since it only involved blasting some register settings
1185 into hardware. However, note that some pin controllers may have their
1186 registers on a slow/IRQ-based bus, so client devices should not assume they
1187 can call pinctrl_select_state() from non-blocking contexts.
1189 - pinctrl_put() frees all information associated with a pinctrl handle.
1191 - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1192 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1193 However, use of this function will be rare, due to the automatic cleanup
1194 that will occur even without calling it.
1196 pinctrl_get() must be paired with a plain pinctrl_put().
1197 pinctrl_get() may not be paired with devm_pinctrl_put().
1198 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1199 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1201 Usually the pin control core handled the get/put pair and call out to the
1202 device drivers bookkeeping operations, like checking available functions and
1203 the associated pins, whereas the enable/disable pass on to the pin controller
1204 driver which takes care of activating and/or deactivating the mux setting by
1205 quickly poking some registers.
1207 The pins are allocated for your device when you issue the devm_pinctrl_get()
1208 call, after this you should be able to see this in the debugfs listing of all
1211 NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1212 requested pinctrl handles, for example if the pinctrl driver has not yet
1213 registered. Thus make sure that the error path in your driver gracefully
1214 cleans up and is ready to retry the probing later in the startup process.
1217 Drivers needing both pin control and GPIOs
1218 ==========================================
1220 Again, it is discouraged to let drivers lookup and select pin control states
1221 themselves, but again sometimes this is unavoidable.
1223 So say that your driver is fetching its resources like this:
1225 #include <linux/pinctrl/consumer.h>
1226 #include <linux/gpio.h>
1228 struct pinctrl *pinctrl;
1231 pinctrl = devm_pinctrl_get_select_default(&dev);
1232 gpio = devm_gpio_request(&dev, 14, "foo");
1234 Here we first request a certain pin state and then request GPIO 14 to be
1235 used. If you're using the subsystems orthogonally like this, you should
1236 nominally always get your pinctrl handle and select the desired pinctrl
1237 state BEFORE requesting the GPIO. This is a semantic convention to avoid
1238 situations that can be electrically unpleasant, you will certainly want to
1239 mux in and bias pins in a certain way before the GPIO subsystems starts to
1242 The above can be hidden: using the device core, the pinctrl core may be
1243 setting up the config and muxing for the pins right before the device is
1244 probing, nevertheless orthogonal to the GPIO subsystem.
1246 But there are also situations where it makes sense for the GPIO subsystem
1247 to communicate directly with the pinctrl subsystem, using the latter as a
1248 back-end. This is when the GPIO driver may call out to the functions
1249 described in the section "Pin control interaction with the GPIO subsystem"
1250 above. This only involves per-pin multiplexing, and will be completely
1251 hidden behind the gpio_*() function namespace. In this case, the driver
1252 need not interact with the pin control subsystem at all.
1254 If a pin control driver and a GPIO driver is dealing with the same pins
1255 and the use cases involve multiplexing, you MUST implement the pin controller
1256 as a back-end for the GPIO driver like this, unless your hardware design
1257 is such that the GPIO controller can override the pin controller's
1258 multiplexing state through hardware without the need to interact with the
1262 System pin control hogging
1263 ==========================
1265 Pin control map entries can be hogged by the core when the pin controller
1266 is registered. This means that the core will attempt to call pinctrl_get(),
1267 lookup_state() and select_state() on it immediately after the pin control
1268 device has been registered.
1270 This occurs for mapping table entries where the client device name is equal
1271 to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1274 .dev_name = "pinctrl-foo",
1275 .name = PINCTRL_STATE_DEFAULT,
1276 .type = PIN_MAP_TYPE_MUX_GROUP,
1277 .ctrl_dev_name = "pinctrl-foo",
1278 .function = "power_func",
1281 Since it may be common to request the core to hog a few always-applicable
1282 mux settings on the primary pin controller, there is a convenience macro for
1285 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1287 This gives the exact same result as the above construction.
1293 It is possible to mux a certain function in and out at runtime, say to move
1294 an SPI port from one set of pins to another set of pins. Say for example for
1295 spi0 in the example above, we expose two different groups of pins for the same
1296 function, but with different named in the mapping as described under
1297 "Advanced mapping" above. So that for an SPI device, we have two states named
1298 "pos-A" and "pos-B".
1300 This snippet first muxes the function in the pins defined by group A, enables
1301 it, disables and releases it, and muxes it in on the pins defined by group B:
1303 #include <linux/pinctrl/consumer.h>
1306 struct pinctrl_state *s1, *s2;
1311 p = devm_pinctrl_get(&device);
1315 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1319 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1326 /* Enable on position A */
1327 ret = pinctrl_select_state(s1);
1333 /* Enable on position B */
1334 ret = pinctrl_select_state(s2);
1341 The above has to be done from process context. The reservation of the pins
1342 will be done when the state is activated, so in effect one specific pin
1343 can be used by different functions at different times on a running system.