2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
13 /include/ "skeleton_hs_idu.dtsi"
16 compatible = "snps,arc";
21 compatible = "simple-bus";
25 ranges = <0x00000000 0xf0000000 0x10000000>;
29 compatible = "fixed-clock";
30 clock-frequency = <100000000>;
33 core_intc: archs-intc@cpu {
34 compatible = "snps,archs-intc";
36 #interrupt-cells = <1>;
39 idu_intc: idu-interrupt-controller {
40 compatible = "snps,archs-idu-intc";
42 interrupt-parent = <&core_intc>;
45 * <hwirq distribution>
46 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
48 #interrupt-cells = <2>;
51 * upstream irqs to core intc - downstream these are
58 * this GPIO block ORs all interrupts on CPU card (creg,..)
59 * to uplink only 1 IRQ to ARC core intc
62 compatible = "snps,dw-apb-gpio";
63 reg = < 0x2000 0x80 >;
67 ictl_intc: gpio-controller@0 {
68 compatible = "snps,dw-apb-gpio-port";
74 #interrupt-cells = <2>;
75 interrupt-parent = <&idu_intc>;
78 * cmn irq 1 -> cpu irq 25
79 * Distribute to cpu0 only
85 debug_uart: dw-apb-uart@0x5000 {
86 compatible = "snps,dw-apb-uart";
88 clock-frequency = <33333000>;
89 interrupt-parent = <&ictl_intc>;
97 compatible = "snps,archs-pct";
98 #interrupt-cells = <1>;
99 interrupt-parent = <&core_intc>;
105 * This INTC is actually connected to DW APB GPIO
106 * which acts as a wire between MB INTC and CPU INTC.
107 * GPIO INTC is configured in platform init code
108 * and here we mimic direct connection from MB INTC to
109 * CPU INTC, thus we set "interrupts = <0 1>" instead of
110 * "interrupts = <12>"
112 * This intc actually resides on MB, but we move it here to
113 * avoid duplicating the MB dtsi file given that IRQ from
114 * this intc to cpu intc are different for axs101 and axs103
116 mb_intc: dw-apb-ictl@0xe0012000 {
117 #interrupt-cells = <1>;
118 compatible = "snps,dw-apb-ictl";
119 reg = < 0xe0012000 0x200 >;
120 interrupt-controller;
121 interrupt-parent = <&idu_intc>;
122 interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
123 distribute to cpu0 only */
127 #address-cells = <1>;
129 ranges = <0x00000000 0x80000000 0x40000000>;
130 device_type = "memory";
131 reg = <0x80000000 0x20000000>; /* 512MiB */
135 #address-cells = <1>;
139 * Move frame buffer out of IOC aperture (0x8z-0xAz).
141 frame_buffer: frame_buffer@be000000 {
142 compatible = "shared-dma-pool";
143 reg = <0xbe000000 0x2000000>;