4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CLONE_BACKWARDS
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IDLE_POLL_SETUP
17 select GENERIC_IRQ_PROBE
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_SMP_IDLE_THREAD
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
30 select HAVE_CONTEXT_TRACKING
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DMA_API_DEBUG
35 select HAVE_DMA_CONTIGUOUS if MMU
36 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
37 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
38 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
39 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
40 select HAVE_GENERIC_DMA_COHERENT
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZ4
46 select HAVE_KERNEL_LZMA
47 select HAVE_KERNEL_LZO
49 select HAVE_KPROBES if !XIP_KERNEL
50 select HAVE_KRETPROBES if (HAVE_KPROBES)
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
54 select HAVE_PERF_EVENTS
56 select HAVE_PERF_USER_STACK_DUMP
57 select HAVE_REGS_AND_STACK_ACCESS_API
58 select HAVE_SYSCALL_TRACEPOINTS
60 select IRQ_FORCED_THREADING
62 select MODULES_USE_ELF_REL
64 select OLD_SIGSUSPEND3
65 select PERF_USE_VMALLOC
67 select SYS_SUPPORTS_APM_EMULATION
68 # Above selects are sorted alphabetically; please add new ones
69 # according to that. Thanks.
71 The ARM series is a line of low-power-consumption RISC chip designs
72 licensed by ARM Ltd and targeted at embedded applications and
73 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
74 manufactured, but legacy ARM-based PC hardware remains popular in
75 Europe. There is an ARM Linux project with a web page at
76 <http://www.arm.linux.org.uk/>.
78 config ARM_HAS_SG_CHAIN
81 config NEED_SG_DMA_LENGTH
84 config ARM_DMA_USE_IOMMU
86 select ARM_HAS_SG_CHAIN
87 select NEED_SG_DMA_LENGTH
91 config ARM_DMA_IOMMU_ALIGNMENT
92 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
96 DMA mapping framework by default aligns all buffers to the smallest
97 PAGE_SIZE order which is greater than or equal to the requested buffer
98 size. This works well for buffers up to a few hundreds kilobytes, but
99 for larger buffers it just a waste of address space. Drivers which has
100 relatively small addressing window (like 64Mib) might run out of
101 virtual space with just a few allocations.
103 With this parameter you can specify the maximum PAGE_SIZE order for
104 DMA IOMMU buffers. Larger buffers will be aligned only to this
105 specified order. The order is expressed as a power of two multiplied
113 config MIGHT_HAVE_PCI
116 config SYS_SUPPORTS_APM_EMULATION
121 select GENERIC_ALLOCATOR
132 The Extended Industry Standard Architecture (EISA) bus was
133 developed as an open alternative to the IBM MicroChannel bus.
135 The EISA bus provided some of the features of the IBM MicroChannel
136 bus while maintaining backward compatibility with cards made for
137 the older ISA bus. The EISA bus saw limited use between 1988 and
138 1995 when it was made obsolete by the PCI bus.
140 Say Y here if you are building a kernel for an EISA-based machine.
147 config STACKTRACE_SUPPORT
151 config HAVE_LATENCYTOP_SUPPORT
156 config LOCKDEP_SUPPORT
160 config TRACE_IRQFLAGS_SUPPORT
164 config RWSEM_GENERIC_SPINLOCK
168 config RWSEM_XCHGADD_ALGORITHM
171 config ARCH_HAS_ILOG2_U32
174 config ARCH_HAS_ILOG2_U64
177 config ARCH_HAS_CPUFREQ
180 Internal node to signify that the ARCH has CPUFREQ support
181 and that the relevant menu configurations are displayed for
184 config ARCH_HAS_BANDGAP
187 config GENERIC_HWEIGHT
191 config GENERIC_CALIBRATE_DELAY
195 config ARCH_MAY_HAVE_PC_FDC
201 config NEED_DMA_MAP_STATE
204 config ARCH_HAS_DMA_SET_COHERENT_MASK
207 config GENERIC_ISA_DMA
213 config NEED_RET_TO_USER
221 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
222 default DRAM_BASE if REMAP_VECTORS_TO_RAM
225 The base address of exception vectors. This must be two pages
228 config ARM_PATCH_PHYS_VIRT
229 bool "Patch physical to virtual translations at runtime" if EMBEDDED
231 depends on !XIP_KERNEL && MMU
232 depends on !ARCH_REALVIEW || !SPARSEMEM
234 Patch phys-to-virt and virt-to-phys translation functions at
235 boot and module load time according to the position of the
236 kernel in system memory.
238 This can only be used with non-XIP MMU kernels where the base
239 of physical memory is at a 16MB boundary.
241 Only disable this option if you know that you do not require
242 this feature (eg, building a kernel for a single machine) and
243 you need to shrink the kernel to the minimal size.
245 config NEED_MACH_GPIO_H
248 Select this when mach/gpio.h is required to provide special
249 definitions for this platform. The need for mach/gpio.h should
250 be avoided when possible.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
269 default DRAM_BASE if !MMU
271 Please provide the physical address corresponding to the
272 location of main memory in your system.
278 source "init/Kconfig"
280 source "kernel/Kconfig.freezer"
285 bool "MMU-based Paged Memory Management Support"
288 Select if you want MMU-based virtualised addressing space
289 support by paged memory management. If unsure, say 'Y'.
292 # The "ARM system type" choice list is ordered alphabetically by option
293 # text. Please add new entries in the option alphabetic order.
296 prompt "ARM system type"
297 default ARCH_VERSATILE if !MMU
298 default ARCH_MULTIPLATFORM if MMU
300 config ARCH_MULTIPLATFORM
301 bool "Allow multiple platforms to be selected"
303 select ARM_PATCH_PHYS_VIRT
306 select MULTI_IRQ_HANDLER
310 config ARCH_INTEGRATOR
311 bool "ARM Ltd. Integrator family"
312 select ARCH_HAS_CPUFREQ
315 select COMMON_CLK_VERSATILE
316 select GENERIC_CLOCKEVENTS
319 select MULTI_IRQ_HANDLER
320 select NEED_MACH_MEMORY_H
321 select PLAT_VERSATILE
323 select VERSATILE_FPGA_IRQ
325 Support for ARM's Integrator platform.
328 bool "ARM Ltd. RealView family"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 select ARM_TIMER_SP804
333 select COMMON_CLK_VERSATILE
334 select GENERIC_CLOCKEVENTS
335 select GPIO_PL061 if GPIOLIB
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLCD
341 This enables support for ARM Ltd RealView boards.
343 config ARCH_VERSATILE
344 bool "ARM Ltd. Versatile family"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select HAVE_MACH_CLKDEV
353 select PLAT_VERSATILE
354 select PLAT_VERSATILE_CLCD
355 select PLAT_VERSATILE_CLOCK
356 select VERSATILE_FPGA_IRQ
358 This enables support for ARM Ltd Versatile board.
362 select ARCH_REQUIRE_GPIOLIB
366 select NEED_MACH_GPIO_H
367 select NEED_MACH_IO_H if PCCARD
369 select PINCTRL_AT91 if USE_OF
371 This enables support for systems based on Atmel
372 AT91RM9200 and AT91SAM9* processors.
375 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
376 select ARCH_REQUIRE_GPIOLIB
382 select GENERIC_CLOCKEVENTS
384 select MULTI_IRQ_HANDLER
387 Support for Cirrus Logic 711x/721x/731x based boards.
390 bool "Cortina Systems Gemini"
391 select ARCH_REQUIRE_GPIOLIB
392 select ARCH_USES_GETTIMEOFFSET
394 select NEED_MACH_GPIO_H
396 Support for the Cortina Systems Gemini family SoCs
400 select ARCH_USES_GETTIMEOFFSET
403 select NEED_MACH_IO_H
404 select NEED_MACH_MEMORY_H
407 This is an evaluation board for the StrongARM processor available
408 from Digital. It has limited hardware on-board, including an
409 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_HAS_HOLES_MEMORYMODEL
415 select ARCH_REQUIRE_GPIOLIB
416 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_MEMORY_H
423 This enables support for the Cirrus EP93xx series of CPUs.
425 config ARCH_FOOTBRIDGE
429 select GENERIC_CLOCKEVENTS
431 select NEED_MACH_IO_H if !MMU
432 select NEED_MACH_MEMORY_H
434 Support for systems based on the DC21285 companion chip
435 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
438 bool "Hilscher NetX based"
442 select GENERIC_CLOCKEVENTS
444 This enables support for systems based on the Hilscher NetX Soc
450 select NEED_MACH_MEMORY_H
451 select NEED_RET_TO_USER
456 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
463 select NEED_MACH_GPIO_H
464 select NEED_RET_TO_USER
468 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
476 select NEED_MACH_GPIO_H
477 select NEED_RET_TO_USER
481 Support for Intel's IOP33X (XScale) family of processors.
486 select ARCH_HAS_DMA_SET_COHERENT_MASK
487 select ARCH_SUPPORTS_BIG_ENDIAN
488 select ARCH_REQUIRE_GPIOLIB
491 select DMABOUNCE if PCI
492 select GENERIC_CLOCKEVENTS
493 select MIGHT_HAVE_PCI
494 select NEED_MACH_IO_H
495 select USB_EHCI_BIG_ENDIAN_DESC
496 select USB_EHCI_BIG_ENDIAN_MMIO
498 Support for Intel's IXP4XX (XScale) family of processors.
502 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select MIGHT_HAVE_PCI
509 select PLAT_ORION_LEGACY
510 select USB_ARCH_HAS_EHCI
512 Support for the Marvell Dove SoC 88AP510
515 bool "Marvell Kirkwood"
516 select ARCH_HAS_CPUFREQ
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
524 select PINCTRL_KIRKWOOD
525 select PLAT_ORION_LEGACY
527 Support for the following Marvell Kirkwood series SoCs:
528 88F6180, 88F6192 and 88F6281.
531 bool "Marvell MV78xx0"
532 select ARCH_REQUIRE_GPIOLIB
534 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION_LEGACY
539 Support for the following Marvell MV78xx0 series SoCs:
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Orion 5x series SoCs:
553 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
554 Orion-2 (5281), Orion-1-90 (6183).
557 bool "Marvell PXA168/910/MMP2"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_ALLOCATOR
562 select GENERIC_CLOCKEVENTS
565 select MULTI_IRQ_HANDLER
566 select NEED_MACH_GPIO_H
571 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
574 bool "Micrel/Kendin KS8695"
575 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_MEMORY_H
581 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
582 System-on-Chip devices.
585 bool "Nuvoton W90X900 CPU"
586 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
592 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
593 At present, the w90x900 has been renamed nuc900, regarding
594 the ARM series product line, you can login the following
595 link address to know more.
597 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
598 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
602 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
610 select USB_ARCH_HAS_OHCI
613 Support for the NXP LPC32XX family of processors
616 bool "PXA2xx/PXA3xx-based"
618 select ARCH_HAS_CPUFREQ
620 select ARCH_REQUIRE_GPIOLIB
621 select ARM_CPU_SUSPEND if PM
625 select GENERIC_CLOCKEVENTS
628 select MULTI_IRQ_HANDLER
629 select NEED_MACH_GPIO_H
633 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
637 select ARCH_REQUIRE_GPIOLIB
639 select CLKSRC_OF if OF
641 select GENERIC_CLOCKEVENTS
643 Support for Qualcomm MSM/QSD based systems. This runs on the
644 apps processor of the MSM/QSD and depends on a shared memory
645 interface to the modem processor which runs the baseband
646 stack and controls some vital subsystems
647 (clock and power control, etc).
650 bool "Renesas SH-Mobile / R-Mobile"
651 select ARM_PATCH_PHYS_VIRT
653 select GENERIC_CLOCKEVENTS
654 select HAVE_ARM_SCU if SMP
655 select HAVE_ARM_TWD if SMP
657 select HAVE_MACH_CLKDEV
659 select MIGHT_HAVE_CACHE_L2X0
660 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
666 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
671 select ARCH_MAY_HAVE_PC_FDC
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
676 select HAVE_PATA_PLATFORM
678 select NEED_MACH_IO_H
679 select NEED_MACH_MEMORY_H
683 On the Acorn Risc-PC, Linux can support the internal IDE disk and
684 CD-ROM interface, serial and parallel port, and the floppy drive.
688 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select ARCH_SPARSEMEM_ENABLE
696 select GENERIC_CLOCKEVENTS
699 select NEED_MACH_GPIO_H
700 select NEED_MACH_MEMORY_H
703 Support for StrongARM 11x0 based boards.
706 bool "Samsung S3C24XX SoCs"
707 select ARCH_HAS_CPUFREQ
708 select ARCH_REQUIRE_GPIOLIB
710 select CLKSRC_SAMSUNG_PWM
711 select GENERIC_CLOCKEVENTS
714 select HAVE_S3C2410_I2C if I2C
715 select HAVE_S3C2410_WATCHDOG if WATCHDOG
716 select HAVE_S3C_RTC if RTC_CLASS
717 select MULTI_IRQ_HANDLER
718 select NEED_MACH_GPIO_H
719 select NEED_MACH_IO_H
722 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
723 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
724 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
725 Samsung SMDK2410 development board (and derivatives).
728 bool "Samsung S3C64XX"
729 select ARCH_HAS_CPUFREQ
730 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 select NEED_MACH_GPIO_H
745 select S3C_GPIO_TRACK
747 select SAMSUNG_CLKSRC
748 select SAMSUNG_GPIOLIB_4BIT
749 select SAMSUNG_WDT_RESET
750 select USB_ARCH_HAS_OHCI
752 Samsung S3C64XX series based systems
755 bool "Samsung S5P6440 S5P6450"
757 select CLKSRC_SAMSUNG_PWM
759 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
764 select HAVE_S3C_RTC if RTC_CLASS
765 select NEED_MACH_GPIO_H
767 select SAMSUNG_WDT_RESET
769 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
773 bool "Samsung S5PC100"
774 select ARCH_REQUIRE_GPIOLIB
776 select CLKSRC_SAMSUNG_PWM
778 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C2410_WATCHDOG if WATCHDOG
783 select HAVE_S3C_RTC if RTC_CLASS
784 select NEED_MACH_GPIO_H
786 select SAMSUNG_WDT_RESET
788 Samsung S5PC100 series based systems
791 bool "Samsung S5PV210/S5PC110"
792 select ARCH_HAS_CPUFREQ
793 select ARCH_HAS_HOLES_MEMORYMODEL
794 select ARCH_SPARSEMEM_ENABLE
796 select CLKSRC_SAMSUNG_PWM
798 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
805 select NEED_MACH_MEMORY_H
808 Samsung S5PV210/S5PC110 series based systems
811 bool "Samsung EXYNOS"
812 select ARCH_HAS_CPUFREQ
813 select ARCH_HAS_HOLES_MEMORYMODEL
814 select ARCH_REQUIRE_GPIOLIB
815 select ARCH_SPARSEMEM_ENABLE
820 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_MEMORY_H
829 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
833 select ARCH_USES_GETTIMEOFFSET
837 select NEED_MACH_MEMORY_H
842 Support for the StrongARM based Digital DNARD machine, also known
843 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 select ARCH_HAS_HOLES_MEMORYMODEL
848 select ARCH_REQUIRE_GPIOLIB
850 select GENERIC_ALLOCATOR
851 select GENERIC_CLOCKEVENTS
852 select GENERIC_IRQ_CHIP
854 select NEED_MACH_GPIO_H
859 Support for TI's DaVinci platform.
864 select ARCH_HAS_CPUFREQ
865 select ARCH_HAS_HOLES_MEMORYMODEL
867 select ARCH_REQUIRE_GPIOLIB
870 select GENERIC_CLOCKEVENTS
871 select GENERIC_IRQ_CHIP
875 select NEED_MACH_IO_H if PCCARD
876 select NEED_MACH_MEMORY_H
878 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
882 menu "Multiple platform selection"
883 depends on ARCH_MULTIPLATFORM
885 comment "CPU Core family selection"
887 config ARCH_MULTI_V4T
888 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
891 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
892 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
893 CPU_ARM925T || CPU_ARM940T)
896 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
897 depends on !ARCH_MULTI_V6_V7
898 select ARCH_MULTI_V4_V5
899 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
900 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
901 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
903 config ARCH_MULTI_V4_V5
907 bool "ARMv6 based platforms (ARM11)"
908 select ARCH_MULTI_V6_V7
912 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
914 select ARCH_MULTI_V6_V7
917 config ARCH_MULTI_V6_V7
920 config ARCH_MULTI_CPU_AUTO
921 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
927 # This is sorted alphabetically by mach-* pathname. However, plat-*
928 # Kconfigs may be included either alphabetically (according to the
929 # plat- suffix) or along side the corresponding mach-* source.
931 source "arch/arm/mach-mvebu/Kconfig"
933 source "arch/arm/mach-at91/Kconfig"
935 source "arch/arm/mach-bcm/Kconfig"
937 source "arch/arm/mach-bcm2835/Kconfig"
939 source "arch/arm/mach-clps711x/Kconfig"
941 source "arch/arm/mach-cns3xxx/Kconfig"
943 source "arch/arm/mach-davinci/Kconfig"
945 source "arch/arm/mach-dove/Kconfig"
947 source "arch/arm/mach-ep93xx/Kconfig"
949 source "arch/arm/mach-footbridge/Kconfig"
951 source "arch/arm/mach-gemini/Kconfig"
953 source "arch/arm/mach-highbank/Kconfig"
955 source "arch/arm/mach-integrator/Kconfig"
957 source "arch/arm/mach-iop32x/Kconfig"
959 source "arch/arm/mach-iop33x/Kconfig"
961 source "arch/arm/mach-iop13xx/Kconfig"
963 source "arch/arm/mach-ixp4xx/Kconfig"
965 source "arch/arm/mach-keystone/Kconfig"
967 source "arch/arm/mach-kirkwood/Kconfig"
969 source "arch/arm/mach-ks8695/Kconfig"
971 source "arch/arm/mach-msm/Kconfig"
973 source "arch/arm/mach-mv78xx0/Kconfig"
975 source "arch/arm/mach-imx/Kconfig"
977 source "arch/arm/mach-mxs/Kconfig"
979 source "arch/arm/mach-netx/Kconfig"
981 source "arch/arm/mach-nomadik/Kconfig"
983 source "arch/arm/mach-nspire/Kconfig"
985 source "arch/arm/plat-omap/Kconfig"
987 source "arch/arm/mach-omap1/Kconfig"
989 source "arch/arm/mach-omap2/Kconfig"
991 source "arch/arm/mach-orion5x/Kconfig"
993 source "arch/arm/mach-picoxcell/Kconfig"
995 source "arch/arm/mach-pxa/Kconfig"
996 source "arch/arm/plat-pxa/Kconfig"
998 source "arch/arm/mach-mmp/Kconfig"
1000 source "arch/arm/mach-realview/Kconfig"
1002 source "arch/arm/mach-rockchip/Kconfig"
1004 source "arch/arm/mach-sa1100/Kconfig"
1006 source "arch/arm/plat-samsung/Kconfig"
1008 source "arch/arm/mach-socfpga/Kconfig"
1010 source "arch/arm/mach-spear/Kconfig"
1012 source "arch/arm/mach-sti/Kconfig"
1014 source "arch/arm/mach-s3c24xx/Kconfig"
1017 source "arch/arm/mach-s3c64xx/Kconfig"
1020 source "arch/arm/mach-s5p64x0/Kconfig"
1022 source "arch/arm/mach-s5pc100/Kconfig"
1024 source "arch/arm/mach-s5pv210/Kconfig"
1026 source "arch/arm/mach-exynos/Kconfig"
1028 source "arch/arm/mach-shmobile/Kconfig"
1030 source "arch/arm/mach-sunxi/Kconfig"
1032 source "arch/arm/mach-prima2/Kconfig"
1034 source "arch/arm/mach-tegra/Kconfig"
1036 source "arch/arm/mach-u300/Kconfig"
1038 source "arch/arm/mach-ux500/Kconfig"
1040 source "arch/arm/mach-versatile/Kconfig"
1042 source "arch/arm/mach-vexpress/Kconfig"
1043 source "arch/arm/plat-versatile/Kconfig"
1045 source "arch/arm/mach-virt/Kconfig"
1047 source "arch/arm/mach-vt8500/Kconfig"
1049 source "arch/arm/mach-w90x900/Kconfig"
1051 source "arch/arm/mach-zynq/Kconfig"
1053 # Definitions to make life easier
1059 select GENERIC_CLOCKEVENTS
1065 select GENERIC_IRQ_CHIP
1068 config PLAT_ORION_LEGACY
1075 config PLAT_VERSATILE
1078 config ARM_TIMER_SP804
1081 select CLKSRC_OF if OF
1083 source arch/arm/mm/Kconfig
1087 default 16 if ARCH_EP93XX
1091 bool "Enable iWMMXt support" if !CPU_PJ4
1092 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1093 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1095 Enable support for iWMMXt context switching at run time if
1096 running on a CPU that supports it.
1098 config MULTI_IRQ_HANDLER
1101 Allow each machine to specify it's own IRQ handler at run time.
1104 source "arch/arm/Kconfig-nommu"
1107 config PJ4B_ERRATA_4742
1108 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1109 depends on CPU_PJ4B && MACH_ARMADA_370
1112 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1113 Event (WFE) IDLE states, a specific timing sensitivity exists between
1114 the retiring WFI/WFE instructions and the newly issued subsequent
1115 instructions. This sensitivity can result in a CPU hang scenario.
1117 The software must insert either a Data Synchronization Barrier (DSB)
1118 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1121 config ARM_ERRATA_326103
1122 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1125 Executing a SWP instruction to read-only memory does not set bit 11
1126 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1127 treat the access as a read, preventing a COW from occurring and
1128 causing the faulting task to livelock.
1130 config ARM_ERRATA_411920
1131 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1132 depends on CPU_V6 || CPU_V6K
1134 Invalidation of the Instruction Cache operation can
1135 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1136 It does not affect the MPCore. This option enables the ARM Ltd.
1137 recommended workaround.
1139 config ARM_ERRATA_430973
1140 bool "ARM errata: Stale prediction on replaced interworking branch"
1143 This option enables the workaround for the 430973 Cortex-A8
1144 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1145 interworking branch is replaced with another code sequence at the
1146 same virtual address, whether due to self-modifying code or virtual
1147 to physical address re-mapping, Cortex-A8 does not recover from the
1148 stale interworking branch prediction. This results in Cortex-A8
1149 executing the new code sequence in the incorrect ARM or Thumb state.
1150 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1151 and also flushes the branch target cache at every context switch.
1152 Note that setting specific bits in the ACTLR register may not be
1153 available in non-secure mode.
1155 config ARM_ERRATA_458693
1156 bool "ARM errata: Processor deadlock when a false hazard is created"
1158 depends on !ARCH_MULTIPLATFORM
1160 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1161 erratum. For very specific sequences of memory operations, it is
1162 possible for a hazard condition intended for a cache line to instead
1163 be incorrectly associated with a different cache line. This false
1164 hazard might then cause a processor deadlock. The workaround enables
1165 the L1 caching of the NEON accesses and disables the PLD instruction
1166 in the ACTLR register. Note that setting specific bits in the ACTLR
1167 register may not be available in non-secure mode.
1169 config ARM_ERRATA_460075
1170 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1172 depends on !ARCH_MULTIPLATFORM
1174 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1175 erratum. Any asynchronous access to the L2 cache may encounter a
1176 situation in which recent store transactions to the L2 cache are lost
1177 and overwritten with stale memory contents from external memory. The
1178 workaround disables the write-allocate mode for the L2 cache via the
1179 ACTLR register. Note that setting specific bits in the ACTLR register
1180 may not be available in non-secure mode.
1182 config ARM_ERRATA_742230
1183 bool "ARM errata: DMB operation may be faulty"
1184 depends on CPU_V7 && SMP
1185 depends on !ARCH_MULTIPLATFORM
1187 This option enables the workaround for the 742230 Cortex-A9
1188 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1189 between two write operations may not ensure the correct visibility
1190 ordering of the two writes. This workaround sets a specific bit in
1191 the diagnostic register of the Cortex-A9 which causes the DMB
1192 instruction to behave as a DSB, ensuring the correct behaviour of
1195 config ARM_ERRATA_742231
1196 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1197 depends on CPU_V7 && SMP
1198 depends on !ARCH_MULTIPLATFORM
1200 This option enables the workaround for the 742231 Cortex-A9
1201 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1202 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1203 accessing some data located in the same cache line, may get corrupted
1204 data due to bad handling of the address hazard when the line gets
1205 replaced from one of the CPUs at the same time as another CPU is
1206 accessing it. This workaround sets specific bits in the diagnostic
1207 register of the Cortex-A9 which reduces the linefill issuing
1208 capabilities of the processor.
1210 config PL310_ERRATA_588369
1211 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1212 depends on CACHE_L2X0
1214 The PL310 L2 cache controller implements three types of Clean &
1215 Invalidate maintenance operations: by Physical Address
1216 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1217 They are architecturally defined to behave as the execution of a
1218 clean operation followed immediately by an invalidate operation,
1219 both performing to the same memory location. This functionality
1220 is not correctly implemented in PL310 as clean lines are not
1221 invalidated as a result of these operations.
1223 config ARM_ERRATA_643719
1224 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1225 depends on CPU_V7 && SMP
1227 This option enables the workaround for the 643719 Cortex-A9 (prior to
1228 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1229 register returns zero when it should return one. The workaround
1230 corrects this value, ensuring cache maintenance operations which use
1231 it behave as intended and avoiding data corruption.
1233 config ARM_ERRATA_720789
1234 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1237 This option enables the workaround for the 720789 Cortex-A9 (prior to
1238 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1239 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1240 As a consequence of this erratum, some TLB entries which should be
1241 invalidated are not, resulting in an incoherency in the system page
1242 tables. The workaround changes the TLB flushing routines to invalidate
1243 entries regardless of the ASID.
1245 config PL310_ERRATA_727915
1246 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1247 depends on CACHE_L2X0
1249 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1250 operation (offset 0x7FC). This operation runs in background so that
1251 PL310 can handle normal accesses while it is in progress. Under very
1252 rare circumstances, due to this erratum, write data can be lost when
1253 PL310 treats a cacheable write transaction during a Clean &
1254 Invalidate by Way operation.
1256 config ARM_ERRATA_743622
1257 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1259 depends on !ARCH_MULTIPLATFORM
1261 This option enables the workaround for the 743622 Cortex-A9
1262 (r2p*) erratum. Under very rare conditions, a faulty
1263 optimisation in the Cortex-A9 Store Buffer may lead to data
1264 corruption. This workaround sets a specific bit in the diagnostic
1265 register of the Cortex-A9 which disables the Store Buffer
1266 optimisation, preventing the defect from occurring. This has no
1267 visible impact on the overall performance or power consumption of the
1270 config ARM_ERRATA_751472
1271 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1273 depends on !ARCH_MULTIPLATFORM
1275 This option enables the workaround for the 751472 Cortex-A9 (prior
1276 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1277 completion of a following broadcasted operation if the second
1278 operation is received by a CPU before the ICIALLUIS has completed,
1279 potentially leading to corrupted entries in the cache or TLB.
1281 config PL310_ERRATA_753970
1282 bool "PL310 errata: cache sync operation may be faulty"
1283 depends on CACHE_PL310
1285 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1287 Under some condition the effect of cache sync operation on
1288 the store buffer still remains when the operation completes.
1289 This means that the store buffer is always asked to drain and
1290 this prevents it from merging any further writes. The workaround
1291 is to replace the normal offset of cache sync operation (0x730)
1292 by another offset targeting an unmapped PL310 register 0x740.
1293 This has the same effect as the cache sync operation: store buffer
1294 drain and waiting for all buffers empty.
1296 config ARM_ERRATA_754322
1297 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1300 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1301 r3p*) erratum. A speculative memory access may cause a page table walk
1302 which starts prior to an ASID switch but completes afterwards. This
1303 can populate the micro-TLB with a stale entry which may be hit with
1304 the new ASID. This workaround places two dsb instructions in the mm
1305 switching code so that no page table walks can cross the ASID switch.
1307 config ARM_ERRATA_754327
1308 bool "ARM errata: no automatic Store Buffer drain"
1309 depends on CPU_V7 && SMP
1311 This option enables the workaround for the 754327 Cortex-A9 (prior to
1312 r2p0) erratum. The Store Buffer does not have any automatic draining
1313 mechanism and therefore a livelock may occur if an external agent
1314 continuously polls a memory location waiting to observe an update.
1315 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1316 written polling loops from denying visibility of updates to memory.
1318 config ARM_ERRATA_364296
1319 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1322 This options enables the workaround for the 364296 ARM1136
1323 r0p2 erratum (possible cache data corruption with
1324 hit-under-miss enabled). It sets the undocumented bit 31 in
1325 the auxiliary control register and the FI bit in the control
1326 register, thus disabling hit-under-miss without putting the
1327 processor into full low interrupt latency mode. ARM11MPCore
1330 config ARM_ERRATA_764369
1331 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1332 depends on CPU_V7 && SMP
1334 This option enables the workaround for erratum 764369
1335 affecting Cortex-A9 MPCore with two or more processors (all
1336 current revisions). Under certain timing circumstances, a data
1337 cache line maintenance operation by MVA targeting an Inner
1338 Shareable memory region may fail to proceed up to either the
1339 Point of Coherency or to the Point of Unification of the
1340 system. This workaround adds a DSB instruction before the
1341 relevant cache maintenance functions and sets a specific bit
1342 in the diagnostic control register of the SCU.
1344 config PL310_ERRATA_769419
1345 bool "PL310 errata: no automatic Store Buffer drain"
1346 depends on CACHE_L2X0
1348 On revisions of the PL310 prior to r3p2, the Store Buffer does
1349 not automatically drain. This can cause normal, non-cacheable
1350 writes to be retained when the memory system is idle, leading
1351 to suboptimal I/O performance for drivers using coherent DMA.
1352 This option adds a write barrier to the cpu_idle loop so that,
1353 on systems with an outer cache, the store buffer is drained
1356 config ARM_ERRATA_775420
1357 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1360 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1361 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1362 operation aborts with MMU exception, it might cause the processor
1363 to deadlock. This workaround puts DSB before executing ISB if
1364 an abort may occur on cache maintenance.
1366 config ARM_ERRATA_798181
1367 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1368 depends on CPU_V7 && SMP
1370 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1371 adequately shooting down all use of the old entries. This
1372 option enables the Linux kernel workaround for this erratum
1373 which sends an IPI to the CPUs that are running the same ASID
1374 as the one being invalidated.
1376 config ARM_ERRATA_773022
1377 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1380 This option enables the workaround for the 773022 Cortex-A15
1381 (up to r0p4) erratum. In certain rare sequences of code, the
1382 loop buffer may deliver incorrect instructions. This
1383 workaround disables the loop buffer to avoid the erratum.
1387 source "arch/arm/common/Kconfig"
1397 Find out whether you have ISA slots on your motherboard. ISA is the
1398 name of a bus system, i.e. the way the CPU talks to the other stuff
1399 inside your box. Other bus systems are PCI, EISA, MicroChannel
1400 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1401 newer boards don't support it. If you have ISA, say Y, otherwise N.
1403 # Select ISA DMA controller support
1408 # Select ISA DMA interface
1413 bool "PCI support" if MIGHT_HAVE_PCI
1415 Find out whether you have a PCI motherboard. PCI is the name of a
1416 bus system, i.e. the way the CPU talks to the other stuff inside
1417 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1418 VESA. If you have PCI, say Y, otherwise N.
1424 config PCI_NANOENGINE
1425 bool "BSE nanoEngine PCI support"
1426 depends on SA1100_NANOENGINE
1428 Enable PCI on the BSE nanoEngine board.
1433 # Select the host bridge type
1434 config PCI_HOST_VIA82C505
1436 depends on PCI && ARCH_SHARK
1439 config PCI_HOST_ITE8152
1441 depends on PCI && MACH_ARMCORE
1445 source "drivers/pci/Kconfig"
1446 source "drivers/pci/pcie/Kconfig"
1448 source "drivers/pcmcia/Kconfig"
1452 menu "Kernel Features"
1457 This option should be selected by machines which have an SMP-
1460 The only effect of this option is to make the SMP-related
1461 options available to the user for configuration.
1464 bool "Symmetric Multi-Processing"
1465 depends on CPU_V6K || CPU_V7
1466 depends on GENERIC_CLOCKEVENTS
1468 depends on MMU || ARM_MPU
1469 select USE_GENERIC_SMP_HELPERS
1471 This enables support for systems with more than one CPU. If you have
1472 a system with only one CPU, like most personal computers, say N. If
1473 you have a system with more than one CPU, say Y.
1475 If you say N here, the kernel will run on single and multiprocessor
1476 machines, but will use only one CPU of a multiprocessor machine. If
1477 you say Y here, the kernel will run on many, but not all, single
1478 processor machines. On a single processor machine, the kernel will
1479 run faster if you say N here.
1481 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1482 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1483 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1485 If you don't know what to do here, say N.
1488 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1489 depends on SMP && !XIP_KERNEL && MMU
1492 SMP kernels contain instructions which fail on non-SMP processors.
1493 Enabling this option allows the kernel to modify itself to make
1494 these instructions safe. Disabling it allows about 1K of space
1497 If you don't know what to do here, say Y.
1499 config ARM_CPU_TOPOLOGY
1500 bool "Support cpu topology definition"
1501 depends on SMP && CPU_V7
1504 Support ARM cpu topology definition. The MPIDR register defines
1505 affinity between processors which is then used to describe the cpu
1506 topology of an ARM System.
1509 bool "Multi-core scheduler support"
1510 depends on ARM_CPU_TOPOLOGY
1512 Multi-core scheduler support improves the CPU scheduler's decision
1513 making when dealing with multi-core CPU chips at a cost of slightly
1514 increased overhead in some places. If unsure say N here.
1517 bool "SMT scheduler support"
1518 depends on ARM_CPU_TOPOLOGY
1520 Improves the CPU scheduler's decision making when dealing with
1521 MultiThreading at a cost of slightly increased overhead in some
1522 places. If unsure say N here.
1527 This option enables support for the ARM system coherency unit
1529 config HAVE_ARM_ARCH_TIMER
1530 bool "Architected timer support"
1532 select ARM_ARCH_TIMER
1534 This option enables support for the ARM architected timer
1539 select CLKSRC_OF if OF
1541 This options enables support for the ARM timer and watchdog unit
1544 bool "Multi-Cluster Power Management"
1545 depends on CPU_V7 && SMP
1547 This option provides the common power management infrastructure
1548 for (multi-)cluster based systems, such as big.LITTLE based
1552 bool "big.LITTLE support (Experimental)"
1553 depends on CPU_V7 && SMP
1556 This option enables support selections for the big.LITTLE
1557 system architecture.
1560 bool "big.LITTLE switcher support"
1561 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1563 select ARM_CPU_SUSPEND
1565 The big.LITTLE "switcher" provides the core functionality to
1566 transparently handle transition between a cluster of A15's
1567 and a cluster of A7's in a big.LITTLE system.
1569 config BL_SWITCHER_DUMMY_IF
1570 tristate "Simple big.LITTLE switcher user interface"
1571 depends on BL_SWITCHER && DEBUG_KERNEL
1573 This is a simple and dummy char dev interface to control
1574 the big.LITTLE switcher core code. It is meant for
1575 debugging purposes only.
1578 prompt "Memory split"
1581 Select the desired split between kernel and user memory.
1583 If you are not absolutely sure what you are doing, leave this
1587 bool "3G/1G user/kernel split"
1589 bool "2G/2G user/kernel split"
1591 bool "1G/3G user/kernel split"
1596 default 0x40000000 if VMSPLIT_1G
1597 default 0x80000000 if VMSPLIT_2G
1601 int "Maximum number of CPUs (2-32)"
1607 bool "Support for hot-pluggable CPUs"
1610 Say Y here to experiment with turning CPUs off and on. CPUs
1611 can be controlled through /sys/devices/system/cpu.
1614 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1617 Say Y here if you want Linux to communicate with system firmware
1618 implementing the PSCI specification for CPU-centric power
1619 management operations described in ARM document number ARM DEN
1620 0022A ("Power State Coordination Interface System Software on
1623 # The GPIO number here must be sorted by descending number. In case of
1624 # a multiplatform kernel, we just want the highest value required by the
1625 # selected platforms.
1628 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1629 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1630 default 392 if ARCH_U8500
1631 default 352 if ARCH_VT8500
1632 default 288 if ARCH_SUNXI
1633 default 264 if MACH_H4700
1636 Maximum number of GPIOs in the system.
1638 If unsure, leave the default value.
1640 source kernel/Kconfig.preempt
1644 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1645 ARCH_S5PV210 || ARCH_EXYNOS4
1646 default AT91_TIMER_HZ if ARCH_AT91
1647 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1651 depends on HZ_FIXED = 0
1652 prompt "Timer frequency"
1676 default HZ_FIXED if HZ_FIXED != 0
1677 default 100 if HZ_100
1678 default 200 if HZ_200
1679 default 250 if HZ_250
1680 default 300 if HZ_300
1681 default 500 if HZ_500
1685 def_bool HIGH_RES_TIMERS
1688 def_bool HIGH_RES_TIMERS
1690 config THUMB2_KERNEL
1691 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1692 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1693 default y if CPU_THUMBONLY
1695 select ARM_ASM_UNIFIED
1698 By enabling this option, the kernel will be compiled in
1699 Thumb-2 mode. A compiler/assembler that understand the unified
1700 ARM-Thumb syntax is needed.
1704 config THUMB2_AVOID_R_ARM_THM_JUMP11
1705 bool "Work around buggy Thumb-2 short branch relocations in gas"
1706 depends on THUMB2_KERNEL && MODULES
1709 Various binutils versions can resolve Thumb-2 branches to
1710 locally-defined, preemptible global symbols as short-range "b.n"
1711 branch instructions.
1713 This is a problem, because there's no guarantee the final
1714 destination of the symbol, or any candidate locations for a
1715 trampoline, are within range of the branch. For this reason, the
1716 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1717 relocation in modules at all, and it makes little sense to add
1720 The symptom is that the kernel fails with an "unsupported
1721 relocation" error when loading some modules.
1723 Until fixed tools are available, passing
1724 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1725 code which hits this problem, at the cost of a bit of extra runtime
1726 stack usage in some cases.
1728 The problem is described in more detail at:
1729 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1731 Only Thumb-2 kernels are affected.
1733 Unless you are sure your tools don't have this problem, say Y.
1735 config ARM_ASM_UNIFIED
1739 bool "Use the ARM EABI to compile the kernel"
1741 This option allows for the kernel to be compiled using the latest
1742 ARM ABI (aka EABI). This is only useful if you are using a user
1743 space environment that is also compiled with EABI.
1745 Since there are major incompatibilities between the legacy ABI and
1746 EABI, especially with regard to structure member alignment, this
1747 option also changes the kernel syscall calling convention to
1748 disambiguate both ABIs and allow for backward compatibility support
1749 (selected with CONFIG_OABI_COMPAT).
1751 To use this you need GCC version 4.0.0 or later.
1754 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1755 depends on AEABI && !THUMB2_KERNEL
1758 This option preserves the old syscall interface along with the
1759 new (ARM EABI) one. It also provides a compatibility layer to
1760 intercept syscalls that have structure arguments which layout
1761 in memory differs between the legacy ABI and the new ARM EABI
1762 (only for non "thumb" binaries). This option adds a tiny
1763 overhead to all syscalls and produces a slightly larger kernel.
1764 If you know you'll be using only pure EABI user space then you
1765 can say N here. If this option is not selected and you attempt
1766 to execute a legacy ABI binary then the result will be
1767 UNPREDICTABLE (in fact it can be predicted that it won't work
1768 at all). If in doubt say Y.
1770 config ARCH_HAS_HOLES_MEMORYMODEL
1773 config ARCH_SPARSEMEM_ENABLE
1776 config ARCH_SPARSEMEM_DEFAULT
1777 def_bool ARCH_SPARSEMEM_ENABLE
1779 config ARCH_SELECT_MEMORY_MODEL
1780 def_bool ARCH_SPARSEMEM_ENABLE
1782 config HAVE_ARCH_PFN_VALID
1783 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1786 bool "High Memory Support"
1789 The address space of ARM processors is only 4 Gigabytes large
1790 and it has to accommodate user address space, kernel address
1791 space as well as some memory mapped IO. That means that, if you
1792 have a large amount of physical memory and/or IO, not all of the
1793 memory can be "permanently mapped" by the kernel. The physical
1794 memory that is not permanently mapped is called "high memory".
1796 Depending on the selected kernel/user memory split, minimum
1797 vmalloc space and actual amount of RAM, you may not need this
1798 option which should result in a slightly faster kernel.
1803 bool "Allocate 2nd-level pagetables from highmem"
1806 config HW_PERF_EVENTS
1807 bool "Enable hardware performance counter support for perf events"
1808 depends on PERF_EVENTS
1811 Enable hardware performance counter support for perf events. If
1812 disabled, perf events will use software events only.
1814 config SYS_SUPPORTS_HUGETLBFS
1818 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1822 config ARCH_WANT_GENERAL_HUGETLB
1827 config FORCE_MAX_ZONEORDER
1828 int "Maximum zone order" if ARCH_SHMOBILE
1829 range 11 64 if ARCH_SHMOBILE
1830 default "12" if SOC_AM33XX
1831 default "9" if SA1111
1834 The kernel memory allocator divides physically contiguous memory
1835 blocks into "zones", where each zone is a power of two number of
1836 pages. This option selects the largest power of two that the kernel
1837 keeps in the memory allocator. If you need to allocate very large
1838 blocks of physically contiguous memory, then you may need to
1839 increase this value.
1841 This config option is actually maximum order plus one. For example,
1842 a value of 11 means that the largest free memory block is 2^10 pages.
1844 config ALIGNMENT_TRAP
1846 depends on CPU_CP15_MMU
1847 default y if !ARCH_EBSA110
1848 select HAVE_PROC_CPU if PROC_FS
1850 ARM processors cannot fetch/store information which is not
1851 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1852 address divisible by 4. On 32-bit ARM processors, these non-aligned
1853 fetch/store instructions will be emulated in software if you say
1854 here, which has a severe performance impact. This is necessary for
1855 correct operation of some network protocols. With an IP-only
1856 configuration it is safe to say N, otherwise say Y.
1858 config UACCESS_WITH_MEMCPY
1859 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1861 default y if CPU_FEROCEON
1863 Implement faster copy_to_user and clear_user methods for CPU
1864 cores where a 8-word STM instruction give significantly higher
1865 memory write throughput than a sequence of individual 32bit stores.
1867 A possible side effect is a slight increase in scheduling latency
1868 between threads sharing the same address space if they invoke
1869 such copy operations with large buffers.
1871 However, if the CPU data cache is using a write-allocate mode,
1872 this option is unlikely to provide any performance gain.
1876 prompt "Enable seccomp to safely compute untrusted bytecode"
1878 This kernel feature is useful for number crunching applications
1879 that may need to compute untrusted bytecode during their
1880 execution. By using pipes or other transports made available to
1881 the process as file descriptors supporting the read/write
1882 syscalls, it's possible to isolate those applications in
1883 their own address space using seccomp. Once seccomp is
1884 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1885 and the task is only allowed to execute a few safe syscalls
1886 defined by each seccomp mode.
1888 config CC_STACKPROTECTOR
1889 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1891 This option turns on the -fstack-protector GCC feature. This
1892 feature puts, at the beginning of functions, a canary value on
1893 the stack just before the return address, and validates
1894 the value just before actually returning. Stack based buffer
1895 overflows (that need to overwrite this return address) now also
1896 overwrite the canary, which gets detected and the attack is then
1897 neutralized via a kernel panic.
1898 This feature requires gcc version 4.2 or above.
1905 bool "Xen guest support on ARM (EXPERIMENTAL)"
1906 depends on ARM && AEABI && OF
1907 depends on CPU_V7 && !CPU_V6
1908 depends on !GENERIC_ATOMIC64
1911 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1918 bool "Flattened Device Tree support"
1921 select OF_EARLY_FLATTREE
1923 Include support for flattened device tree machine descriptions.
1926 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1929 This is the traditional way of passing data to the kernel at boot
1930 time. If you are solely relying on the flattened device tree (or
1931 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1932 to remove ATAGS support from your kernel binary. If unsure,
1935 config DEPRECATED_PARAM_STRUCT
1936 bool "Provide old way to pass kernel parameters"
1939 This was deprecated in 2001 and announced to live on for 5 years.
1940 Some old boot loaders still use this way.
1942 # Compressed boot loader in ROM. Yes, we really want to ask about
1943 # TEXT and BSS so we preserve their values in the config files.
1944 config ZBOOT_ROM_TEXT
1945 hex "Compressed ROM boot loader base address"
1948 The physical address at which the ROM-able zImage is to be
1949 placed in the target. Platforms which normally make use of
1950 ROM-able zImage formats normally set this to a suitable
1951 value in their defconfig file.
1953 If ZBOOT_ROM is not enabled, this has no effect.
1955 config ZBOOT_ROM_BSS
1956 hex "Compressed ROM boot loader BSS address"
1959 The base address of an area of read/write memory in the target
1960 for the ROM-able zImage which must be available while the
1961 decompressor is running. It must be large enough to hold the
1962 entire decompressed kernel plus an additional 128 KiB.
1963 Platforms which normally make use of ROM-able zImage formats
1964 normally set this to a suitable value in their defconfig file.
1966 If ZBOOT_ROM is not enabled, this has no effect.
1969 bool "Compressed boot loader in ROM/flash"
1970 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1972 Say Y here if you intend to execute your compressed kernel image
1973 (zImage) directly from ROM or flash. If unsure, say N.
1976 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1977 depends on ZBOOT_ROM && ARCH_SH7372
1978 default ZBOOT_ROM_NONE
1980 Include experimental SD/MMC loading code in the ROM-able zImage.
1981 With this enabled it is possible to write the ROM-able zImage
1982 kernel image to an MMC or SD card and boot the kernel straight
1983 from the reset vector. At reset the processor Mask ROM will load
1984 the first part of the ROM-able zImage which in turn loads the
1985 rest the kernel image to RAM.
1987 config ZBOOT_ROM_NONE
1988 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1990 Do not load image from SD or MMC
1992 config ZBOOT_ROM_MMCIF
1993 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1995 Load image from MMCIF hardware block.
1997 config ZBOOT_ROM_SH_MOBILE_SDHI
1998 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2000 Load image from SDHI hardware block
2004 config ARM_APPENDED_DTB
2005 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2006 depends on OF && !ZBOOT_ROM
2008 With this option, the boot code will look for a device tree binary
2009 (DTB) appended to zImage
2010 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2012 This is meant as a backward compatibility convenience for those
2013 systems with a bootloader that can't be upgraded to accommodate
2014 the documented boot protocol using a device tree.
2016 Beware that there is very little in terms of protection against
2017 this option being confused by leftover garbage in memory that might
2018 look like a DTB header after a reboot if no actual DTB is appended
2019 to zImage. Do not leave this option active in a production kernel
2020 if you don't intend to always append a DTB. Proper passing of the
2021 location into r2 of a bootloader provided DTB is always preferable
2024 config ARM_ATAG_DTB_COMPAT
2025 bool "Supplement the appended DTB with traditional ATAG information"
2026 depends on ARM_APPENDED_DTB
2028 Some old bootloaders can't be updated to a DTB capable one, yet
2029 they provide ATAGs with memory configuration, the ramdisk address,
2030 the kernel cmdline string, etc. Such information is dynamically
2031 provided by the bootloader and can't always be stored in a static
2032 DTB. To allow a device tree enabled kernel to be used with such
2033 bootloaders, this option allows zImage to extract the information
2034 from the ATAG list and store it at run time into the appended DTB.
2037 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2038 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2040 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2041 bool "Use bootloader kernel arguments if available"
2043 Uses the command-line options passed by the boot loader instead of
2044 the device tree bootargs property. If the boot loader doesn't provide
2045 any, the device tree bootargs property will be used.
2047 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2048 bool "Extend with bootloader kernel arguments"
2050 The command-line arguments provided by the boot loader will be
2051 appended to the the device tree bootargs property.
2056 string "Default kernel command string"
2059 On some architectures (EBSA110 and CATS), there is currently no way
2060 for the boot loader to pass arguments to the kernel. For these
2061 architectures, you should supply some command-line options at build
2062 time by entering them here. As a minimum, you should specify the
2063 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2066 prompt "Kernel command line type" if CMDLINE != ""
2067 default CMDLINE_FROM_BOOTLOADER
2070 config CMDLINE_FROM_BOOTLOADER
2071 bool "Use bootloader kernel arguments if available"
2073 Uses the command-line options passed by the boot loader. If
2074 the boot loader doesn't provide any, the default kernel command
2075 string provided in CMDLINE will be used.
2077 config CMDLINE_EXTEND
2078 bool "Extend bootloader kernel arguments"
2080 The command-line arguments provided by the boot loader will be
2081 appended to the default kernel command string.
2083 config CMDLINE_FORCE
2084 bool "Always use the default kernel command string"
2086 Always use the default kernel command string, even if the boot
2087 loader passes other arguments to the kernel.
2088 This is useful if you cannot or don't want to change the
2089 command-line options your boot loader passes to the kernel.
2093 bool "Kernel Execute-In-Place from ROM"
2094 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2096 Execute-In-Place allows the kernel to run from non-volatile storage
2097 directly addressable by the CPU, such as NOR flash. This saves RAM
2098 space since the text section of the kernel is not loaded from flash
2099 to RAM. Read-write sections, such as the data section and stack,
2100 are still copied to RAM. The XIP kernel is not compressed since
2101 it has to run directly from flash, so it will take more space to
2102 store it. The flash address used to link the kernel object files,
2103 and for storing it, is configuration dependent. Therefore, if you
2104 say Y here, you must know the proper physical address where to
2105 store the kernel image depending on your own flash memory usage.
2107 Also note that the make target becomes "make xipImage" rather than
2108 "make zImage" or "make Image". The final kernel binary to put in
2109 ROM memory will be arch/arm/boot/xipImage.
2113 config XIP_PHYS_ADDR
2114 hex "XIP Kernel Physical Location"
2115 depends on XIP_KERNEL
2116 default "0x00080000"
2118 This is the physical address in your flash memory the kernel will
2119 be linked for and stored to. This address is dependent on your
2123 bool "Kexec system call (EXPERIMENTAL)"
2124 depends on (!SMP || PM_SLEEP_SMP)
2126 kexec is a system call that implements the ability to shutdown your
2127 current kernel, and to start another kernel. It is like a reboot
2128 but it is independent of the system firmware. And like a reboot
2129 you can start any kernel with it, not just Linux.
2131 It is an ongoing process to be certain the hardware in a machine
2132 is properly shutdown, so do not be surprised if this code does not
2133 initially work for you.
2136 bool "Export atags in procfs"
2137 depends on ATAGS && KEXEC
2140 Should the atags used to boot the kernel be exported in an "atags"
2141 file in procfs. Useful with kexec.
2144 bool "Build kdump crash kernel (EXPERIMENTAL)"
2146 Generate crash dump after being started by kexec. This should
2147 be normally only set in special crash dump kernels which are
2148 loaded in the main kernel with kexec-tools into a specially
2149 reserved region and then later executed after a crash by
2150 kdump/kexec. The crash dump kernel must be compiled to a
2151 memory address not used by the main kernel
2153 For more details see Documentation/kdump/kdump.txt
2155 config AUTO_ZRELADDR
2156 bool "Auto calculation of the decompressed kernel image address"
2157 depends on !ZBOOT_ROM
2159 ZRELADDR is the physical address where the decompressed kernel
2160 image will be placed. If AUTO_ZRELADDR is selected, the address
2161 will be determined at run-time by masking the current IP with
2162 0xf8000000. This assumes the zImage being placed in the first 128MB
2163 from start of memory.
2167 menu "CPU Power Management"
2170 source "drivers/cpufreq/Kconfig"
2173 source "drivers/cpuidle/Kconfig"
2177 menu "Floating point emulation"
2179 comment "At least one emulation must be selected"
2182 bool "NWFPE math emulation"
2183 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2185 Say Y to include the NWFPE floating point emulator in the kernel.
2186 This is necessary to run most binaries. Linux does not currently
2187 support floating point hardware so you need to say Y here even if
2188 your machine has an FPA or floating point co-processor podule.
2190 You may say N here if you are going to load the Acorn FPEmulator
2191 early in the bootup.
2194 bool "Support extended precision"
2195 depends on FPE_NWFPE
2197 Say Y to include 80-bit support in the kernel floating-point
2198 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2199 Note that gcc does not generate 80-bit operations by default,
2200 so in most cases this option only enlarges the size of the
2201 floating point emulator without any good reason.
2203 You almost surely want to say N here.
2206 bool "FastFPE math emulation (EXPERIMENTAL)"
2207 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2209 Say Y here to include the FAST floating point emulator in the kernel.
2210 This is an experimental much faster emulator which now also has full
2211 precision for the mantissa. It does not support any exceptions.
2212 It is very simple, and approximately 3-6 times faster than NWFPE.
2214 It should be sufficient for most programs. It may be not suitable
2215 for scientific calculations, but you have to check this for yourself.
2216 If you do not feel you need a faster FP emulation you should better
2220 bool "VFP-format floating point maths"
2221 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2223 Say Y to include VFP support code in the kernel. This is needed
2224 if your hardware includes a VFP unit.
2226 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2227 release notes and additional status information.
2229 Say N if your target does not have VFP hardware.
2237 bool "Advanced SIMD (NEON) Extension support"
2238 depends on VFPv3 && CPU_V7
2240 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2243 config KERNEL_MODE_NEON
2244 bool "Support for NEON in kernel mode"
2245 depends on NEON && AEABI
2247 Say Y to include support for NEON in kernel mode.
2251 menu "Userspace binary formats"
2253 source "fs/Kconfig.binfmt"
2256 tristate "RISC OS personality"
2259 Say Y here to include the kernel code necessary if you want to run
2260 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2261 experimental; if this sounds frightening, say N and sleep in peace.
2262 You can also say M here to compile this support as a module (which
2263 will be called arthur).
2267 menu "Power management options"
2269 source "kernel/power/Kconfig"
2271 config ARCH_SUSPEND_POSSIBLE
2272 depends on !ARCH_S5PC100
2273 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2274 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2277 config ARM_CPU_SUSPEND
2282 source "net/Kconfig"
2284 source "drivers/Kconfig"
2288 source "arch/arm/Kconfig.debug"
2290 source "security/Kconfig"
2292 source "crypto/Kconfig"
2294 source "lib/Kconfig"
2296 source "arch/arm/kvm/Kconfig"