4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_EXIT_THREAD
54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59 select HAVE_IDE if PCI || ISA || PCMCIA
60 select HAVE_IRQ_TIME_ACCOUNTING
61 select HAVE_KERNEL_GZIP
62 select HAVE_KERNEL_LZ4
63 select HAVE_KERNEL_LZMA
64 select HAVE_KERNEL_LZO
66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67 select HAVE_KRETPROBES if (HAVE_KPROBES)
69 select HAVE_MOD_ARCH_SPECIFIC
70 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
71 select HAVE_OPTPROBES if !THUMB2_KERNEL
72 select HAVE_PERF_EVENTS
74 select HAVE_PERF_USER_STACK_DUMP
75 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
76 select HAVE_REGS_AND_STACK_ACCESS_API
77 select HAVE_SYSCALL_TRACEPOINTS
79 select HAVE_VIRT_CPU_ACCOUNTING_GEN
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_REL
83 select OF_EARLY_FLATTREE if OF
84 select OF_RESERVED_MEM if OF
86 select OLD_SIGSUSPEND3
87 select PERF_USE_VMALLOC
89 select SYS_SUPPORTS_APM_EMULATION
90 # Above selects are sorted alphabetically; please add new ones
91 # according to that. Thanks.
93 The ARM series is a line of low-power-consumption RISC chip designs
94 licensed by ARM Ltd and targeted at embedded applications and
95 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
96 manufactured, but legacy ARM-based PC hardware remains popular in
97 Europe. There is an ARM Linux project with a web page at
98 <http://www.arm.linux.org.uk/>.
100 config ARM_HAS_SG_CHAIN
101 select ARCH_HAS_SG_CHAIN
104 config NEED_SG_DMA_LENGTH
107 config ARM_DMA_USE_IOMMU
109 select ARM_HAS_SG_CHAIN
110 select NEED_SG_DMA_LENGTH
114 config ARM_DMA_IOMMU_ALIGNMENT
115 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
119 DMA mapping framework by default aligns all buffers to the smallest
120 PAGE_SIZE order which is greater than or equal to the requested buffer
121 size. This works well for buffers up to a few hundreds kilobytes, but
122 for larger buffers it just a waste of address space. Drivers which has
123 relatively small addressing window (like 64Mib) might run out of
124 virtual space with just a few allocations.
126 With this parameter you can specify the maximum PAGE_SIZE order for
127 DMA IOMMU buffers. Larger buffers will be aligned only to this
128 specified order. The order is expressed as a power of two multiplied
133 config MIGHT_HAVE_PCI
136 config SYS_SUPPORTS_APM_EMULATION
141 select GENERIC_ALLOCATOR
152 The Extended Industry Standard Architecture (EISA) bus was
153 developed as an open alternative to the IBM MicroChannel bus.
155 The EISA bus provided some of the features of the IBM MicroChannel
156 bus while maintaining backward compatibility with cards made for
157 the older ISA bus. The EISA bus saw limited use between 1988 and
158 1995 when it was made obsolete by the PCI bus.
160 Say Y here if you are building a kernel for an EISA-based machine.
167 config STACKTRACE_SUPPORT
171 config LOCKDEP_SUPPORT
175 config TRACE_IRQFLAGS_SUPPORT
179 config RWSEM_XCHGADD_ALGORITHM
183 config ARCH_HAS_ILOG2_U32
186 config ARCH_HAS_ILOG2_U64
189 config ARCH_HAS_BANDGAP
192 config FIX_EARLYCON_MEM
195 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
203 config ARCH_MAY_HAVE_PC_FDC
209 config NEED_DMA_MAP_STATE
212 config ARCH_SUPPORTS_UPROBES
215 config ARCH_HAS_DMA_SET_COHERENT_MASK
218 config GENERIC_ISA_DMA
224 config NEED_RET_TO_USER
232 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
233 default DRAM_BASE if REMAP_VECTORS_TO_RAM
236 The base address of exception vectors. This must be two pages
239 config ARM_PATCH_PHYS_VIRT
240 bool "Patch physical to virtual translations at runtime" if EMBEDDED
242 depends on !XIP_KERNEL && MMU
244 Patch phys-to-virt and virt-to-phys translation functions at
245 boot and module load time according to the position of the
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 16MB boundary.
251 Only disable this option if you know that you do not require
252 this feature (eg, building a kernel for a single machine) and
253 you need to shrink the kernel to the minimal size.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT
272 default DRAM_BASE if !MMU
273 default 0x00000000 if ARCH_EBSA110 || \
278 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
279 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
280 default 0x20000000 if ARCH_S5PV210
281 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
282 default 0xc0000000 if ARCH_SA1100
284 Please provide the physical address corresponding to the
285 location of main memory in your system.
291 config PGTABLE_LEVELS
293 default 3 if ARM_LPAE
296 source "init/Kconfig"
298 source "kernel/Kconfig.freezer"
303 bool "MMU-based Paged Memory Management Support"
306 Select if you want MMU-based virtualised addressing space
307 support by paged memory management. If unsure, say 'Y'.
309 config ARCH_MMAP_RND_BITS_MIN
312 config ARCH_MMAP_RND_BITS_MAX
313 default 14 if PAGE_OFFSET=0x40000000
314 default 15 if PAGE_OFFSET=0x80000000
318 # The "ARM system type" choice list is ordered alphabetically by option
319 # text. Please add new entries in the option alphabetic order.
322 prompt "ARM system type"
323 default ARM_SINGLE_ARMV7M if !MMU
324 default ARCH_MULTIPLATFORM if MMU
326 config ARCH_MULTIPLATFORM
327 bool "Allow multiple platforms to be selected"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_HAS_SG_CHAIN
331 select ARM_PATCH_PHYS_VIRT
335 select GENERIC_CLOCKEVENTS
336 select MIGHT_HAVE_PCI
337 select MULTI_IRQ_HANDLER
341 config ARM_SINGLE_ARMV7M
342 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select GENERIC_CLOCKEVENTS
357 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
358 select ARCH_REQUIRE_GPIOLIB
363 select GENERIC_CLOCKEVENTS
367 Support for Cirrus Logic 711x/721x/731x based boards.
370 bool "Cortina Systems Gemini"
371 select ARCH_REQUIRE_GPIOLIB
374 select GENERIC_CLOCKEVENTS
376 Support for the Cortina Systems Gemini family SoCs
380 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_IO_H
384 select NEED_MACH_MEMORY_H
387 This is an evaluation board for the StrongARM processor available
388 from Digital. It has limited hardware on-board, including an
389 Ethernet interface, two PCMCIA sockets, two serial ports and a
394 select ARCH_HAS_HOLES_MEMORYMODEL
395 select ARCH_REQUIRE_GPIOLIB
397 select ARM_PATCH_PHYS_VIRT
403 select GENERIC_CLOCKEVENTS
405 This enables support for the Cirrus EP93xx series of CPUs.
407 config ARCH_FOOTBRIDGE
411 select GENERIC_CLOCKEVENTS
413 select NEED_MACH_IO_H if !MMU
414 select NEED_MACH_MEMORY_H
416 Support for systems based on the DC21285 companion chip
417 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
420 bool "Hilscher NetX based"
424 select GENERIC_CLOCKEVENTS
426 This enables support for systems based on the Hilscher NetX Soc
432 select NEED_MACH_MEMORY_H
433 select NEED_RET_TO_USER
439 Support for Intel's IOP13XX (XScale) family of processors.
444 select ARCH_REQUIRE_GPIOLIB
447 select NEED_RET_TO_USER
451 Support for Intel's 80219 and IOP32X (XScale) family of
457 select ARCH_REQUIRE_GPIOLIB
460 select NEED_RET_TO_USER
464 Support for Intel's IOP33X (XScale) family of processors.
469 select ARCH_HAS_DMA_SET_COHERENT_MASK
470 select ARCH_REQUIRE_GPIOLIB
471 select ARCH_SUPPORTS_BIG_ENDIAN
474 select DMABOUNCE if PCI
475 select GENERIC_CLOCKEVENTS
476 select MIGHT_HAVE_PCI
477 select NEED_MACH_IO_H
478 select USB_EHCI_BIG_ENDIAN_DESC
479 select USB_EHCI_BIG_ENDIAN_MMIO
481 Support for Intel's IXP4XX (XScale) family of processors.
485 select ARCH_REQUIRE_GPIOLIB
487 select GENERIC_CLOCKEVENTS
488 select MIGHT_HAVE_PCI
489 select MULTI_IRQ_HANDLER
493 select PLAT_ORION_LEGACY
495 select PM_GENERIC_DOMAINS if PM
497 Support for the Marvell Dove SoC 88AP510
500 bool "Micrel/Kendin KS8695"
501 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select NEED_MACH_MEMORY_H
507 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
508 System-on-Chip devices.
511 bool "Nuvoton W90X900 CPU"
512 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
518 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
519 At present, the w90x900 has been renamed nuc900, regarding
520 the ARM series product line, you can login the following
521 link address to know more.
523 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
524 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
528 select ARCH_REQUIRE_GPIOLIB
531 select CLKSRC_LPC32XX
534 select GENERIC_CLOCKEVENTS
535 select MULTI_IRQ_HANDLER
539 Support for the NXP LPC32XX family of processors
542 bool "PXA2xx/PXA3xx-based"
545 select ARCH_REQUIRE_GPIOLIB
546 select ARM_CPU_SUSPEND if PM
553 select CPU_XSCALE if !CPU_XSC3
554 select GENERIC_CLOCKEVENTS
558 select MULTI_IRQ_HANDLER
562 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
568 select ARCH_MAY_HAVE_PC_FDC
569 select ARCH_SPARSEMEM_ENABLE
570 select ARCH_USES_GETTIMEOFFSET
574 select HAVE_PATA_PLATFORM
576 select NEED_MACH_IO_H
577 select NEED_MACH_MEMORY_H
580 On the Acorn Risc-PC, Linux can support the internal IDE disk and
581 CD-ROM interface, serial and parallel port, and the floppy drive.
586 select ARCH_REQUIRE_GPIOLIB
587 select ARCH_SPARSEMEM_ENABLE
591 select CLKSRC_OF if OF
594 select GENERIC_CLOCKEVENTS
598 select MULTI_IRQ_HANDLER
599 select NEED_MACH_MEMORY_H
602 Support for StrongARM 11x0 based boards.
605 bool "Samsung S3C24XX SoCs"
606 select ARCH_REQUIRE_GPIOLIB
609 select CLKSRC_SAMSUNG_PWM
610 select GENERIC_CLOCKEVENTS
612 select HAVE_S3C2410_I2C if I2C
613 select HAVE_S3C2410_WATCHDOG if WATCHDOG
614 select HAVE_S3C_RTC if RTC_CLASS
615 select MULTI_IRQ_HANDLER
616 select NEED_MACH_IO_H
619 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
620 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
621 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
622 Samsung SMDK2410 development board (and derivatives).
626 select ARCH_HAS_HOLES_MEMORYMODEL
627 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_ALLOCATOR
631 select GENERIC_CLOCKEVENTS
632 select GENERIC_IRQ_CHIP
637 Support for TI's DaVinci platform.
642 select ARCH_HAS_HOLES_MEMORYMODEL
644 select ARCH_REQUIRE_GPIOLIB
647 select GENERIC_CLOCKEVENTS
648 select GENERIC_IRQ_CHIP
651 select MULTI_IRQ_HANDLER
652 select NEED_MACH_IO_H if PCCARD
653 select NEED_MACH_MEMORY_H
656 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
660 menu "Multiple platform selection"
661 depends on ARCH_MULTIPLATFORM
663 comment "CPU Core family selection"
666 bool "ARMv4 based platforms (FA526)"
667 depends on !ARCH_MULTI_V6_V7
668 select ARCH_MULTI_V4_V5
671 config ARCH_MULTI_V4T
672 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
673 depends on !ARCH_MULTI_V6_V7
674 select ARCH_MULTI_V4_V5
675 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
676 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
677 CPU_ARM925T || CPU_ARM940T)
680 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
681 depends on !ARCH_MULTI_V6_V7
682 select ARCH_MULTI_V4_V5
683 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
684 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
685 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
687 config ARCH_MULTI_V4_V5
691 bool "ARMv6 based platforms (ARM11)"
692 select ARCH_MULTI_V6_V7
696 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
698 select ARCH_MULTI_V6_V7
702 config ARCH_MULTI_V6_V7
704 select MIGHT_HAVE_CACHE_L2X0
706 config ARCH_MULTI_CPU_AUTO
707 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
713 bool "Dummy Virtual Machine"
714 depends on ARCH_MULTI_V7
717 select ARM_GIC_V2M if PCI_MSI
720 select HAVE_ARM_ARCH_TIMER
723 # This is sorted alphabetically by mach-* pathname. However, plat-*
724 # Kconfigs may be included either alphabetically (according to the
725 # plat- suffix) or along side the corresponding mach-* source.
727 source "arch/arm/mach-mvebu/Kconfig"
729 source "arch/arm/mach-alpine/Kconfig"
731 source "arch/arm/mach-artpec/Kconfig"
733 source "arch/arm/mach-asm9260/Kconfig"
735 source "arch/arm/mach-at91/Kconfig"
737 source "arch/arm/mach-axxia/Kconfig"
739 source "arch/arm/mach-bcm/Kconfig"
741 source "arch/arm/mach-berlin/Kconfig"
743 source "arch/arm/mach-clps711x/Kconfig"
745 source "arch/arm/mach-cns3xxx/Kconfig"
747 source "arch/arm/mach-davinci/Kconfig"
749 source "arch/arm/mach-digicolor/Kconfig"
751 source "arch/arm/mach-dove/Kconfig"
753 source "arch/arm/mach-ep93xx/Kconfig"
755 source "arch/arm/mach-footbridge/Kconfig"
757 source "arch/arm/mach-gemini/Kconfig"
759 source "arch/arm/mach-highbank/Kconfig"
761 source "arch/arm/mach-hisi/Kconfig"
763 source "arch/arm/mach-integrator/Kconfig"
765 source "arch/arm/mach-iop32x/Kconfig"
767 source "arch/arm/mach-iop33x/Kconfig"
769 source "arch/arm/mach-iop13xx/Kconfig"
771 source "arch/arm/mach-ixp4xx/Kconfig"
773 source "arch/arm/mach-keystone/Kconfig"
775 source "arch/arm/mach-ks8695/Kconfig"
777 source "arch/arm/mach-meson/Kconfig"
779 source "arch/arm/mach-moxart/Kconfig"
781 source "arch/arm/mach-aspeed/Kconfig"
783 source "arch/arm/mach-mv78xx0/Kconfig"
785 source "arch/arm/mach-imx/Kconfig"
787 source "arch/arm/mach-mediatek/Kconfig"
789 source "arch/arm/mach-mxs/Kconfig"
791 source "arch/arm/mach-netx/Kconfig"
793 source "arch/arm/mach-nomadik/Kconfig"
795 source "arch/arm/mach-nspire/Kconfig"
797 source "arch/arm/plat-omap/Kconfig"
799 source "arch/arm/mach-omap1/Kconfig"
801 source "arch/arm/mach-omap2/Kconfig"
803 source "arch/arm/mach-orion5x/Kconfig"
805 source "arch/arm/mach-picoxcell/Kconfig"
807 source "arch/arm/mach-pxa/Kconfig"
808 source "arch/arm/plat-pxa/Kconfig"
810 source "arch/arm/mach-mmp/Kconfig"
812 source "arch/arm/mach-oxnas/Kconfig"
814 source "arch/arm/mach-qcom/Kconfig"
816 source "arch/arm/mach-realview/Kconfig"
818 source "arch/arm/mach-rockchip/Kconfig"
820 source "arch/arm/mach-sa1100/Kconfig"
822 source "arch/arm/mach-socfpga/Kconfig"
824 source "arch/arm/mach-spear/Kconfig"
826 source "arch/arm/mach-sti/Kconfig"
828 source "arch/arm/mach-s3c24xx/Kconfig"
830 source "arch/arm/mach-s3c64xx/Kconfig"
832 source "arch/arm/mach-s5pv210/Kconfig"
834 source "arch/arm/mach-exynos/Kconfig"
835 source "arch/arm/plat-samsung/Kconfig"
837 source "arch/arm/mach-shmobile/Kconfig"
839 source "arch/arm/mach-sunxi/Kconfig"
841 source "arch/arm/mach-prima2/Kconfig"
843 source "arch/arm/mach-tango/Kconfig"
845 source "arch/arm/mach-tegra/Kconfig"
847 source "arch/arm/mach-u300/Kconfig"
849 source "arch/arm/mach-uniphier/Kconfig"
851 source "arch/arm/mach-ux500/Kconfig"
853 source "arch/arm/mach-versatile/Kconfig"
855 source "arch/arm/mach-vexpress/Kconfig"
856 source "arch/arm/plat-versatile/Kconfig"
858 source "arch/arm/mach-vt8500/Kconfig"
860 source "arch/arm/mach-w90x900/Kconfig"
862 source "arch/arm/mach-zx/Kconfig"
864 source "arch/arm/mach-zynq/Kconfig"
866 # ARMv7-M architecture
868 bool "Energy Micro efm32"
869 depends on ARM_SINGLE_ARMV7M
870 select ARCH_REQUIRE_GPIOLIB
872 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
876 bool "NXP LPC18xx/LPC43xx"
877 depends on ARM_SINGLE_ARMV7M
878 select ARCH_HAS_RESET_CONTROLLER
880 select CLKSRC_LPC32XX
883 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
884 high performance microcontrollers.
887 bool "STMicrolectronics STM32"
888 depends on ARM_SINGLE_ARMV7M
889 select ARCH_HAS_RESET_CONTROLLER
890 select ARMV7M_SYSTICK
893 select RESET_CONTROLLER
895 Support for STMicroelectronics STM32 processors.
897 config MACH_STM32F429
898 bool "STMicrolectronics STM32F429"
899 depends on ARCH_STM32
903 bool "ARM MPS2 paltform"
904 depends on ARM_SINGLE_ARMV7M
908 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
909 with a range of available cores like Cortex-M3/M4/M7.
911 Please, note that depends which Application Note is used memory map
912 for the platform may vary, so adjustment of RAM base might be needed.
914 # Definitions to make life easier
920 select GENERIC_CLOCKEVENTS
926 select GENERIC_IRQ_CHIP
929 config PLAT_ORION_LEGACY
936 config PLAT_VERSATILE
939 source "arch/arm/firmware/Kconfig"
941 source arch/arm/mm/Kconfig
944 bool "Enable iWMMXt support"
945 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
946 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
948 Enable support for iWMMXt context switching at run time if
949 running on a CPU that supports it.
951 config MULTI_IRQ_HANDLER
954 Allow each machine to specify it's own IRQ handler at run time.
957 source "arch/arm/Kconfig-nommu"
960 config PJ4B_ERRATA_4742
961 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
962 depends on CPU_PJ4B && MACH_ARMADA_370
965 When coming out of either a Wait for Interrupt (WFI) or a Wait for
966 Event (WFE) IDLE states, a specific timing sensitivity exists between
967 the retiring WFI/WFE instructions and the newly issued subsequent
968 instructions. This sensitivity can result in a CPU hang scenario.
970 The software must insert either a Data Synchronization Barrier (DSB)
971 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
974 config ARM_ERRATA_326103
975 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
978 Executing a SWP instruction to read-only memory does not set bit 11
979 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
980 treat the access as a read, preventing a COW from occurring and
981 causing the faulting task to livelock.
983 config ARM_ERRATA_411920
984 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
985 depends on CPU_V6 || CPU_V6K
987 Invalidation of the Instruction Cache operation can
988 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
989 It does not affect the MPCore. This option enables the ARM Ltd.
990 recommended workaround.
992 config ARM_ERRATA_430973
993 bool "ARM errata: Stale prediction on replaced interworking branch"
996 This option enables the workaround for the 430973 Cortex-A8
997 r1p* erratum. If a code sequence containing an ARM/Thumb
998 interworking branch is replaced with another code sequence at the
999 same virtual address, whether due to self-modifying code or virtual
1000 to physical address re-mapping, Cortex-A8 does not recover from the
1001 stale interworking branch prediction. This results in Cortex-A8
1002 executing the new code sequence in the incorrect ARM or Thumb state.
1003 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1004 and also flushes the branch target cache at every context switch.
1005 Note that setting specific bits in the ACTLR register may not be
1006 available in non-secure mode.
1008 config ARM_ERRATA_458693
1009 bool "ARM errata: Processor deadlock when a false hazard is created"
1011 depends on !ARCH_MULTIPLATFORM
1013 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1014 erratum. For very specific sequences of memory operations, it is
1015 possible for a hazard condition intended for a cache line to instead
1016 be incorrectly associated with a different cache line. This false
1017 hazard might then cause a processor deadlock. The workaround enables
1018 the L1 caching of the NEON accesses and disables the PLD instruction
1019 in the ACTLR register. Note that setting specific bits in the ACTLR
1020 register may not be available in non-secure mode.
1022 config ARM_ERRATA_460075
1023 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1025 depends on !ARCH_MULTIPLATFORM
1027 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1028 erratum. Any asynchronous access to the L2 cache may encounter a
1029 situation in which recent store transactions to the L2 cache are lost
1030 and overwritten with stale memory contents from external memory. The
1031 workaround disables the write-allocate mode for the L2 cache via the
1032 ACTLR register. Note that setting specific bits in the ACTLR register
1033 may not be available in non-secure mode.
1035 config ARM_ERRATA_742230
1036 bool "ARM errata: DMB operation may be faulty"
1037 depends on CPU_V7 && SMP
1038 depends on !ARCH_MULTIPLATFORM
1040 This option enables the workaround for the 742230 Cortex-A9
1041 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1042 between two write operations may not ensure the correct visibility
1043 ordering of the two writes. This workaround sets a specific bit in
1044 the diagnostic register of the Cortex-A9 which causes the DMB
1045 instruction to behave as a DSB, ensuring the correct behaviour of
1048 config ARM_ERRATA_742231
1049 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1050 depends on CPU_V7 && SMP
1051 depends on !ARCH_MULTIPLATFORM
1053 This option enables the workaround for the 742231 Cortex-A9
1054 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1055 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1056 accessing some data located in the same cache line, may get corrupted
1057 data due to bad handling of the address hazard when the line gets
1058 replaced from one of the CPUs at the same time as another CPU is
1059 accessing it. This workaround sets specific bits in the diagnostic
1060 register of the Cortex-A9 which reduces the linefill issuing
1061 capabilities of the processor.
1063 config ARM_ERRATA_643719
1064 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1065 depends on CPU_V7 && SMP
1068 This option enables the workaround for the 643719 Cortex-A9 (prior to
1069 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1070 register returns zero when it should return one. The workaround
1071 corrects this value, ensuring cache maintenance operations which use
1072 it behave as intended and avoiding data corruption.
1074 config ARM_ERRATA_720789
1075 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1078 This option enables the workaround for the 720789 Cortex-A9 (prior to
1079 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1080 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1081 As a consequence of this erratum, some TLB entries which should be
1082 invalidated are not, resulting in an incoherency in the system page
1083 tables. The workaround changes the TLB flushing routines to invalidate
1084 entries regardless of the ASID.
1086 config ARM_ERRATA_743622
1087 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1089 depends on !ARCH_MULTIPLATFORM
1091 This option enables the workaround for the 743622 Cortex-A9
1092 (r2p*) erratum. Under very rare conditions, a faulty
1093 optimisation in the Cortex-A9 Store Buffer may lead to data
1094 corruption. This workaround sets a specific bit in the diagnostic
1095 register of the Cortex-A9 which disables the Store Buffer
1096 optimisation, preventing the defect from occurring. This has no
1097 visible impact on the overall performance or power consumption of the
1100 config ARM_ERRATA_751472
1101 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1103 depends on !ARCH_MULTIPLATFORM
1105 This option enables the workaround for the 751472 Cortex-A9 (prior
1106 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1107 completion of a following broadcasted operation if the second
1108 operation is received by a CPU before the ICIALLUIS has completed,
1109 potentially leading to corrupted entries in the cache or TLB.
1111 config ARM_ERRATA_754322
1112 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1115 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1116 r3p*) erratum. A speculative memory access may cause a page table walk
1117 which starts prior to an ASID switch but completes afterwards. This
1118 can populate the micro-TLB with a stale entry which may be hit with
1119 the new ASID. This workaround places two dsb instructions in the mm
1120 switching code so that no page table walks can cross the ASID switch.
1122 config ARM_ERRATA_754327
1123 bool "ARM errata: no automatic Store Buffer drain"
1124 depends on CPU_V7 && SMP
1126 This option enables the workaround for the 754327 Cortex-A9 (prior to
1127 r2p0) erratum. The Store Buffer does not have any automatic draining
1128 mechanism and therefore a livelock may occur if an external agent
1129 continuously polls a memory location waiting to observe an update.
1130 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1131 written polling loops from denying visibility of updates to memory.
1133 config ARM_ERRATA_364296
1134 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1137 This options enables the workaround for the 364296 ARM1136
1138 r0p2 erratum (possible cache data corruption with
1139 hit-under-miss enabled). It sets the undocumented bit 31 in
1140 the auxiliary control register and the FI bit in the control
1141 register, thus disabling hit-under-miss without putting the
1142 processor into full low interrupt latency mode. ARM11MPCore
1145 config ARM_ERRATA_764369
1146 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1147 depends on CPU_V7 && SMP
1149 This option enables the workaround for erratum 764369
1150 affecting Cortex-A9 MPCore with two or more processors (all
1151 current revisions). Under certain timing circumstances, a data
1152 cache line maintenance operation by MVA targeting an Inner
1153 Shareable memory region may fail to proceed up to either the
1154 Point of Coherency or to the Point of Unification of the
1155 system. This workaround adds a DSB instruction before the
1156 relevant cache maintenance functions and sets a specific bit
1157 in the diagnostic control register of the SCU.
1159 config ARM_ERRATA_775420
1160 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1163 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1164 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1165 operation aborts with MMU exception, it might cause the processor
1166 to deadlock. This workaround puts DSB before executing ISB if
1167 an abort may occur on cache maintenance.
1169 config ARM_ERRATA_798181
1170 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1171 depends on CPU_V7 && SMP
1173 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1174 adequately shooting down all use of the old entries. This
1175 option enables the Linux kernel workaround for this erratum
1176 which sends an IPI to the CPUs that are running the same ASID
1177 as the one being invalidated.
1179 config ARM_ERRATA_773022
1180 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1183 This option enables the workaround for the 773022 Cortex-A15
1184 (up to r0p4) erratum. In certain rare sequences of code, the
1185 loop buffer may deliver incorrect instructions. This
1186 workaround disables the loop buffer to avoid the erratum.
1190 source "arch/arm/common/Kconfig"
1197 Find out whether you have ISA slots on your motherboard. ISA is the
1198 name of a bus system, i.e. the way the CPU talks to the other stuff
1199 inside your box. Other bus systems are PCI, EISA, MicroChannel
1200 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1201 newer boards don't support it. If you have ISA, say Y, otherwise N.
1203 # Select ISA DMA controller support
1208 # Select ISA DMA interface
1213 bool "PCI support" if MIGHT_HAVE_PCI
1215 Find out whether you have a PCI motherboard. PCI is the name of a
1216 bus system, i.e. the way the CPU talks to the other stuff inside
1217 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1218 VESA. If you have PCI, say Y, otherwise N.
1224 config PCI_DOMAINS_GENERIC
1225 def_bool PCI_DOMAINS
1227 config PCI_NANOENGINE
1228 bool "BSE nanoEngine PCI support"
1229 depends on SA1100_NANOENGINE
1231 Enable PCI on the BSE nanoEngine board.
1236 config PCI_HOST_ITE8152
1238 depends on PCI && MACH_ARMCORE
1242 source "drivers/pci/Kconfig"
1244 source "drivers/pcmcia/Kconfig"
1248 menu "Kernel Features"
1253 This option should be selected by machines which have an SMP-
1256 The only effect of this option is to make the SMP-related
1257 options available to the user for configuration.
1260 bool "Symmetric Multi-Processing"
1261 depends on CPU_V6K || CPU_V7
1262 depends on GENERIC_CLOCKEVENTS
1264 depends on MMU || ARM_MPU
1267 This enables support for systems with more than one CPU. If you have
1268 a system with only one CPU, say N. If you have a system with more
1269 than one CPU, say Y.
1271 If you say N here, the kernel will run on uni- and multiprocessor
1272 machines, but will use only one CPU of a multiprocessor machine. If
1273 you say Y here, the kernel will run on many, but not all,
1274 uniprocessor machines. On a uniprocessor machine, the kernel
1275 will run faster if you say N here.
1277 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1278 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1279 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1281 If you don't know what to do here, say N.
1284 bool "Allow booting SMP kernel on uniprocessor systems"
1285 depends on SMP && !XIP_KERNEL && MMU
1288 SMP kernels contain instructions which fail on non-SMP processors.
1289 Enabling this option allows the kernel to modify itself to make
1290 these instructions safe. Disabling it allows about 1K of space
1293 If you don't know what to do here, say Y.
1295 config ARM_CPU_TOPOLOGY
1296 bool "Support cpu topology definition"
1297 depends on SMP && CPU_V7
1300 Support ARM cpu topology definition. The MPIDR register defines
1301 affinity between processors which is then used to describe the cpu
1302 topology of an ARM System.
1305 bool "Multi-core scheduler support"
1306 depends on ARM_CPU_TOPOLOGY
1308 Multi-core scheduler support improves the CPU scheduler's decision
1309 making when dealing with multi-core CPU chips at a cost of slightly
1310 increased overhead in some places. If unsure say N here.
1313 bool "SMT scheduler support"
1314 depends on ARM_CPU_TOPOLOGY
1316 Improves the CPU scheduler's decision making when dealing with
1317 MultiThreading at a cost of slightly increased overhead in some
1318 places. If unsure say N here.
1323 This option enables support for the ARM system coherency unit
1325 config HAVE_ARM_ARCH_TIMER
1326 bool "Architected timer support"
1328 select ARM_ARCH_TIMER
1329 select GENERIC_CLOCKEVENTS
1331 This option enables support for the ARM architected timer
1335 select CLKSRC_OF if OF
1337 This options enables support for the ARM timer and watchdog unit
1340 bool "Multi-Cluster Power Management"
1341 depends on CPU_V7 && SMP
1343 This option provides the common power management infrastructure
1344 for (multi-)cluster based systems, such as big.LITTLE based
1347 config MCPM_QUAD_CLUSTER
1351 To avoid wasting resources unnecessarily, MCPM only supports up
1352 to 2 clusters by default.
1353 Platforms with 3 or 4 clusters that use MCPM must select this
1354 option to allow the additional clusters to be managed.
1357 bool "big.LITTLE support (Experimental)"
1358 depends on CPU_V7 && SMP
1361 This option enables support selections for the big.LITTLE
1362 system architecture.
1365 bool "big.LITTLE switcher support"
1366 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1369 The big.LITTLE "switcher" provides the core functionality to
1370 transparently handle transition between a cluster of A15's
1371 and a cluster of A7's in a big.LITTLE system.
1373 config BL_SWITCHER_DUMMY_IF
1374 tristate "Simple big.LITTLE switcher user interface"
1375 depends on BL_SWITCHER && DEBUG_KERNEL
1377 This is a simple and dummy char dev interface to control
1378 the big.LITTLE switcher core code. It is meant for
1379 debugging purposes only.
1382 prompt "Memory split"
1386 Select the desired split between kernel and user memory.
1388 If you are not absolutely sure what you are doing, leave this
1392 bool "3G/1G user/kernel split"
1393 config VMSPLIT_3G_OPT
1394 bool "3G/1G user/kernel split (for full 1G low memory)"
1396 bool "2G/2G user/kernel split"
1398 bool "1G/3G user/kernel split"
1403 default PHYS_OFFSET if !MMU
1404 default 0x40000000 if VMSPLIT_1G
1405 default 0x80000000 if VMSPLIT_2G
1406 default 0xB0000000 if VMSPLIT_3G_OPT
1410 int "Maximum number of CPUs (2-32)"
1416 bool "Support for hot-pluggable CPUs"
1419 Say Y here to experiment with turning CPUs off and on. CPUs
1420 can be controlled through /sys/devices/system/cpu.
1423 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1424 depends on HAVE_ARM_SMCCC
1427 Say Y here if you want Linux to communicate with system firmware
1428 implementing the PSCI specification for CPU-centric power
1429 management operations described in ARM document number ARM DEN
1430 0022A ("Power State Coordination Interface System Software on
1433 # The GPIO number here must be sorted by descending number. In case of
1434 # a multiplatform kernel, we just want the highest value required by the
1435 # selected platforms.
1438 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1440 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1441 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1442 default 416 if ARCH_SUNXI
1443 default 392 if ARCH_U8500
1444 default 352 if ARCH_VT8500
1445 default 288 if ARCH_ROCKCHIP
1446 default 264 if MACH_H4700
1449 Maximum number of GPIOs in the system.
1451 If unsure, leave the default value.
1453 source kernel/Kconfig.preempt
1457 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1458 ARCH_S5PV210 || ARCH_EXYNOS4
1459 default 128 if SOC_AT91RM9200
1463 depends on HZ_FIXED = 0
1464 prompt "Timer frequency"
1488 default HZ_FIXED if HZ_FIXED != 0
1489 default 100 if HZ_100
1490 default 200 if HZ_200
1491 default 250 if HZ_250
1492 default 300 if HZ_300
1493 default 500 if HZ_500
1497 def_bool HIGH_RES_TIMERS
1499 config THUMB2_KERNEL
1500 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1501 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1502 default y if CPU_THUMBONLY
1504 select ARM_ASM_UNIFIED
1507 By enabling this option, the kernel will be compiled in
1508 Thumb-2 mode. A compiler/assembler that understand the unified
1509 ARM-Thumb syntax is needed.
1513 config THUMB2_AVOID_R_ARM_THM_JUMP11
1514 bool "Work around buggy Thumb-2 short branch relocations in gas"
1515 depends on THUMB2_KERNEL && MODULES
1518 Various binutils versions can resolve Thumb-2 branches to
1519 locally-defined, preemptible global symbols as short-range "b.n"
1520 branch instructions.
1522 This is a problem, because there's no guarantee the final
1523 destination of the symbol, or any candidate locations for a
1524 trampoline, are within range of the branch. For this reason, the
1525 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1526 relocation in modules at all, and it makes little sense to add
1529 The symptom is that the kernel fails with an "unsupported
1530 relocation" error when loading some modules.
1532 Until fixed tools are available, passing
1533 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1534 code which hits this problem, at the cost of a bit of extra runtime
1535 stack usage in some cases.
1537 The problem is described in more detail at:
1538 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1540 Only Thumb-2 kernels are affected.
1542 Unless you are sure your tools don't have this problem, say Y.
1544 config ARM_ASM_UNIFIED
1547 config ARM_PATCH_IDIV
1548 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1549 depends on CPU_32v7 && !XIP_KERNEL
1552 The ARM compiler inserts calls to __aeabi_idiv() and
1553 __aeabi_uidiv() when it needs to perform division on signed
1554 and unsigned integers. Some v7 CPUs have support for the sdiv
1555 and udiv instructions that can be used to implement those
1558 Enabling this option allows the kernel to modify itself to
1559 replace the first two instructions of these library functions
1560 with the sdiv or udiv plus "bx lr" instructions when the CPU
1561 it is running on supports them. Typically this will be faster
1562 and less power intensive than running the original library
1563 code to do integer division.
1566 bool "Use the ARM EABI to compile the kernel"
1568 This option allows for the kernel to be compiled using the latest
1569 ARM ABI (aka EABI). This is only useful if you are using a user
1570 space environment that is also compiled with EABI.
1572 Since there are major incompatibilities between the legacy ABI and
1573 EABI, especially with regard to structure member alignment, this
1574 option also changes the kernel syscall calling convention to
1575 disambiguate both ABIs and allow for backward compatibility support
1576 (selected with CONFIG_OABI_COMPAT).
1578 To use this you need GCC version 4.0.0 or later.
1581 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1582 depends on AEABI && !THUMB2_KERNEL
1584 This option preserves the old syscall interface along with the
1585 new (ARM EABI) one. It also provides a compatibility layer to
1586 intercept syscalls that have structure arguments which layout
1587 in memory differs between the legacy ABI and the new ARM EABI
1588 (only for non "thumb" binaries). This option adds a tiny
1589 overhead to all syscalls and produces a slightly larger kernel.
1591 The seccomp filter system will not be available when this is
1592 selected, since there is no way yet to sensibly distinguish
1593 between calling conventions during filtering.
1595 If you know you'll be using only pure EABI user space then you
1596 can say N here. If this option is not selected and you attempt
1597 to execute a legacy ABI binary then the result will be
1598 UNPREDICTABLE (in fact it can be predicted that it won't work
1599 at all). If in doubt say N.
1601 config ARCH_HAS_HOLES_MEMORYMODEL
1604 config ARCH_SPARSEMEM_ENABLE
1607 config ARCH_SPARSEMEM_DEFAULT
1608 def_bool ARCH_SPARSEMEM_ENABLE
1610 config ARCH_SELECT_MEMORY_MODEL
1611 def_bool ARCH_SPARSEMEM_ENABLE
1613 config HAVE_ARCH_PFN_VALID
1614 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1616 config HAVE_GENERIC_RCU_GUP
1621 bool "High Memory Support"
1624 The address space of ARM processors is only 4 Gigabytes large
1625 and it has to accommodate user address space, kernel address
1626 space as well as some memory mapped IO. That means that, if you
1627 have a large amount of physical memory and/or IO, not all of the
1628 memory can be "permanently mapped" by the kernel. The physical
1629 memory that is not permanently mapped is called "high memory".
1631 Depending on the selected kernel/user memory split, minimum
1632 vmalloc space and actual amount of RAM, you may not need this
1633 option which should result in a slightly faster kernel.
1638 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1642 The VM uses one page of physical memory for each page table.
1643 For systems with a lot of processes, this can use a lot of
1644 precious low memory, eventually leading to low memory being
1645 consumed by page tables. Setting this option will allow
1646 user-space 2nd level page tables to reside in high memory.
1648 config CPU_SW_DOMAIN_PAN
1649 bool "Enable use of CPU domains to implement privileged no-access"
1650 depends on MMU && !ARM_LPAE
1653 Increase kernel security by ensuring that normal kernel accesses
1654 are unable to access userspace addresses. This can help prevent
1655 use-after-free bugs becoming an exploitable privilege escalation
1656 by ensuring that magic values (such as LIST_POISON) will always
1657 fault when dereferenced.
1659 CPUs with low-vector mappings use a best-efforts implementation.
1660 Their lower 1MB needs to remain accessible for the vectors, but
1661 the remainder of userspace will become appropriately inaccessible.
1663 config HW_PERF_EVENTS
1667 config SYS_SUPPORTS_HUGETLBFS
1671 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1675 config ARCH_WANT_GENERAL_HUGETLB
1678 config ARM_MODULE_PLTS
1679 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1682 Allocate PLTs when loading modules so that jumps and calls whose
1683 targets are too far away for their relative offsets to be encoded
1684 in the instructions themselves can be bounced via veneers in the
1685 module's PLT. This allows modules to be allocated in the generic
1686 vmalloc area after the dedicated module memory area has been
1687 exhausted. The modules will use slightly more memory, but after
1688 rounding up to page size, the actual memory footprint is usually
1691 Say y if you are getting out of memory errors while loading modules
1695 config FORCE_MAX_ZONEORDER
1696 int "Maximum zone order"
1697 default "12" if SOC_AM33XX
1698 default "9" if SA1111 || ARCH_EFM32
1701 The kernel memory allocator divides physically contiguous memory
1702 blocks into "zones", where each zone is a power of two number of
1703 pages. This option selects the largest power of two that the kernel
1704 keeps in the memory allocator. If you need to allocate very large
1705 blocks of physically contiguous memory, then you may need to
1706 increase this value.
1708 This config option is actually maximum order plus one. For example,
1709 a value of 11 means that the largest free memory block is 2^10 pages.
1711 config ALIGNMENT_TRAP
1713 depends on CPU_CP15_MMU
1714 default y if !ARCH_EBSA110
1715 select HAVE_PROC_CPU if PROC_FS
1717 ARM processors cannot fetch/store information which is not
1718 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1719 address divisible by 4. On 32-bit ARM processors, these non-aligned
1720 fetch/store instructions will be emulated in software if you say
1721 here, which has a severe performance impact. This is necessary for
1722 correct operation of some network protocols. With an IP-only
1723 configuration it is safe to say N, otherwise say Y.
1725 config UACCESS_WITH_MEMCPY
1726 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1728 default y if CPU_FEROCEON
1730 Implement faster copy_to_user and clear_user methods for CPU
1731 cores where a 8-word STM instruction give significantly higher
1732 memory write throughput than a sequence of individual 32bit stores.
1734 A possible side effect is a slight increase in scheduling latency
1735 between threads sharing the same address space if they invoke
1736 such copy operations with large buffers.
1738 However, if the CPU data cache is using a write-allocate mode,
1739 this option is unlikely to provide any performance gain.
1743 prompt "Enable seccomp to safely compute untrusted bytecode"
1745 This kernel feature is useful for number crunching applications
1746 that may need to compute untrusted bytecode during their
1747 execution. By using pipes or other transports made available to
1748 the process as file descriptors supporting the read/write
1749 syscalls, it's possible to isolate those applications in
1750 their own address space using seccomp. Once seccomp is
1751 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1752 and the task is only allowed to execute a few safe syscalls
1753 defined by each seccomp mode.
1762 bool "Enable paravirtualization code"
1764 This changes the kernel so it can modify itself when it is run
1765 under a hypervisor, potentially improving performance significantly
1766 over full virtualization.
1768 config PARAVIRT_TIME_ACCOUNTING
1769 bool "Paravirtual steal time accounting"
1773 Select this option to enable fine granularity task steal time
1774 accounting. Time spent executing other tasks in parallel with
1775 the current vCPU is discounted from the vCPU power. To account for
1776 that, there can be a small performance impact.
1778 If in doubt, say N here.
1785 bool "Xen guest support on ARM"
1786 depends on ARM && AEABI && OF
1787 depends on CPU_V7 && !CPU_V6
1788 depends on !GENERIC_ATOMIC64
1790 select ARCH_DMA_ADDR_T_64BIT
1795 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1802 bool "Flattened Device Tree support"
1806 Include support for flattened device tree machine descriptions.
1809 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1812 This is the traditional way of passing data to the kernel at boot
1813 time. If you are solely relying on the flattened device tree (or
1814 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1815 to remove ATAGS support from your kernel binary. If unsure,
1818 config DEPRECATED_PARAM_STRUCT
1819 bool "Provide old way to pass kernel parameters"
1822 This was deprecated in 2001 and announced to live on for 5 years.
1823 Some old boot loaders still use this way.
1825 # Compressed boot loader in ROM. Yes, we really want to ask about
1826 # TEXT and BSS so we preserve their values in the config files.
1827 config ZBOOT_ROM_TEXT
1828 hex "Compressed ROM boot loader base address"
1831 The physical address at which the ROM-able zImage is to be
1832 placed in the target. Platforms which normally make use of
1833 ROM-able zImage formats normally set this to a suitable
1834 value in their defconfig file.
1836 If ZBOOT_ROM is not enabled, this has no effect.
1838 config ZBOOT_ROM_BSS
1839 hex "Compressed ROM boot loader BSS address"
1842 The base address of an area of read/write memory in the target
1843 for the ROM-able zImage which must be available while the
1844 decompressor is running. It must be large enough to hold the
1845 entire decompressed kernel plus an additional 128 KiB.
1846 Platforms which normally make use of ROM-able zImage formats
1847 normally set this to a suitable value in their defconfig file.
1849 If ZBOOT_ROM is not enabled, this has no effect.
1852 bool "Compressed boot loader in ROM/flash"
1853 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1854 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1856 Say Y here if you intend to execute your compressed kernel image
1857 (zImage) directly from ROM or flash. If unsure, say N.
1859 config ARM_APPENDED_DTB
1860 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1863 With this option, the boot code will look for a device tree binary
1864 (DTB) appended to zImage
1865 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1867 This is meant as a backward compatibility convenience for those
1868 systems with a bootloader that can't be upgraded to accommodate
1869 the documented boot protocol using a device tree.
1871 Beware that there is very little in terms of protection against
1872 this option being confused by leftover garbage in memory that might
1873 look like a DTB header after a reboot if no actual DTB is appended
1874 to zImage. Do not leave this option active in a production kernel
1875 if you don't intend to always append a DTB. Proper passing of the
1876 location into r2 of a bootloader provided DTB is always preferable
1879 config ARM_ATAG_DTB_COMPAT
1880 bool "Supplement the appended DTB with traditional ATAG information"
1881 depends on ARM_APPENDED_DTB
1883 Some old bootloaders can't be updated to a DTB capable one, yet
1884 they provide ATAGs with memory configuration, the ramdisk address,
1885 the kernel cmdline string, etc. Such information is dynamically
1886 provided by the bootloader and can't always be stored in a static
1887 DTB. To allow a device tree enabled kernel to be used with such
1888 bootloaders, this option allows zImage to extract the information
1889 from the ATAG list and store it at run time into the appended DTB.
1892 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1893 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1895 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1896 bool "Use bootloader kernel arguments if available"
1898 Uses the command-line options passed by the boot loader instead of
1899 the device tree bootargs property. If the boot loader doesn't provide
1900 any, the device tree bootargs property will be used.
1902 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1903 bool "Extend with bootloader kernel arguments"
1905 The command-line arguments provided by the boot loader will be
1906 appended to the the device tree bootargs property.
1911 string "Default kernel command string"
1914 On some architectures (EBSA110 and CATS), there is currently no way
1915 for the boot loader to pass arguments to the kernel. For these
1916 architectures, you should supply some command-line options at build
1917 time by entering them here. As a minimum, you should specify the
1918 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1921 prompt "Kernel command line type" if CMDLINE != ""
1922 default CMDLINE_FROM_BOOTLOADER
1925 config CMDLINE_FROM_BOOTLOADER
1926 bool "Use bootloader kernel arguments if available"
1928 Uses the command-line options passed by the boot loader. If
1929 the boot loader doesn't provide any, the default kernel command
1930 string provided in CMDLINE will be used.
1932 config CMDLINE_EXTEND
1933 bool "Extend bootloader kernel arguments"
1935 The command-line arguments provided by the boot loader will be
1936 appended to the default kernel command string.
1938 config CMDLINE_FORCE
1939 bool "Always use the default kernel command string"
1941 Always use the default kernel command string, even if the boot
1942 loader passes other arguments to the kernel.
1943 This is useful if you cannot or don't want to change the
1944 command-line options your boot loader passes to the kernel.
1948 bool "Kernel Execute-In-Place from ROM"
1949 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1951 Execute-In-Place allows the kernel to run from non-volatile storage
1952 directly addressable by the CPU, such as NOR flash. This saves RAM
1953 space since the text section of the kernel is not loaded from flash
1954 to RAM. Read-write sections, such as the data section and stack,
1955 are still copied to RAM. The XIP kernel is not compressed since
1956 it has to run directly from flash, so it will take more space to
1957 store it. The flash address used to link the kernel object files,
1958 and for storing it, is configuration dependent. Therefore, if you
1959 say Y here, you must know the proper physical address where to
1960 store the kernel image depending on your own flash memory usage.
1962 Also note that the make target becomes "make xipImage" rather than
1963 "make zImage" or "make Image". The final kernel binary to put in
1964 ROM memory will be arch/arm/boot/xipImage.
1968 config XIP_PHYS_ADDR
1969 hex "XIP Kernel Physical Location"
1970 depends on XIP_KERNEL
1971 default "0x00080000"
1973 This is the physical address in your flash memory the kernel will
1974 be linked for and stored to. This address is dependent on your
1978 bool "Kexec system call (EXPERIMENTAL)"
1979 depends on (!SMP || PM_SLEEP_SMP)
1983 kexec is a system call that implements the ability to shutdown your
1984 current kernel, and to start another kernel. It is like a reboot
1985 but it is independent of the system firmware. And like a reboot
1986 you can start any kernel with it, not just Linux.
1988 It is an ongoing process to be certain the hardware in a machine
1989 is properly shutdown, so do not be surprised if this code does not
1990 initially work for you.
1993 bool "Export atags in procfs"
1994 depends on ATAGS && KEXEC
1997 Should the atags used to boot the kernel be exported in an "atags"
1998 file in procfs. Useful with kexec.
2001 bool "Build kdump crash kernel (EXPERIMENTAL)"
2003 Generate crash dump after being started by kexec. This should
2004 be normally only set in special crash dump kernels which are
2005 loaded in the main kernel with kexec-tools into a specially
2006 reserved region and then later executed after a crash by
2007 kdump/kexec. The crash dump kernel must be compiled to a
2008 memory address not used by the main kernel
2010 For more details see Documentation/kdump/kdump.txt
2012 config AUTO_ZRELADDR
2013 bool "Auto calculation of the decompressed kernel image address"
2015 ZRELADDR is the physical address where the decompressed kernel
2016 image will be placed. If AUTO_ZRELADDR is selected, the address
2017 will be determined at run-time by masking the current IP with
2018 0xf8000000. This assumes the zImage being placed in the first 128MB
2019 from start of memory.
2025 bool "UEFI runtime support"
2026 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2028 select EFI_PARAMS_FROM_FDT
2031 select EFI_RUNTIME_WRAPPERS
2033 This option provides support for runtime services provided
2034 by UEFI firmware (such as non-volatile variables, realtime
2035 clock, and platform reset). A UEFI stub is also provided to
2036 allow the kernel to be booted as an EFI application. This
2037 is only useful for kernels that may run on systems that have
2042 menu "CPU Power Management"
2044 source "drivers/cpufreq/Kconfig"
2046 source "drivers/cpuidle/Kconfig"
2050 menu "Floating point emulation"
2052 comment "At least one emulation must be selected"
2055 bool "NWFPE math emulation"
2056 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2058 Say Y to include the NWFPE floating point emulator in the kernel.
2059 This is necessary to run most binaries. Linux does not currently
2060 support floating point hardware so you need to say Y here even if
2061 your machine has an FPA or floating point co-processor podule.
2063 You may say N here if you are going to load the Acorn FPEmulator
2064 early in the bootup.
2067 bool "Support extended precision"
2068 depends on FPE_NWFPE
2070 Say Y to include 80-bit support in the kernel floating-point
2071 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2072 Note that gcc does not generate 80-bit operations by default,
2073 so in most cases this option only enlarges the size of the
2074 floating point emulator without any good reason.
2076 You almost surely want to say N here.
2079 bool "FastFPE math emulation (EXPERIMENTAL)"
2080 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2082 Say Y here to include the FAST floating point emulator in the kernel.
2083 This is an experimental much faster emulator which now also has full
2084 precision for the mantissa. It does not support any exceptions.
2085 It is very simple, and approximately 3-6 times faster than NWFPE.
2087 It should be sufficient for most programs. It may be not suitable
2088 for scientific calculations, but you have to check this for yourself.
2089 If you do not feel you need a faster FP emulation you should better
2093 bool "VFP-format floating point maths"
2094 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2096 Say Y to include VFP support code in the kernel. This is needed
2097 if your hardware includes a VFP unit.
2099 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2100 release notes and additional status information.
2102 Say N if your target does not have VFP hardware.
2110 bool "Advanced SIMD (NEON) Extension support"
2111 depends on VFPv3 && CPU_V7
2113 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2116 config KERNEL_MODE_NEON
2117 bool "Support for NEON in kernel mode"
2118 depends on NEON && AEABI
2120 Say Y to include support for NEON in kernel mode.
2124 menu "Userspace binary formats"
2126 source "fs/Kconfig.binfmt"
2130 menu "Power management options"
2132 source "kernel/power/Kconfig"
2134 config ARCH_SUSPEND_POSSIBLE
2135 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2136 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2139 config ARM_CPU_SUSPEND
2140 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2141 depends on ARCH_SUSPEND_POSSIBLE
2143 config ARCH_HIBERNATION_POSSIBLE
2146 default y if ARCH_SUSPEND_POSSIBLE
2150 source "net/Kconfig"
2152 source "drivers/Kconfig"
2154 source "drivers/firmware/Kconfig"
2158 source "arch/arm/Kconfig.debug"
2160 source "security/Kconfig"
2162 source "crypto/Kconfig"
2164 source "arch/arm/crypto/Kconfig"
2167 source "lib/Kconfig"
2169 source "arch/arm/kvm/Kconfig"