4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
228 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 The base address of exception vectors. This must be two pages
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
238 depends on !ARCH_REALVIEW || !SPARSEMEM
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_GPIO_H
254 Select this when mach/gpio.h is required to provide special
255 definitions for this platform. The need for mach/gpio.h should
256 be avoided when possible.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
275 default DRAM_BASE if !MMU
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARM_PATCH_PHYS_VIRT
312 select MULTI_IRQ_HANDLER
316 config ARCH_INTEGRATOR
317 bool "ARM Ltd. Integrator family"
318 select ARCH_HAS_CPUFREQ
320 select ARM_PATCH_PHYS_VIRT
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
327 select MULTI_IRQ_HANDLER
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
332 select VERSATILE_FPGA_IRQ
334 Support for ARM's Integrator platform.
337 bool "ARM Ltd. RealView family"
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_TIMER_SP804
342 select COMMON_CLK_VERSATILE
343 select GENERIC_CLOCKEVENTS
344 select GPIO_PL061 if GPIOLIB
346 select NEED_MACH_MEMORY_H
347 select PLAT_VERSATILE
348 select PLAT_VERSATILE_CLCD
350 This enables support for ARM Ltd RealView boards.
352 config ARCH_VERSATILE
353 bool "ARM Ltd. Versatile family"
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select HAVE_MACH_CLKDEV
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_CLCD
364 select PLAT_VERSATILE_CLOCK
365 select VERSATILE_FPGA_IRQ
367 This enables support for ARM Ltd Versatile board.
371 select ARCH_REQUIRE_GPIOLIB
374 select NEED_MACH_GPIO_H
375 select NEED_MACH_IO_H if PCCARD
377 select PINCTRL_AT91 if USE_OF
379 This enables support for systems based on Atmel
380 AT91RM9200 and AT91SAM9* processors.
383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
384 select ARCH_REQUIRE_GPIOLIB
389 select GENERIC_CLOCKEVENTS
391 select MULTI_IRQ_HANDLER
394 Support for Cirrus Logic 711x/721x/731x based boards.
397 bool "Cortina Systems Gemini"
398 select ARCH_REQUIRE_GPIOLIB
401 select GENERIC_CLOCKEVENTS
403 Support for the Cortina Systems Gemini family SoCs
407 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_IO_H
411 select NEED_MACH_MEMORY_H
414 This is an evaluation board for the StrongARM processor available
415 from Digital. It has limited hardware on-board, including an
416 Ethernet interface, two PCMCIA sockets, two serial ports and a
420 bool "Energy Micro efm32"
422 select ARCH_REQUIRE_GPIOLIB
425 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
426 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
431 select GENERIC_CLOCKEVENTS
437 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
484 Support for Intel's IOP13XX (XScale) family of processors.
489 select ARCH_REQUIRE_GPIOLIB
492 select NEED_RET_TO_USER
496 Support for Intel's 80219 and IOP32X (XScale) family of
502 select ARCH_REQUIRE_GPIOLIB
505 select NEED_RET_TO_USER
509 Support for Intel's IOP33X (XScale) family of processors.
514 select ARCH_HAS_DMA_SET_COHERENT_MASK
515 select ARCH_SUPPORTS_BIG_ENDIAN
516 select ARCH_REQUIRE_GPIOLIB
519 select DMABOUNCE if PCI
520 select GENERIC_CLOCKEVENTS
521 select MIGHT_HAVE_PCI
522 select NEED_MACH_IO_H
523 select USB_EHCI_BIG_ENDIAN_DESC
524 select USB_EHCI_BIG_ENDIAN_MMIO
526 Support for Intel's IXP4XX (XScale) family of processors.
530 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
537 select PLAT_ORION_LEGACY
538 select USB_ARCH_HAS_EHCI
540 Support for the Marvell Dove SoC 88AP510
543 bool "Marvell Kirkwood"
544 select ARCH_HAS_CPUFREQ
545 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 select PLAT_ORION_LEGACY
567 Support for the following Marvell MV78xx0 series SoCs:
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select MULTI_IRQ_HANDLER
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
637 select USB_ARCH_HAS_OHCI
640 Support for the NXP LPC32XX family of processors
643 bool "PXA2xx/PXA3xx-based"
645 select ARCH_HAS_CPUFREQ
647 select ARCH_REQUIRE_GPIOLIB
648 select ARM_CPU_SUSPEND if PM
652 select GENERIC_CLOCKEVENTS
655 select MULTI_IRQ_HANDLER
659 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
664 select ARCH_REQUIRE_GPIOLIB
666 select GENERIC_CLOCKEVENTS
668 Support for Qualcomm MSM/QSD based systems. This runs on the
669 apps processor of the MSM/QSD and depends on a shared memory
670 interface to the modem processor which runs the baseband
671 stack and controls some vital subsystems
672 (clock and power control, etc).
674 config ARCH_SHMOBILE_LEGACY
675 bool "Renesas ARM SoCs (non-multiplatform)"
677 select ARM_PATCH_PHYS_VIRT
679 select GENERIC_CLOCKEVENTS
680 select HAVE_ARM_SCU if SMP
681 select HAVE_ARM_TWD if SMP
682 select HAVE_MACH_CLKDEV
684 select MIGHT_HAVE_CACHE_L2X0
685 select MULTI_IRQ_HANDLER
688 select PM_GENERIC_DOMAINS if PM
691 Support for Renesas ARM SoC platforms using a non-multiplatform
692 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
698 select ARCH_MAY_HAVE_PC_FDC
699 select ARCH_SPARSEMEM_ENABLE
700 select ARCH_USES_GETTIMEOFFSET
704 select HAVE_PATA_PLATFORM
706 select NEED_MACH_IO_H
707 select NEED_MACH_MEMORY_H
711 On the Acorn Risc-PC, Linux can support the internal IDE disk and
712 CD-ROM interface, serial and parallel port, and the floppy drive.
716 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
719 select ARCH_SPARSEMEM_ENABLE
724 select GENERIC_CLOCKEVENTS
727 select NEED_MACH_MEMORY_H
730 Support for StrongARM 11x0 based boards.
733 bool "Samsung S3C24XX SoCs"
734 select ARCH_HAS_CPUFREQ
735 select ARCH_REQUIRE_GPIOLIB
737 select CLKSRC_SAMSUNG_PWM
738 select GENERIC_CLOCKEVENTS
740 select HAVE_S3C2410_I2C if I2C
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 select HAVE_S3C_RTC if RTC_CLASS
743 select MULTI_IRQ_HANDLER
744 select NEED_MACH_IO_H
747 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
748 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
749 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
750 Samsung SMDK2410 development board (and derivatives).
753 bool "Samsung S3C64XX"
754 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
759 select CLKSRC_SAMSUNG_PWM
762 select GENERIC_CLOCKEVENTS
764 select HAVE_S3C2410_I2C if I2C
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
769 select PM_GENERIC_DOMAINS if PM
771 select S3C_GPIO_TRACK
773 select SAMSUNG_WAKEMASK
774 select SAMSUNG_WDT_RESET
775 select USB_ARCH_HAS_OHCI
777 Samsung S3C64XX series based systems
780 bool "Samsung S5P6440 S5P6450"
782 select CLKSRC_SAMSUNG_PWM
784 select GENERIC_CLOCKEVENTS
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 select HAVE_S3C_RTC if RTC_CLASS
789 select NEED_MACH_GPIO_H
791 select SAMSUNG_WDT_RESET
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
797 bool "Samsung S5PC100"
798 select ARCH_REQUIRE_GPIOLIB
800 select CLKSRC_SAMSUNG_PWM
802 select GENERIC_CLOCKEVENTS
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
809 select SAMSUNG_WDT_RESET
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
819 select CLKSRC_SAMSUNG_PWM
821 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select HAVE_S3C_RTC if RTC_CLASS
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
837 select ARCH_SPARSEMEM_ENABLE
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
856 select GENERIC_ALLOCATOR
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
864 Support for TI's DaVinci platform.
869 select ARCH_HAS_CPUFREQ
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_REQUIRE_GPIOLIB
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_IRQ_CHIP
879 select NEED_MACH_IO_H if PCCARD
880 select NEED_MACH_MEMORY_H
882 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
886 menu "Multiple platform selection"
887 depends on ARCH_MULTIPLATFORM
889 comment "CPU Core family selection"
891 config ARCH_MULTI_V4T
892 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
895 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
896 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
897 CPU_ARM925T || CPU_ARM940T)
900 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
901 depends on !ARCH_MULTI_V6_V7
902 select ARCH_MULTI_V4_V5
903 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
904 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
905 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
907 config ARCH_MULTI_V4_V5
911 bool "ARMv6 based platforms (ARM11)"
912 select ARCH_MULTI_V6_V7
916 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
918 select ARCH_MULTI_V6_V7
921 config ARCH_MULTI_V6_V7
924 config ARCH_MULTI_CPU_AUTO
925 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
931 # This is sorted alphabetically by mach-* pathname. However, plat-*
932 # Kconfigs may be included either alphabetically (according to the
933 # plat- suffix) or along side the corresponding mach-* source.
935 source "arch/arm/mach-mvebu/Kconfig"
937 source "arch/arm/mach-at91/Kconfig"
939 source "arch/arm/mach-bcm/Kconfig"
941 source "arch/arm/mach-bcm2835/Kconfig"
943 source "arch/arm/mach-berlin/Kconfig"
945 source "arch/arm/mach-clps711x/Kconfig"
947 source "arch/arm/mach-cns3xxx/Kconfig"
949 source "arch/arm/mach-davinci/Kconfig"
951 source "arch/arm/mach-dove/Kconfig"
953 source "arch/arm/mach-ep93xx/Kconfig"
955 source "arch/arm/mach-footbridge/Kconfig"
957 source "arch/arm/mach-gemini/Kconfig"
959 source "arch/arm/mach-highbank/Kconfig"
961 source "arch/arm/mach-hisi/Kconfig"
963 source "arch/arm/mach-integrator/Kconfig"
965 source "arch/arm/mach-iop32x/Kconfig"
967 source "arch/arm/mach-iop33x/Kconfig"
969 source "arch/arm/mach-iop13xx/Kconfig"
971 source "arch/arm/mach-ixp4xx/Kconfig"
973 source "arch/arm/mach-keystone/Kconfig"
975 source "arch/arm/mach-kirkwood/Kconfig"
977 source "arch/arm/mach-ks8695/Kconfig"
979 source "arch/arm/mach-msm/Kconfig"
981 source "arch/arm/mach-moxart/Kconfig"
983 source "arch/arm/mach-mv78xx0/Kconfig"
985 source "arch/arm/mach-imx/Kconfig"
987 source "arch/arm/mach-mxs/Kconfig"
989 source "arch/arm/mach-netx/Kconfig"
991 source "arch/arm/mach-nomadik/Kconfig"
993 source "arch/arm/mach-nspire/Kconfig"
995 source "arch/arm/plat-omap/Kconfig"
997 source "arch/arm/mach-omap1/Kconfig"
999 source "arch/arm/mach-omap2/Kconfig"
1001 source "arch/arm/mach-orion5x/Kconfig"
1003 source "arch/arm/mach-picoxcell/Kconfig"
1005 source "arch/arm/mach-pxa/Kconfig"
1006 source "arch/arm/plat-pxa/Kconfig"
1008 source "arch/arm/mach-mmp/Kconfig"
1010 source "arch/arm/mach-realview/Kconfig"
1012 source "arch/arm/mach-rockchip/Kconfig"
1014 source "arch/arm/mach-sa1100/Kconfig"
1016 source "arch/arm/plat-samsung/Kconfig"
1018 source "arch/arm/mach-socfpga/Kconfig"
1020 source "arch/arm/mach-spear/Kconfig"
1022 source "arch/arm/mach-sti/Kconfig"
1024 source "arch/arm/mach-s3c24xx/Kconfig"
1026 source "arch/arm/mach-s3c64xx/Kconfig"
1028 source "arch/arm/mach-s5p64x0/Kconfig"
1030 source "arch/arm/mach-s5pc100/Kconfig"
1032 source "arch/arm/mach-s5pv210/Kconfig"
1034 source "arch/arm/mach-exynos/Kconfig"
1036 source "arch/arm/mach-shmobile/Kconfig"
1038 source "arch/arm/mach-sunxi/Kconfig"
1040 source "arch/arm/mach-prima2/Kconfig"
1042 source "arch/arm/mach-tegra/Kconfig"
1044 source "arch/arm/mach-u300/Kconfig"
1046 source "arch/arm/mach-ux500/Kconfig"
1048 source "arch/arm/mach-versatile/Kconfig"
1050 source "arch/arm/mach-vexpress/Kconfig"
1051 source "arch/arm/plat-versatile/Kconfig"
1053 source "arch/arm/mach-virt/Kconfig"
1055 source "arch/arm/mach-vt8500/Kconfig"
1057 source "arch/arm/mach-w90x900/Kconfig"
1059 source "arch/arm/mach-zynq/Kconfig"
1061 # Definitions to make life easier
1067 select GENERIC_CLOCKEVENTS
1073 select GENERIC_IRQ_CHIP
1076 config PLAT_ORION_LEGACY
1083 config PLAT_VERSATILE
1086 config ARM_TIMER_SP804
1089 select CLKSRC_OF if OF
1091 source "arch/arm/firmware/Kconfig"
1093 source arch/arm/mm/Kconfig
1097 default 16 if ARCH_EP93XX
1101 bool "Enable iWMMXt support" if !CPU_PJ4
1102 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1103 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1105 Enable support for iWMMXt context switching at run time if
1106 running on a CPU that supports it.
1108 config MULTI_IRQ_HANDLER
1111 Allow each machine to specify it's own IRQ handler at run time.
1114 source "arch/arm/Kconfig-nommu"
1117 config PJ4B_ERRATA_4742
1118 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1119 depends on CPU_PJ4B && MACH_ARMADA_370
1122 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1123 Event (WFE) IDLE states, a specific timing sensitivity exists between
1124 the retiring WFI/WFE instructions and the newly issued subsequent
1125 instructions. This sensitivity can result in a CPU hang scenario.
1127 The software must insert either a Data Synchronization Barrier (DSB)
1128 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1131 config ARM_ERRATA_326103
1132 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1135 Executing a SWP instruction to read-only memory does not set bit 11
1136 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1137 treat the access as a read, preventing a COW from occurring and
1138 causing the faulting task to livelock.
1140 config ARM_ERRATA_411920
1141 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1142 depends on CPU_V6 || CPU_V6K
1144 Invalidation of the Instruction Cache operation can
1145 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1146 It does not affect the MPCore. This option enables the ARM Ltd.
1147 recommended workaround.
1149 config ARM_ERRATA_430973
1150 bool "ARM errata: Stale prediction on replaced interworking branch"
1153 This option enables the workaround for the 430973 Cortex-A8
1154 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1155 interworking branch is replaced with another code sequence at the
1156 same virtual address, whether due to self-modifying code or virtual
1157 to physical address re-mapping, Cortex-A8 does not recover from the
1158 stale interworking branch prediction. This results in Cortex-A8
1159 executing the new code sequence in the incorrect ARM or Thumb state.
1160 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1161 and also flushes the branch target cache at every context switch.
1162 Note that setting specific bits in the ACTLR register may not be
1163 available in non-secure mode.
1165 config ARM_ERRATA_458693
1166 bool "ARM errata: Processor deadlock when a false hazard is created"
1168 depends on !ARCH_MULTIPLATFORM
1170 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1171 erratum. For very specific sequences of memory operations, it is
1172 possible for a hazard condition intended for a cache line to instead
1173 be incorrectly associated with a different cache line. This false
1174 hazard might then cause a processor deadlock. The workaround enables
1175 the L1 caching of the NEON accesses and disables the PLD instruction
1176 in the ACTLR register. Note that setting specific bits in the ACTLR
1177 register may not be available in non-secure mode.
1179 config ARM_ERRATA_460075
1180 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1185 erratum. Any asynchronous access to the L2 cache may encounter a
1186 situation in which recent store transactions to the L2 cache are lost
1187 and overwritten with stale memory contents from external memory. The
1188 workaround disables the write-allocate mode for the L2 cache via the
1189 ACTLR register. Note that setting specific bits in the ACTLR register
1190 may not be available in non-secure mode.
1192 config ARM_ERRATA_742230
1193 bool "ARM errata: DMB operation may be faulty"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 742230 Cortex-A9
1198 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1199 between two write operations may not ensure the correct visibility
1200 ordering of the two writes. This workaround sets a specific bit in
1201 the diagnostic register of the Cortex-A9 which causes the DMB
1202 instruction to behave as a DSB, ensuring the correct behaviour of
1205 config ARM_ERRATA_742231
1206 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1207 depends on CPU_V7 && SMP
1208 depends on !ARCH_MULTIPLATFORM
1210 This option enables the workaround for the 742231 Cortex-A9
1211 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1212 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1213 accessing some data located in the same cache line, may get corrupted
1214 data due to bad handling of the address hazard when the line gets
1215 replaced from one of the CPUs at the same time as another CPU is
1216 accessing it. This workaround sets specific bits in the diagnostic
1217 register of the Cortex-A9 which reduces the linefill issuing
1218 capabilities of the processor.
1220 config PL310_ERRATA_588369
1221 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1222 depends on CACHE_L2X0
1224 The PL310 L2 cache controller implements three types of Clean &
1225 Invalidate maintenance operations: by Physical Address
1226 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1227 They are architecturally defined to behave as the execution of a
1228 clean operation followed immediately by an invalidate operation,
1229 both performing to the same memory location. This functionality
1230 is not correctly implemented in PL310 as clean lines are not
1231 invalidated as a result of these operations.
1233 config ARM_ERRATA_643719
1234 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 643719 Cortex-A9 (prior to
1238 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1239 register returns zero when it should return one. The workaround
1240 corrects this value, ensuring cache maintenance operations which use
1241 it behave as intended and avoiding data corruption.
1243 config ARM_ERRATA_720789
1244 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1247 This option enables the workaround for the 720789 Cortex-A9 (prior to
1248 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1249 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1250 As a consequence of this erratum, some TLB entries which should be
1251 invalidated are not, resulting in an incoherency in the system page
1252 tables. The workaround changes the TLB flushing routines to invalidate
1253 entries regardless of the ASID.
1255 config PL310_ERRATA_727915
1256 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1257 depends on CACHE_L2X0
1259 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1260 operation (offset 0x7FC). This operation runs in background so that
1261 PL310 can handle normal accesses while it is in progress. Under very
1262 rare circumstances, due to this erratum, write data can be lost when
1263 PL310 treats a cacheable write transaction during a Clean &
1264 Invalidate by Way operation.
1266 config ARM_ERRATA_743622
1267 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1269 depends on !ARCH_MULTIPLATFORM
1271 This option enables the workaround for the 743622 Cortex-A9
1272 (r2p*) erratum. Under very rare conditions, a faulty
1273 optimisation in the Cortex-A9 Store Buffer may lead to data
1274 corruption. This workaround sets a specific bit in the diagnostic
1275 register of the Cortex-A9 which disables the Store Buffer
1276 optimisation, preventing the defect from occurring. This has no
1277 visible impact on the overall performance or power consumption of the
1280 config ARM_ERRATA_751472
1281 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1283 depends on !ARCH_MULTIPLATFORM
1285 This option enables the workaround for the 751472 Cortex-A9 (prior
1286 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1287 completion of a following broadcasted operation if the second
1288 operation is received by a CPU before the ICIALLUIS has completed,
1289 potentially leading to corrupted entries in the cache or TLB.
1291 config PL310_ERRATA_753970
1292 bool "PL310 errata: cache sync operation may be faulty"
1293 depends on CACHE_PL310
1295 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1297 Under some condition the effect of cache sync operation on
1298 the store buffer still remains when the operation completes.
1299 This means that the store buffer is always asked to drain and
1300 this prevents it from merging any further writes. The workaround
1301 is to replace the normal offset of cache sync operation (0x730)
1302 by another offset targeting an unmapped PL310 register 0x740.
1303 This has the same effect as the cache sync operation: store buffer
1304 drain and waiting for all buffers empty.
1306 config ARM_ERRATA_754322
1307 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1310 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1311 r3p*) erratum. A speculative memory access may cause a page table walk
1312 which starts prior to an ASID switch but completes afterwards. This
1313 can populate the micro-TLB with a stale entry which may be hit with
1314 the new ASID. This workaround places two dsb instructions in the mm
1315 switching code so that no page table walks can cross the ASID switch.
1317 config ARM_ERRATA_754327
1318 bool "ARM errata: no automatic Store Buffer drain"
1319 depends on CPU_V7 && SMP
1321 This option enables the workaround for the 754327 Cortex-A9 (prior to
1322 r2p0) erratum. The Store Buffer does not have any automatic draining
1323 mechanism and therefore a livelock may occur if an external agent
1324 continuously polls a memory location waiting to observe an update.
1325 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1326 written polling loops from denying visibility of updates to memory.
1328 config ARM_ERRATA_364296
1329 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1332 This options enables the workaround for the 364296 ARM1136
1333 r0p2 erratum (possible cache data corruption with
1334 hit-under-miss enabled). It sets the undocumented bit 31 in
1335 the auxiliary control register and the FI bit in the control
1336 register, thus disabling hit-under-miss without putting the
1337 processor into full low interrupt latency mode. ARM11MPCore
1340 config ARM_ERRATA_764369
1341 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1342 depends on CPU_V7 && SMP
1344 This option enables the workaround for erratum 764369
1345 affecting Cortex-A9 MPCore with two or more processors (all
1346 current revisions). Under certain timing circumstances, a data
1347 cache line maintenance operation by MVA targeting an Inner
1348 Shareable memory region may fail to proceed up to either the
1349 Point of Coherency or to the Point of Unification of the
1350 system. This workaround adds a DSB instruction before the
1351 relevant cache maintenance functions and sets a specific bit
1352 in the diagnostic control register of the SCU.
1354 config PL310_ERRATA_769419
1355 bool "PL310 errata: no automatic Store Buffer drain"
1356 depends on CACHE_L2X0
1358 On revisions of the PL310 prior to r3p2, the Store Buffer does
1359 not automatically drain. This can cause normal, non-cacheable
1360 writes to be retained when the memory system is idle, leading
1361 to suboptimal I/O performance for drivers using coherent DMA.
1362 This option adds a write barrier to the cpu_idle loop so that,
1363 on systems with an outer cache, the store buffer is drained
1366 config ARM_ERRATA_775420
1367 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1370 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1371 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1372 operation aborts with MMU exception, it might cause the processor
1373 to deadlock. This workaround puts DSB before executing ISB if
1374 an abort may occur on cache maintenance.
1376 config ARM_ERRATA_798181
1377 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1378 depends on CPU_V7 && SMP
1380 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1381 adequately shooting down all use of the old entries. This
1382 option enables the Linux kernel workaround for this erratum
1383 which sends an IPI to the CPUs that are running the same ASID
1384 as the one being invalidated.
1386 config ARM_ERRATA_773022
1387 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1390 This option enables the workaround for the 773022 Cortex-A15
1391 (up to r0p4) erratum. In certain rare sequences of code, the
1392 loop buffer may deliver incorrect instructions. This
1393 workaround disables the loop buffer to avoid the erratum.
1397 source "arch/arm/common/Kconfig"
1407 Find out whether you have ISA slots on your motherboard. ISA is the
1408 name of a bus system, i.e. the way the CPU talks to the other stuff
1409 inside your box. Other bus systems are PCI, EISA, MicroChannel
1410 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1411 newer boards don't support it. If you have ISA, say Y, otherwise N.
1413 # Select ISA DMA controller support
1418 # Select ISA DMA interface
1423 bool "PCI support" if MIGHT_HAVE_PCI
1425 Find out whether you have a PCI motherboard. PCI is the name of a
1426 bus system, i.e. the way the CPU talks to the other stuff inside
1427 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1428 VESA. If you have PCI, say Y, otherwise N.
1434 config PCI_NANOENGINE
1435 bool "BSE nanoEngine PCI support"
1436 depends on SA1100_NANOENGINE
1438 Enable PCI on the BSE nanoEngine board.
1443 config PCI_HOST_ITE8152
1445 depends on PCI && MACH_ARMCORE
1449 source "drivers/pci/Kconfig"
1450 source "drivers/pci/pcie/Kconfig"
1452 source "drivers/pcmcia/Kconfig"
1456 menu "Kernel Features"
1461 This option should be selected by machines which have an SMP-
1464 The only effect of this option is to make the SMP-related
1465 options available to the user for configuration.
1468 bool "Symmetric Multi-Processing"
1469 depends on CPU_V6K || CPU_V7
1470 depends on GENERIC_CLOCKEVENTS
1472 depends on MMU || ARM_MPU
1474 This enables support for systems with more than one CPU. If you have
1475 a system with only one CPU, say N. If you have a system with more
1476 than one CPU, say Y.
1478 If you say N here, the kernel will run on uni- and multiprocessor
1479 machines, but will use only one CPU of a multiprocessor machine. If
1480 you say Y here, the kernel will run on many, but not all,
1481 uniprocessor machines. On a uniprocessor machine, the kernel
1482 will run faster if you say N here.
1484 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1485 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1486 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1488 If you don't know what to do here, say N.
1491 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1492 depends on SMP && !XIP_KERNEL && MMU
1495 SMP kernels contain instructions which fail on non-SMP processors.
1496 Enabling this option allows the kernel to modify itself to make
1497 these instructions safe. Disabling it allows about 1K of space
1500 If you don't know what to do here, say Y.
1502 config ARM_CPU_TOPOLOGY
1503 bool "Support cpu topology definition"
1504 depends on SMP && CPU_V7
1507 Support ARM cpu topology definition. The MPIDR register defines
1508 affinity between processors which is then used to describe the cpu
1509 topology of an ARM System.
1512 bool "Multi-core scheduler support"
1513 depends on ARM_CPU_TOPOLOGY
1515 Multi-core scheduler support improves the CPU scheduler's decision
1516 making when dealing with multi-core CPU chips at a cost of slightly
1517 increased overhead in some places. If unsure say N here.
1520 bool "SMT scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1523 Improves the CPU scheduler's decision making when dealing with
1524 MultiThreading at a cost of slightly increased overhead in some
1525 places. If unsure say N here.
1530 This option enables support for the ARM system coherency unit
1532 config HAVE_ARM_ARCH_TIMER
1533 bool "Architected timer support"
1535 select ARM_ARCH_TIMER
1536 select GENERIC_CLOCKEVENTS
1538 This option enables support for the ARM architected timer
1543 select CLKSRC_OF if OF
1545 This options enables support for the ARM timer and watchdog unit
1548 bool "Multi-Cluster Power Management"
1549 depends on CPU_V7 && SMP
1551 This option provides the common power management infrastructure
1552 for (multi-)cluster based systems, such as big.LITTLE based
1556 bool "big.LITTLE support (Experimental)"
1557 depends on CPU_V7 && SMP
1560 This option enables support selections for the big.LITTLE
1561 system architecture.
1564 bool "big.LITTLE switcher support"
1565 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1567 select ARM_CPU_SUSPEND
1569 The big.LITTLE "switcher" provides the core functionality to
1570 transparently handle transition between a cluster of A15's
1571 and a cluster of A7's in a big.LITTLE system.
1573 config BL_SWITCHER_DUMMY_IF
1574 tristate "Simple big.LITTLE switcher user interface"
1575 depends on BL_SWITCHER && DEBUG_KERNEL
1577 This is a simple and dummy char dev interface to control
1578 the big.LITTLE switcher core code. It is meant for
1579 debugging purposes only.
1582 prompt "Memory split"
1585 Select the desired split between kernel and user memory.
1587 If you are not absolutely sure what you are doing, leave this
1591 bool "3G/1G user/kernel split"
1593 bool "2G/2G user/kernel split"
1595 bool "1G/3G user/kernel split"
1600 default 0x40000000 if VMSPLIT_1G
1601 default 0x80000000 if VMSPLIT_2G
1605 int "Maximum number of CPUs (2-32)"
1611 bool "Support for hot-pluggable CPUs"
1614 Say Y here to experiment with turning CPUs off and on. CPUs
1615 can be controlled through /sys/devices/system/cpu.
1618 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1621 Say Y here if you want Linux to communicate with system firmware
1622 implementing the PSCI specification for CPU-centric power
1623 management operations described in ARM document number ARM DEN
1624 0022A ("Power State Coordination Interface System Software on
1627 # The GPIO number here must be sorted by descending number. In case of
1628 # a multiplatform kernel, we just want the highest value required by the
1629 # selected platforms.
1632 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1633 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1634 default 392 if ARCH_U8500
1635 default 352 if ARCH_VT8500
1636 default 288 if ARCH_SUNXI
1637 default 264 if MACH_H4700
1640 Maximum number of GPIOs in the system.
1642 If unsure, leave the default value.
1644 source kernel/Kconfig.preempt
1648 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1649 ARCH_S5PV210 || ARCH_EXYNOS4
1650 default AT91_TIMER_HZ if ARCH_AT91
1651 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1655 depends on HZ_FIXED = 0
1656 prompt "Timer frequency"
1680 default HZ_FIXED if HZ_FIXED != 0
1681 default 100 if HZ_100
1682 default 200 if HZ_200
1683 default 250 if HZ_250
1684 default 300 if HZ_300
1685 default 500 if HZ_500
1689 def_bool HIGH_RES_TIMERS
1691 config THUMB2_KERNEL
1692 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1693 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1694 default y if CPU_THUMBONLY
1696 select ARM_ASM_UNIFIED
1699 By enabling this option, the kernel will be compiled in
1700 Thumb-2 mode. A compiler/assembler that understand the unified
1701 ARM-Thumb syntax is needed.
1705 config THUMB2_AVOID_R_ARM_THM_JUMP11
1706 bool "Work around buggy Thumb-2 short branch relocations in gas"
1707 depends on THUMB2_KERNEL && MODULES
1710 Various binutils versions can resolve Thumb-2 branches to
1711 locally-defined, preemptible global symbols as short-range "b.n"
1712 branch instructions.
1714 This is a problem, because there's no guarantee the final
1715 destination of the symbol, or any candidate locations for a
1716 trampoline, are within range of the branch. For this reason, the
1717 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1718 relocation in modules at all, and it makes little sense to add
1721 The symptom is that the kernel fails with an "unsupported
1722 relocation" error when loading some modules.
1724 Until fixed tools are available, passing
1725 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1726 code which hits this problem, at the cost of a bit of extra runtime
1727 stack usage in some cases.
1729 The problem is described in more detail at:
1730 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1732 Only Thumb-2 kernels are affected.
1734 Unless you are sure your tools don't have this problem, say Y.
1736 config ARM_ASM_UNIFIED
1740 bool "Use the ARM EABI to compile the kernel"
1742 This option allows for the kernel to be compiled using the latest
1743 ARM ABI (aka EABI). This is only useful if you are using a user
1744 space environment that is also compiled with EABI.
1746 Since there are major incompatibilities between the legacy ABI and
1747 EABI, especially with regard to structure member alignment, this
1748 option also changes the kernel syscall calling convention to
1749 disambiguate both ABIs and allow for backward compatibility support
1750 (selected with CONFIG_OABI_COMPAT).
1752 To use this you need GCC version 4.0.0 or later.
1755 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1756 depends on AEABI && !THUMB2_KERNEL
1758 This option preserves the old syscall interface along with the
1759 new (ARM EABI) one. It also provides a compatibility layer to
1760 intercept syscalls that have structure arguments which layout
1761 in memory differs between the legacy ABI and the new ARM EABI
1762 (only for non "thumb" binaries). This option adds a tiny
1763 overhead to all syscalls and produces a slightly larger kernel.
1765 The seccomp filter system will not be available when this is
1766 selected, since there is no way yet to sensibly distinguish
1767 between calling conventions during filtering.
1769 If you know you'll be using only pure EABI user space then you
1770 can say N here. If this option is not selected and you attempt
1771 to execute a legacy ABI binary then the result will be
1772 UNPREDICTABLE (in fact it can be predicted that it won't work
1773 at all). If in doubt say N.
1775 config ARCH_HAS_HOLES_MEMORYMODEL
1778 config ARCH_SPARSEMEM_ENABLE
1781 config ARCH_SPARSEMEM_DEFAULT
1782 def_bool ARCH_SPARSEMEM_ENABLE
1784 config ARCH_SELECT_MEMORY_MODEL
1785 def_bool ARCH_SPARSEMEM_ENABLE
1787 config HAVE_ARCH_PFN_VALID
1788 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1791 bool "High Memory Support"
1794 The address space of ARM processors is only 4 Gigabytes large
1795 and it has to accommodate user address space, kernel address
1796 space as well as some memory mapped IO. That means that, if you
1797 have a large amount of physical memory and/or IO, not all of the
1798 memory can be "permanently mapped" by the kernel. The physical
1799 memory that is not permanently mapped is called "high memory".
1801 Depending on the selected kernel/user memory split, minimum
1802 vmalloc space and actual amount of RAM, you may not need this
1803 option which should result in a slightly faster kernel.
1808 bool "Allocate 2nd-level pagetables from highmem"
1811 config HW_PERF_EVENTS
1812 bool "Enable hardware performance counter support for perf events"
1813 depends on PERF_EVENTS
1816 Enable hardware performance counter support for perf events. If
1817 disabled, perf events will use software events only.
1819 config SYS_SUPPORTS_HUGETLBFS
1823 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1827 config ARCH_WANT_GENERAL_HUGETLB
1832 config FORCE_MAX_ZONEORDER
1833 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1834 range 11 64 if ARCH_SHMOBILE_LEGACY
1835 default "12" if SOC_AM33XX
1836 default "9" if SA1111 || ARCH_EFM32
1839 The kernel memory allocator divides physically contiguous memory
1840 blocks into "zones", where each zone is a power of two number of
1841 pages. This option selects the largest power of two that the kernel
1842 keeps in the memory allocator. If you need to allocate very large
1843 blocks of physically contiguous memory, then you may need to
1844 increase this value.
1846 This config option is actually maximum order plus one. For example,
1847 a value of 11 means that the largest free memory block is 2^10 pages.
1849 config ALIGNMENT_TRAP
1851 depends on CPU_CP15_MMU
1852 default y if !ARCH_EBSA110
1853 select HAVE_PROC_CPU if PROC_FS
1855 ARM processors cannot fetch/store information which is not
1856 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1857 address divisible by 4. On 32-bit ARM processors, these non-aligned
1858 fetch/store instructions will be emulated in software if you say
1859 here, which has a severe performance impact. This is necessary for
1860 correct operation of some network protocols. With an IP-only
1861 configuration it is safe to say N, otherwise say Y.
1863 config UACCESS_WITH_MEMCPY
1864 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1866 default y if CPU_FEROCEON
1868 Implement faster copy_to_user and clear_user methods for CPU
1869 cores where a 8-word STM instruction give significantly higher
1870 memory write throughput than a sequence of individual 32bit stores.
1872 A possible side effect is a slight increase in scheduling latency
1873 between threads sharing the same address space if they invoke
1874 such copy operations with large buffers.
1876 However, if the CPU data cache is using a write-allocate mode,
1877 this option is unlikely to provide any performance gain.
1881 prompt "Enable seccomp to safely compute untrusted bytecode"
1883 This kernel feature is useful for number crunching applications
1884 that may need to compute untrusted bytecode during their
1885 execution. By using pipes or other transports made available to
1886 the process as file descriptors supporting the read/write
1887 syscalls, it's possible to isolate those applications in
1888 their own address space using seccomp. Once seccomp is
1889 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1890 and the task is only allowed to execute a few safe syscalls
1891 defined by each seccomp mode.
1904 bool "Xen guest support on ARM (EXPERIMENTAL)"
1905 depends on ARM && AEABI && OF
1906 depends on CPU_V7 && !CPU_V6
1907 depends on !GENERIC_ATOMIC64
1910 select ARCH_DMA_ADDR_T_64BIT
1912 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1919 bool "Flattened Device Tree support"
1922 select OF_EARLY_FLATTREE
1924 Include support for flattened device tree machine descriptions.
1927 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1930 This is the traditional way of passing data to the kernel at boot
1931 time. If you are solely relying on the flattened device tree (or
1932 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1933 to remove ATAGS support from your kernel binary. If unsure,
1936 config DEPRECATED_PARAM_STRUCT
1937 bool "Provide old way to pass kernel parameters"
1940 This was deprecated in 2001 and announced to live on for 5 years.
1941 Some old boot loaders still use this way.
1943 # Compressed boot loader in ROM. Yes, we really want to ask about
1944 # TEXT and BSS so we preserve their values in the config files.
1945 config ZBOOT_ROM_TEXT
1946 hex "Compressed ROM boot loader base address"
1949 The physical address at which the ROM-able zImage is to be
1950 placed in the target. Platforms which normally make use of
1951 ROM-able zImage formats normally set this to a suitable
1952 value in their defconfig file.
1954 If ZBOOT_ROM is not enabled, this has no effect.
1956 config ZBOOT_ROM_BSS
1957 hex "Compressed ROM boot loader BSS address"
1960 The base address of an area of read/write memory in the target
1961 for the ROM-able zImage which must be available while the
1962 decompressor is running. It must be large enough to hold the
1963 entire decompressed kernel plus an additional 128 KiB.
1964 Platforms which normally make use of ROM-able zImage formats
1965 normally set this to a suitable value in their defconfig file.
1967 If ZBOOT_ROM is not enabled, this has no effect.
1970 bool "Compressed boot loader in ROM/flash"
1971 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1972 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1974 Say Y here if you intend to execute your compressed kernel image
1975 (zImage) directly from ROM or flash. If unsure, say N.
1978 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1979 depends on ZBOOT_ROM && ARCH_SH7372
1980 default ZBOOT_ROM_NONE
1982 Include experimental SD/MMC loading code in the ROM-able zImage.
1983 With this enabled it is possible to write the ROM-able zImage
1984 kernel image to an MMC or SD card and boot the kernel straight
1985 from the reset vector. At reset the processor Mask ROM will load
1986 the first part of the ROM-able zImage which in turn loads the
1987 rest the kernel image to RAM.
1989 config ZBOOT_ROM_NONE
1990 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1992 Do not load image from SD or MMC
1994 config ZBOOT_ROM_MMCIF
1995 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1997 Load image from MMCIF hardware block.
1999 config ZBOOT_ROM_SH_MOBILE_SDHI
2000 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2002 Load image from SDHI hardware block
2006 config ARM_APPENDED_DTB
2007 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2010 With this option, the boot code will look for a device tree binary
2011 (DTB) appended to zImage
2012 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2014 This is meant as a backward compatibility convenience for those
2015 systems with a bootloader that can't be upgraded to accommodate
2016 the documented boot protocol using a device tree.
2018 Beware that there is very little in terms of protection against
2019 this option being confused by leftover garbage in memory that might
2020 look like a DTB header after a reboot if no actual DTB is appended
2021 to zImage. Do not leave this option active in a production kernel
2022 if you don't intend to always append a DTB. Proper passing of the
2023 location into r2 of a bootloader provided DTB is always preferable
2026 config ARM_ATAG_DTB_COMPAT
2027 bool "Supplement the appended DTB with traditional ATAG information"
2028 depends on ARM_APPENDED_DTB
2030 Some old bootloaders can't be updated to a DTB capable one, yet
2031 they provide ATAGs with memory configuration, the ramdisk address,
2032 the kernel cmdline string, etc. Such information is dynamically
2033 provided by the bootloader and can't always be stored in a static
2034 DTB. To allow a device tree enabled kernel to be used with such
2035 bootloaders, this option allows zImage to extract the information
2036 from the ATAG list and store it at run time into the appended DTB.
2039 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2040 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2042 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2043 bool "Use bootloader kernel arguments if available"
2045 Uses the command-line options passed by the boot loader instead of
2046 the device tree bootargs property. If the boot loader doesn't provide
2047 any, the device tree bootargs property will be used.
2049 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2050 bool "Extend with bootloader kernel arguments"
2052 The command-line arguments provided by the boot loader will be
2053 appended to the the device tree bootargs property.
2058 string "Default kernel command string"
2061 On some architectures (EBSA110 and CATS), there is currently no way
2062 for the boot loader to pass arguments to the kernel. For these
2063 architectures, you should supply some command-line options at build
2064 time by entering them here. As a minimum, you should specify the
2065 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2068 prompt "Kernel command line type" if CMDLINE != ""
2069 default CMDLINE_FROM_BOOTLOADER
2072 config CMDLINE_FROM_BOOTLOADER
2073 bool "Use bootloader kernel arguments if available"
2075 Uses the command-line options passed by the boot loader. If
2076 the boot loader doesn't provide any, the default kernel command
2077 string provided in CMDLINE will be used.
2079 config CMDLINE_EXTEND
2080 bool "Extend bootloader kernel arguments"
2082 The command-line arguments provided by the boot loader will be
2083 appended to the default kernel command string.
2085 config CMDLINE_FORCE
2086 bool "Always use the default kernel command string"
2088 Always use the default kernel command string, even if the boot
2089 loader passes other arguments to the kernel.
2090 This is useful if you cannot or don't want to change the
2091 command-line options your boot loader passes to the kernel.
2095 bool "Kernel Execute-In-Place from ROM"
2096 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2098 Execute-In-Place allows the kernel to run from non-volatile storage
2099 directly addressable by the CPU, such as NOR flash. This saves RAM
2100 space since the text section of the kernel is not loaded from flash
2101 to RAM. Read-write sections, such as the data section and stack,
2102 are still copied to RAM. The XIP kernel is not compressed since
2103 it has to run directly from flash, so it will take more space to
2104 store it. The flash address used to link the kernel object files,
2105 and for storing it, is configuration dependent. Therefore, if you
2106 say Y here, you must know the proper physical address where to
2107 store the kernel image depending on your own flash memory usage.
2109 Also note that the make target becomes "make xipImage" rather than
2110 "make zImage" or "make Image". The final kernel binary to put in
2111 ROM memory will be arch/arm/boot/xipImage.
2115 config XIP_PHYS_ADDR
2116 hex "XIP Kernel Physical Location"
2117 depends on XIP_KERNEL
2118 default "0x00080000"
2120 This is the physical address in your flash memory the kernel will
2121 be linked for and stored to. This address is dependent on your
2125 bool "Kexec system call (EXPERIMENTAL)"
2126 depends on (!SMP || PM_SLEEP_SMP)
2128 kexec is a system call that implements the ability to shutdown your
2129 current kernel, and to start another kernel. It is like a reboot
2130 but it is independent of the system firmware. And like a reboot
2131 you can start any kernel with it, not just Linux.
2133 It is an ongoing process to be certain the hardware in a machine
2134 is properly shutdown, so do not be surprised if this code does not
2135 initially work for you.
2138 bool "Export atags in procfs"
2139 depends on ATAGS && KEXEC
2142 Should the atags used to boot the kernel be exported in an "atags"
2143 file in procfs. Useful with kexec.
2146 bool "Build kdump crash kernel (EXPERIMENTAL)"
2148 Generate crash dump after being started by kexec. This should
2149 be normally only set in special crash dump kernels which are
2150 loaded in the main kernel with kexec-tools into a specially
2151 reserved region and then later executed after a crash by
2152 kdump/kexec. The crash dump kernel must be compiled to a
2153 memory address not used by the main kernel
2155 For more details see Documentation/kdump/kdump.txt
2157 config AUTO_ZRELADDR
2158 bool "Auto calculation of the decompressed kernel image address"
2160 ZRELADDR is the physical address where the decompressed kernel
2161 image will be placed. If AUTO_ZRELADDR is selected, the address
2162 will be determined at run-time by masking the current IP with
2163 0xf8000000. This assumes the zImage being placed in the first 128MB
2164 from start of memory.
2168 menu "CPU Power Management"
2171 source "drivers/cpufreq/Kconfig"
2174 source "drivers/cpuidle/Kconfig"
2178 menu "Floating point emulation"
2180 comment "At least one emulation must be selected"
2183 bool "NWFPE math emulation"
2184 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2186 Say Y to include the NWFPE floating point emulator in the kernel.
2187 This is necessary to run most binaries. Linux does not currently
2188 support floating point hardware so you need to say Y here even if
2189 your machine has an FPA or floating point co-processor podule.
2191 You may say N here if you are going to load the Acorn FPEmulator
2192 early in the bootup.
2195 bool "Support extended precision"
2196 depends on FPE_NWFPE
2198 Say Y to include 80-bit support in the kernel floating-point
2199 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2200 Note that gcc does not generate 80-bit operations by default,
2201 so in most cases this option only enlarges the size of the
2202 floating point emulator without any good reason.
2204 You almost surely want to say N here.
2207 bool "FastFPE math emulation (EXPERIMENTAL)"
2208 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2210 Say Y here to include the FAST floating point emulator in the kernel.
2211 This is an experimental much faster emulator which now also has full
2212 precision for the mantissa. It does not support any exceptions.
2213 It is very simple, and approximately 3-6 times faster than NWFPE.
2215 It should be sufficient for most programs. It may be not suitable
2216 for scientific calculations, but you have to check this for yourself.
2217 If you do not feel you need a faster FP emulation you should better
2221 bool "VFP-format floating point maths"
2222 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2224 Say Y to include VFP support code in the kernel. This is needed
2225 if your hardware includes a VFP unit.
2227 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2228 release notes and additional status information.
2230 Say N if your target does not have VFP hardware.
2238 bool "Advanced SIMD (NEON) Extension support"
2239 depends on VFPv3 && CPU_V7
2241 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2244 config KERNEL_MODE_NEON
2245 bool "Support for NEON in kernel mode"
2246 depends on NEON && AEABI
2248 Say Y to include support for NEON in kernel mode.
2252 menu "Userspace binary formats"
2254 source "fs/Kconfig.binfmt"
2257 tristate "RISC OS personality"
2260 Say Y here to include the kernel code necessary if you want to run
2261 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2262 experimental; if this sounds frightening, say N and sleep in peace.
2263 You can also say M here to compile this support as a module (which
2264 will be called arthur).
2268 menu "Power management options"
2270 source "kernel/power/Kconfig"
2272 config ARCH_SUSPEND_POSSIBLE
2273 depends on !ARCH_S5PC100
2274 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2275 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2278 config ARM_CPU_SUSPEND
2283 source "net/Kconfig"
2285 source "drivers/Kconfig"
2289 source "arch/arm/Kconfig.debug"
2291 source "security/Kconfig"
2293 source "crypto/Kconfig"
2295 source "lib/Kconfig"
2297 source "arch/arm/kvm/Kconfig"