2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
33 /* 2 GHz fixed main PLL */
35 compatible = "fixed-clock";
37 clock-frequency = <2000000000>;
44 enable-method = "marvell,armada-375-smp";
48 compatible = "arm,cortex-a9";
53 compatible = "arm,cortex-a9";
59 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
62 controller = <&mbusc>;
63 interrupt-parent = <&gic>;
64 pcie-mem-aperture = <0xe0000000 0x8000000>;
65 pcie-io-aperture = <0xe8000000 0x100000>;
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
73 compatible = "marvell,mvebu-devbus";
74 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
75 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
78 clocks = <&coreclk 0>;
83 compatible = "marvell,mvebu-devbus";
84 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
85 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
88 clocks = <&coreclk 0>;
93 compatible = "marvell,mvebu-devbus";
94 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
95 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
98 clocks = <&coreclk 0>;
103 compatible = "marvell,mvebu-devbus";
104 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
105 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
106 #address-cells = <1>;
108 clocks = <&coreclk 0>;
113 compatible = "marvell,mvebu-devbus";
114 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
115 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
116 #address-cells = <1>;
118 clocks = <&coreclk 0>;
123 compatible = "simple-bus";
124 #address-cells = <1>;
126 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
128 L2: cache-controller@8000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x8000 0x1000>;
136 compatible = "arm,cortex-a9-scu";
141 compatible = "arm,cortex-a9-twd-timer";
143 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
144 clocks = <&coreclk 2>;
147 gic: interrupt-controller@d000 {
148 compatible = "arm,cortex-a9-gic";
149 #interrupt-cells = <3>;
151 interrupt-controller;
152 reg = <0xd000 0x1000>,
157 #address-cells = <1>;
159 compatible = "marvell,orion-mdio";
161 clocks = <&gateclk 19>;
164 /* Network controller */
166 compatible = "marvell,armada-375-pp2";
167 reg = <0xf0000 0xa000>, /* Packet Processor regs */
168 <0xc0000 0x3060>, /* LMS regs */
169 <0xc4000 0x100>, /* eth0 regs */
170 <0xc5000 0x100>; /* eth1 regs */
171 clocks = <&gateclk 3>, <&gateclk 19>;
172 clock-names = "pp_clk", "gop_clk";
176 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
182 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
189 compatible = "marvell,orion-spi";
190 reg = <0x10600 0x50>;
191 #address-cells = <1>;
194 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&coreclk 0>;
200 compatible = "marvell,orion-spi";
201 reg = <0x10680 0x50>;
202 #address-cells = <1>;
205 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&coreclk 0>;
211 compatible = "marvell,mv64xxx-i2c";
212 reg = <0x11000 0x20>;
213 #address-cells = <1>;
215 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&coreclk 0>;
222 compatible = "marvell,mv64xxx-i2c";
223 reg = <0x11100 0x20>;
224 #address-cells = <1>;
226 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&coreclk 0>;
233 compatible = "snps,dw-apb-uart";
234 reg = <0x12000 0x100>;
236 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&coreclk 0>;
243 compatible = "snps,dw-apb-uart";
244 reg = <0x12100 0x100>;
246 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&coreclk 0>;
253 compatible = "marvell,mv88f6720-pinctrl";
254 reg = <0x18000 0x24>;
256 i2c0_pins: i2c0-pins {
257 marvell,pins = "mpp14", "mpp15";
258 marvell,function = "i2c0";
261 i2c1_pins: i2c1-pins {
262 marvell,pins = "mpp61", "mpp62";
263 marvell,function = "i2c1";
266 nand_pins: nand-pins {
267 marvell,pins = "mpp0", "mpp1", "mpp2",
268 "mpp3", "mpp4", "mpp5",
269 "mpp6", "mpp7", "mpp8",
270 "mpp9", "mpp10", "mpp11",
272 marvell,function = "nand";
275 sdio_pins: sdio-pins {
276 marvell,pins = "mpp24", "mpp25", "mpp26",
277 "mpp27", "mpp28", "mpp29";
278 marvell,function = "sd";
281 spi0_pins: spi0-pins {
282 marvell,pins = "mpp0", "mpp1", "mpp4",
283 "mpp5", "mpp8", "mpp9";
284 marvell,function = "spi0";
289 compatible = "marvell,orion-gpio";
290 reg = <0x18100 0x40>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
303 compatible = "marvell,orion-gpio";
304 reg = <0x18140 0x40>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
317 compatible = "marvell,orion-gpio";
318 reg = <0x18180 0x40>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
327 system-controller@18200 {
328 compatible = "marvell,armada-375-system-controller";
329 reg = <0x18200 0x100>;
332 gateclk: clock-gating-control@18220 {
333 compatible = "marvell,armada-375-gating-clock";
335 clocks = <&coreclk 0>;
339 mbusc: mbus-controller@20000 {
340 compatible = "marvell,mbus-controller";
341 reg = <0x20000 0x100>, <0x20180 0x20>;
344 mpic: interrupt-controller@20000 {
345 compatible = "marvell,mpic";
346 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
347 #interrupt-cells = <1>;
349 interrupt-controller;
351 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
355 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
356 reg = <0x20300 0x30>, <0x21040 0x30>;
357 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
358 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
359 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
360 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
363 clocks = <&coreclk 0>;
367 compatible = "marvell,armada-375-wdt";
368 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
369 clocks = <&coreclk 0>;
373 compatible = "marvell,armada-370-cpu-reset";
374 reg = <0x20800 0x10>;
377 coherency-fabric@21010 {
378 compatible = "marvell,armada-375-coherency-fabric";
379 reg = <0x21010 0x1c>;
383 compatible = "marvell,orion-ehci";
384 reg = <0x50000 0x500>;
385 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&gateclk 18>;
391 compatible = "marvell,orion-ehci";
392 reg = <0x54000 0x500>;
393 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&gateclk 26>;
399 compatible = "marvell,armada-375-xhci";
400 reg = <0x58000 0x20000>,<0x5b880 0x80>;
401 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&gateclk 16>;
407 compatible = "marvell,orion-xor";
410 clocks = <&gateclk 22>;
414 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
419 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
427 compatible = "marvell,orion-xor";
430 clocks = <&gateclk 23>;
434 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
439 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
447 compatible = "marvell,orion-sata";
448 reg = <0xa0000 0x5000>;
449 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&gateclk 14>, <&gateclk 20>;
451 clock-names = "0", "1";
456 compatible = "marvell,armada370-nand";
457 reg = <0xd0000 0x54>;
458 #address-cells = <1>;
460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&gateclk 11>;
466 compatible = "marvell,orion-sdio";
467 reg = <0xd4000 0x200>;
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&gateclk 17>;
478 compatible = "marvell,armada375-thermal";
479 reg = <0xe8078 0x4>, <0xe807c 0x8>;
483 coreclk: mvebu-sar@e8204 {
484 compatible = "marvell,armada-375-core-clock";
485 reg = <0xe8204 0x04>;
489 coredivclk: corediv-clock@e8250 {
490 compatible = "marvell,armada-375-corediv-clock";
494 clock-output-names = "nand";
499 compatible = "marvell,armada-370-pcie";
503 #address-cells = <3>;
506 msi-parent = <&mpic>;
507 bus-range = <0x00 0xff>;
510 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
511 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
512 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
513 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
514 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
515 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
519 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
520 reg = <0x0800 0 0 0 0>;
521 #address-cells = <3>;
523 #interrupt-cells = <1>;
524 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
525 0x81000000 0 0 0x81000000 0x1 0 1 0>;
526 interrupt-map-mask = <0 0 0 0>;
527 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
528 marvell,pcie-port = <0>;
529 marvell,pcie-lane = <0>;
530 clocks = <&gateclk 5>;
536 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
537 reg = <0x1000 0 0 0 0>;
538 #address-cells = <3>;
540 #interrupt-cells = <1>;
541 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
542 0x81000000 0 0 0x81000000 0x2 0 1 0>;
543 interrupt-map-mask = <0 0 0 0>;
544 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
545 marvell,pcie-port = <0>;
546 marvell,pcie-lane = <1>;
547 clocks = <&gateclk 6>;