2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 #include "skeleton.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
18 intc: interrupt-controller@fffee000 {
19 compatible = "ti,cp-intc";
21 #interrupt-cells = <1>;
23 reg = <0xfffee000 0x2000>;
27 compatible = "simple-bus";
31 ranges = <0x0 0x01c00000 0x400000>;
32 interrupt-parent = <&intc>;
34 pmx_core: pinmux@14120 {
35 compatible = "pinctrl-single";
39 pinctrl-single,bit-per-mux;
40 pinctrl-single,register-width = <32>;
41 pinctrl-single,function-mask = <0xf>;
44 nand_cs3_pins: pinmux_nand_pins {
45 pinctrl-single,bits = <
47 0x1c 0x00110000 0x00ff0000
48 /* EMA_CS[4],EMA_CS[3]*/
49 0x1c 0x00000110 0x00000ff0
51 * EMA_D[0], EMA_D[1], EMA_D[2],
52 * EMA_D[3], EMA_D[4], EMA_D[5],
55 0x24 0x11111111 0xffffffff
56 /* EMA_A[1], EMA_A[2] */
57 0x30 0x01100000 0x0ff00000
60 i2c0_pins: pinmux_i2c0_pins {
61 pinctrl-single,bits = <
62 /* I2C0_SDA,I2C0_SCL */
63 0x10 0x00002200 0x0000ff00
66 i2c1_pins: pinmux_i2c1_pins {
67 pinctrl-single,bits = <
68 /* I2C1_SDA, I2C1_SCL */
69 0x10 0x00440000 0x00ff0000
72 mmc0_pins: pinmux_mmc_pins {
73 pinctrl-single,bits = <
74 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
75 * MMCSD0_DAT[1] MMCSD0_DAT[0]
76 * MMCSD0_CMD MMCSD0_CLK
78 0x28 0x00222222 0x00ffffff
81 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
82 pinctrl-single,bits = <
84 0xc 0x00000002 0x0000000f
87 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
88 pinctrl-single,bits = <
90 0xc 0x00000020 0x000000f0
93 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
94 pinctrl-single,bits = <
96 0x14 0x00000002 0x0000000f
99 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
100 pinctrl-single,bits = <
102 0x14 0x00000020 0x000000f0
105 ecap0_pins: pinmux_ecap0_pins {
106 pinctrl-single,bits = <
108 0x8 0x20000000 0xf0000000
111 ecap1_pins: pinmux_ecap1_pins {
112 pinctrl-single,bits = <
114 0x4 0x40000000 0xf0000000
117 ecap2_pins: pinmux_ecap2_pins {
118 pinctrl-single,bits = <
120 0x4 0x00000004 0x0000000f
123 spi1_pins: pinmux_spi_pins {
124 pinctrl-single,bits = <
125 /* SIMO, SOMI, CLK */
126 0x14 0x00110100 0x00ff0f00
129 spi1_cs0_pin: pinmux_spi1_cs0 {
130 pinctrl-single,bits = <
132 0x14 0x00000010 0x000000f0
135 mdio_pins: pinmux_mdio_pins {
136 pinctrl-single,bits = <
137 /* MDIO_CLK, MDIO_D */
138 0x10 0x00000088 0x000000ff
141 mii_pins: pinmux_mii_pins {
142 pinctrl-single,bits = <
144 * MII_TXEN, MII_TXCLK, MII_COL
145 * MII_TXD_3, MII_TXD_2, MII_TXD_1
148 0x8 0x88888880 0xfffffff0
150 * MII_RXER, MII_CRS, MII_RXCLK
151 * MII_RXDV, MII_RXD_3, MII_RXD_2
152 * MII_RXD_1, MII_RXD_0
154 0xc 0x88888888 0xffffffff
160 compatible = "ti,edma3-tpcc";
161 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
163 reg-names = "edma3_cc";
164 interrupts = <11 12>;
165 interrupt-names = "edma3_ccint", "edma3_ccerrint";
168 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
170 edma0_tptc0: tptc@8000 {
171 compatible = "ti,edma3-tptc";
172 reg = <0x8000 0x400>;
174 interrupt-names = "edm3_tcerrint";
176 edma0_tptc1: tptc@8400 {
177 compatible = "ti,edma3-tptc";
178 reg = <0x8400 0x400>;
180 interrupt-names = "edm3_tcerrint";
183 compatible = "ti,edma3-tpcc";
184 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
185 reg = <0x230000 0x8000>;
186 reg-names = "edma3_cc";
187 interrupts = <93 94>;
188 interrupt-names = "edma3_ccint", "edma3_ccerrint";
191 ti,tptcs = <&edma1_tptc0 7>;
193 edma1_tptc0: tptc@238000 {
194 compatible = "ti,edma3-tptc";
195 reg = <0x238000 0x400>;
197 interrupt-names = "edm3_tcerrint";
199 serial0: serial@42000 {
200 compatible = "ns16550a";
201 reg = <0x42000 0x100>;
206 serial1: serial@10c000 {
207 compatible = "ns16550a";
208 reg = <0x10c000 0x100>;
213 serial2: serial@10d000 {
214 compatible = "ns16550a";
215 reg = <0x10d000 0x100>;
221 compatible = "ti,da830-rtc";
222 reg = <0x23000 0x1000>;
228 compatible = "ti,davinci-i2c";
229 reg = <0x22000 0x1000>;
231 #address-cells = <1>;
236 compatible = "ti,davinci-i2c";
237 reg = <0x228000 0x1000>;
239 #address-cells = <1>;
244 compatible = "ti,davinci-wdt";
245 reg = <0x21000 0x1000>;
249 compatible = "ti,da830-mmc";
250 reg = <0x40000 0x1000>;
252 dmas = <&edma0 16 0>, <&edma0 17 0>;
253 dma-names = "rx", "tx";
257 compatible = "ti,da830-mmc";
258 reg = <0x21b000 0x1000>;
260 dmas = <&edma1 28 0>, <&edma1 29 0>;
261 dma-names = "rx", "tx";
264 ehrpwm0: pwm@300000 {
265 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
267 reg = <0x300000 0x2000>;
270 ehrpwm1: pwm@302000 {
271 compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
273 reg = <0x302000 0x2000>;
277 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
279 reg = <0x306000 0x80>;
283 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
285 reg = <0x307000 0x80>;
289 compatible = "ti,da850-ecap", "ti,am33xx-ecap";
291 reg = <0x308000 0x80>;
295 #address-cells = <1>;
297 compatible = "ti,da830-spi";
298 reg = <0x30e000 0x1000>;
300 ti,davinci-spi-intr-line = <1>;
302 dmas = <&edma0 18 0>, <&edma0 19 0>;
303 dma-names = "rx", "tx";
307 compatible = "ti,davinci_mdio";
308 #address-cells = <1>;
310 reg = <0x224000 0x1000>;
312 eth0: ethernet@220000 {
313 compatible = "ti,davinci-dm6467-emac";
314 reg = <0x220000 0x4000>;
315 ti,davinci-ctrl-reg-offset = <0x3000>;
316 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
317 ti,davinci-ctrl-ram-offset = <0>;
318 ti,davinci-ctrl-ram-size = <0x2000>;
319 local-mac-address = [ 00 00 00 00 00 00 ];
327 compatible = "ti,dm6441-gpio";
330 reg = <0x226000 0x1000>;
331 interrupts = <42 IRQ_TYPE_EDGE_BOTH
332 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
333 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
334 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
335 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
337 ti,davinci-gpio-unbanked = <0>;
341 mcasp0: mcasp@100000 {
342 compatible = "ti,da830-mcasp-audio";
343 reg = <0x100000 0x2000>,
345 reg-names = "mpu", "dat";
347 interrupt-names = "common";
351 dma-names = "tx", "rx";
355 compatible = "ti,davinci-nand";
356 reg = <0x62000000 0x807ff
358 ti,davinci-chipselect = <1>;
359 ti,davinci-mask-ale = <0>;
360 ti,davinci-mask-cle = <0>;
361 ti,davinci-mask-chipsel = <0>;
362 ti,davinci-ecc-mode = "hw";
363 ti,davinci-ecc-bits = <4>;
364 ti,davinci-nand-use-bbt;