arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         clock_audss: clock-controller@03810000 {
  55                 compatible = "samsung,exynos4210-audss-clock";
  56                 reg = <0x03810000 0x0C>;
  57                 #clock-cells = <1>;
  58         };
  59
  60         i2s0: i2s@03830000 {
  61                 compatible = "samsung,s5pv210-i2s";
  62                 reg = <0x03830000 0x100>;
  63                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  64                 clock-names = "iis";
  65                 #clock-cells = <1>;
  66                 clock-output-names = "i2s_cdclk0";
  67                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  68                 dma-names = "tx", "rx", "tx-sec";
  69                 samsung,idma-addr = <0x03000000>;
  70                 #sound-dai-cells = <1>;
  71                 status = "disabled";
  72         };
  73
  74         chipid@10000000 {
  75                 compatible = "samsung,exynos4210-chipid";
  76                 reg = <0x10000000 0x100>;
  77         };
  78
  79         mipi_phy: video-phy@10020710 {
  80                 compatible = "samsung,s5pv210-mipi-video-phy";
  81                 #phy-cells = <1>;
  82                 syscon = <&pmu_system_controller>;
  83         };
  84
  85         pd_mfc: mfc-power-domain@10023C40 {
  86                 compatible = "samsung,exynos4210-pd";
  87                 reg = <0x10023C40 0x20>;
  88                 #power-domain-cells = <0>;
  89         };
  90
  91         pd_g3d: g3d-power-domain@10023C60 {
  92                 compatible = "samsung,exynos4210-pd";
  93                 reg = <0x10023C60 0x20>;
  94                 #power-domain-cells = <0>;
  95         };
  96
  97         pd_lcd0: lcd0-power-domain@10023C80 {
  98                 compatible = "samsung,exynos4210-pd";
  99                 reg = <0x10023C80 0x20>;
 100                 #power-domain-cells = <0>;
 101         };
 102
 103         pd_tv: tv-power-domain@10023C20 {
 104                 compatible = "samsung,exynos4210-pd";
 105                 reg = <0x10023C20 0x20>;
 106                 #power-domain-cells = <0>;
 107                 power-domains = <&pd_lcd0>;
 108         };
 109
 110         pd_cam: cam-power-domain@10023C00 {
 111                 compatible = "samsung,exynos4210-pd";
 112                 reg = <0x10023C00 0x20>;
 113                 #power-domain-cells = <0>;
 114         };
 115
 116         pd_gps: gps-power-domain@10023CE0 {
 117                 compatible = "samsung,exynos4210-pd";
 118                 reg = <0x10023CE0 0x20>;
 119                 #power-domain-cells = <0>;
 120         };
 121
 122         pd_gps_alive: gps-alive-power-domain@10023D00 {
 123                 compatible = "samsung,exynos4210-pd";
 124                 reg = <0x10023D00 0x20>;
 125                 #power-domain-cells = <0>;
 126         };
 127
 128         gic: interrupt-controller@10490000 {
 129                 compatible = "arm,cortex-a9-gic";
 130                 #interrupt-cells = <3>;
 131                 interrupt-controller;
 132                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 133         };
 134
 135         combiner: interrupt-controller@10440000 {
 136                 compatible = "samsung,exynos4210-combiner";
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139                 reg = <0x10440000 0x1000>;
 140         };
 141
 142         pmu {
 143                 compatible = "arm,cortex-a9-pmu";
 144                 interrupt-parent = <&combiner>;
 145                 interrupts = <2 2>, <3 2>;
 146         };
 147
 148         sys_reg: syscon@10010000 {
 149                 compatible = "samsung,exynos4-sysreg", "syscon";
 150                 reg = <0x10010000 0x400>;
 151         };
 152
 153         pmu_system_controller: system-controller@10020000 {
 154                 compatible = "samsung,exynos4210-pmu", "syscon";
 155                 reg = <0x10020000 0x4000>;
 156                 interrupt-controller;
 157                 #interrupt-cells = <3>;
 158                 interrupt-parent = <&gic>;
 159         };
 160
 161         poweroff: syscon-poweroff {
 162                 compatible = "syscon-poweroff";
 163                 regmap = <&pmu_system_controller>;
 164                 offset = <0x330C>; /* PS_HOLD_CONTROL */
 165                 mask = <0x5200>; /* reset value */
 166         };
 167
 168         reboot: syscon-reboot {
 169                 compatible = "syscon-reboot";
 170                 regmap = <&pmu_system_controller>;
 171                 offset = <0x0400>; /* SWRESET */
 172                 mask = <0x1>;
 173         };
 174
 175         dsi_0: dsi@11C80000 {
 176                 compatible = "samsung,exynos4210-mipi-dsi";
 177                 reg = <0x11C80000 0x10000>;
 178                 interrupts = <0 79 0>;
 179                 power-domains = <&pd_lcd0>;
 180                 phys = <&mipi_phy 1>;
 181                 phy-names = "dsim";
 182                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 183                 clock-names = "bus_clk", "sclk_mipi";
 184                 status = "disabled";
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187         };
 188
 189         camera {
 190                 compatible = "samsung,fimc", "simple-bus";
 191                 status = "disabled";
 192                 #address-cells = <1>;
 193                 #size-cells = <1>;
 194                 #clock-cells = <1>;
 195                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 196                 ranges;
 197
 198                 fimc_0: fimc@11800000 {
 199                         compatible = "samsung,exynos4210-fimc";
 200                         reg = <0x11800000 0x1000>;
 201                         interrupts = <0 84 0>;
 202                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 203                         clock-names = "fimc", "sclk_fimc";
 204                         power-domains = <&pd_cam>;
 205                         samsung,sysreg = <&sys_reg>;
 206                         iommus = <&sysmmu_fimc0>;
 207                         status = "disabled";
 208                 };
 209
 210                 fimc_1: fimc@11810000 {
 211                         compatible = "samsung,exynos4210-fimc";
 212                         reg = <0x11810000 0x1000>;
 213                         interrupts = <0 85 0>;
 214                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 215                         clock-names = "fimc", "sclk_fimc";
 216                         power-domains = <&pd_cam>;
 217                         samsung,sysreg = <&sys_reg>;
 218                         iommus = <&sysmmu_fimc1>;
 219                         status = "disabled";
 220                 };
 221
 222                 fimc_2: fimc@11820000 {
 223                         compatible = "samsung,exynos4210-fimc";
 224                         reg = <0x11820000 0x1000>;
 225                         interrupts = <0 86 0>;
 226                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 227                         clock-names = "fimc", "sclk_fimc";
 228                         power-domains = <&pd_cam>;
 229                         samsung,sysreg = <&sys_reg>;
 230                         iommus = <&sysmmu_fimc2>;
 231                         status = "disabled";
 232                 };
 233
 234                 fimc_3: fimc@11830000 {
 235                         compatible = "samsung,exynos4210-fimc";
 236                         reg = <0x11830000 0x1000>;
 237                         interrupts = <0 87 0>;
 238                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 239                         clock-names = "fimc", "sclk_fimc";
 240                         power-domains = <&pd_cam>;
 241                         samsung,sysreg = <&sys_reg>;
 242                         iommus = <&sysmmu_fimc3>;
 243                         status = "disabled";
 244                 };
 245
 246                 csis_0: csis@11880000 {
 247                         compatible = "samsung,exynos4210-csis";
 248                         reg = <0x11880000 0x4000>;
 249                         interrupts = <0 78 0>;
 250                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 251                         clock-names = "csis", "sclk_csis";
 252                         bus-width = <4>;
 253                         power-domains = <&pd_cam>;
 254                         phys = <&mipi_phy 0>;
 255                         phy-names = "csis";
 256                         status = "disabled";
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                 };
 260
 261                 csis_1: csis@11890000 {
 262                         compatible = "samsung,exynos4210-csis";
 263                         reg = <0x11890000 0x4000>;
 264                         interrupts = <0 80 0>;
 265                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 266                         clock-names = "csis", "sclk_csis";
 267                         bus-width = <2>;
 268                         power-domains = <&pd_cam>;
 269                         phys = <&mipi_phy 2>;
 270                         phy-names = "csis";
 271                         status = "disabled";
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                 };
 275         };
 276
 277         watchdog: watchdog@10060000 {
 278                 compatible = "samsung,s3c2410-wdt";
 279                 reg = <0x10060000 0x100>;
 280                 interrupts = <0 43 0>;
 281                 clocks = <&clock CLK_WDT>;
 282                 clock-names = "watchdog";
 283                 status = "disabled";
 284         };
 285
 286         rtc: rtc@10070000 {
 287                 compatible = "samsung,s3c6410-rtc";
 288                 reg = <0x10070000 0x100>;
 289                 interrupt-parent = <&pmu_system_controller>;
 290                 interrupts = <0 44 0>, <0 45 0>;
 291                 clocks = <&clock CLK_RTC>;
 292                 clock-names = "rtc";
 293                 status = "disabled";
 294         };
 295
 296         keypad: keypad@100A0000 {
 297                 compatible = "samsung,s5pv210-keypad";
 298                 reg = <0x100A0000 0x100>;
 299                 interrupts = <0 109 0>;
 300                 clocks = <&clock CLK_KEYIF>;
 301                 clock-names = "keypad";
 302                 status = "disabled";
 303         };
 304
 305         sdhci_0: sdhci@12510000 {
 306                 compatible = "samsung,exynos4210-sdhci";
 307                 reg = <0x12510000 0x100>;
 308                 interrupts = <0 73 0>;
 309                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 310                 clock-names = "hsmmc", "mmc_busclk.2";
 311                 status = "disabled";
 312         };
 313
 314         sdhci_1: sdhci@12520000 {
 315                 compatible = "samsung,exynos4210-sdhci";
 316                 reg = <0x12520000 0x100>;
 317                 interrupts = <0 74 0>;
 318                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 319                 clock-names = "hsmmc", "mmc_busclk.2";
 320                 status = "disabled";
 321         };
 322
 323         sdhci_2: sdhci@12530000 {
 324                 compatible = "samsung,exynos4210-sdhci";
 325                 reg = <0x12530000 0x100>;
 326                 interrupts = <0 75 0>;
 327                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 328                 clock-names = "hsmmc", "mmc_busclk.2";
 329                 status = "disabled";
 330         };
 331
 332         sdhci_3: sdhci@12540000 {
 333                 compatible = "samsung,exynos4210-sdhci";
 334                 reg = <0x12540000 0x100>;
 335                 interrupts = <0 76 0>;
 336                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 337                 clock-names = "hsmmc", "mmc_busclk.2";
 338                 status = "disabled";
 339         };
 340
 341         exynos_usbphy: exynos-usbphy@125B0000 {
 342                 compatible = "samsung,exynos4210-usb2-phy";
 343                 reg = <0x125B0000 0x100>;
 344                 samsung,pmureg-phandle = <&pmu_system_controller>;
 345                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 346                 clock-names = "phy", "ref";
 347                 #phy-cells = <1>;
 348                 status = "disabled";
 349         };
 350
 351         hsotg: hsotg@12480000 {
 352                 compatible = "samsung,s3c6400-hsotg";
 353                 reg = <0x12480000 0x20000>;
 354                 interrupts = <0 71 0>;
 355                 clocks = <&clock CLK_USB_DEVICE>;
 356                 clock-names = "otg";
 357                 phys = <&exynos_usbphy 0>;
 358                 phy-names = "usb2-phy";
 359                 status = "disabled";
 360         };
 361
 362         ehci: ehci@12580000 {
 363                 compatible = "samsung,exynos4210-ehci";
 364                 reg = <0x12580000 0x100>;
 365                 interrupts = <0 70 0>;
 366                 clocks = <&clock CLK_USB_HOST>;
 367                 clock-names = "usbhost";
 368                 status = "disabled";
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 port@0 {
 372                     reg = <0>;
 373                     phys = <&exynos_usbphy 1>;
 374                     status = "disabled";
 375                 };
 376                 port@1 {
 377                     reg = <1>;
 378                     phys = <&exynos_usbphy 2>;
 379                     status = "disabled";
 380                 };
 381                 port@2 {
 382                     reg = <2>;
 383                     phys = <&exynos_usbphy 3>;
 384                     status = "disabled";
 385                 };
 386         };
 387
 388         ohci: ohci@12590000 {
 389                 compatible = "samsung,exynos4210-ohci";
 390                 reg = <0x12590000 0x100>;
 391                 interrupts = <0 70 0>;
 392                 clocks = <&clock CLK_USB_HOST>;
 393                 clock-names = "usbhost";
 394                 status = "disabled";
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 port@0 {
 398                     reg = <0>;
 399                     phys = <&exynos_usbphy 1>;
 400                     status = "disabled";
 401                 };
 402         };
 403
 404         i2s1: i2s@13960000 {
 405                 compatible = "samsung,s3c6410-i2s";
 406                 reg = <0x13960000 0x100>;
 407                 clocks = <&clock CLK_I2S1>;
 408                 clock-names = "iis";
 409                 #clock-cells = <1>;
 410                 clock-output-names = "i2s_cdclk1";
 411                 dmas = <&pdma1 12>, <&pdma1 11>;
 412                 dma-names = "tx", "rx";
 413                 #sound-dai-cells = <1>;
 414                 status = "disabled";
 415         };
 416
 417         i2s2: i2s@13970000 {
 418                 compatible = "samsung,s3c6410-i2s";
 419                 reg = <0x13970000 0x100>;
 420                 clocks = <&clock CLK_I2S2>;
 421                 clock-names = "iis";
 422                 #clock-cells = <1>;
 423                 clock-output-names = "i2s_cdclk2";
 424                 dmas = <&pdma0 14>, <&pdma0 13>;
 425                 dma-names = "tx", "rx";
 426                 #sound-dai-cells = <1>;
 427                 status = "disabled";
 428         };
 429
 430         mfc: codec@13400000 {
 431                 compatible = "samsung,mfc-v5";
 432                 reg = <0x13400000 0x10000>;
 433                 interrupts = <0 94 0>;
 434                 power-domains = <&pd_mfc>;
 435                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 436                 clock-names = "mfc", "sclk_mfc";
 437                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 438                 iommu-names = "left", "right";
 439                 status = "disabled";
 440         };
 441
 442         serial_0: serial@13800000 {
 443                 compatible = "samsung,exynos4210-uart";
 444                 reg = <0x13800000 0x100>;
 445                 interrupts = <0 52 0>;
 446                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 447                 clock-names = "uart", "clk_uart_baud0";
 448                 dmas = <&pdma0 15>, <&pdma0 16>;
 449                 dma-names = "rx", "tx";
 450                 status = "disabled";
 451         };
 452
 453         serial_1: serial@13810000 {
 454                 compatible = "samsung,exynos4210-uart";
 455                 reg = <0x13810000 0x100>;
 456                 interrupts = <0 53 0>;
 457                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 458                 clock-names = "uart", "clk_uart_baud0";
 459                 dmas = <&pdma1 15>, <&pdma1 16>;
 460                 dma-names = "rx", "tx";
 461                 status = "disabled";
 462         };
 463
 464         serial_2: serial@13820000 {
 465                 compatible = "samsung,exynos4210-uart";
 466                 reg = <0x13820000 0x100>;
 467                 interrupts = <0 54 0>;
 468                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 469                 clock-names = "uart", "clk_uart_baud0";
 470                 dmas = <&pdma0 17>, <&pdma0 18>;
 471                 dma-names = "rx", "tx";
 472                 status = "disabled";
 473         };
 474
 475         serial_3: serial@13830000 {
 476                 compatible = "samsung,exynos4210-uart";
 477                 reg = <0x13830000 0x100>;
 478                 interrupts = <0 55 0>;
 479                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 480                 clock-names = "uart", "clk_uart_baud0";
 481                 dmas = <&pdma1 17>, <&pdma1 18>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         i2c_0: i2c@13860000 {
 487                 #address-cells = <1>;
 488                 #size-cells = <0>;
 489                 compatible = "samsung,s3c2440-i2c";
 490                 reg = <0x13860000 0x100>;
 491                 interrupts = <0 58 0>;
 492                 clocks = <&clock CLK_I2C0>;
 493                 clock-names = "i2c";
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&i2c0_bus>;
 496                 status = "disabled";
 497         };
 498
 499         i2c_1: i2c@13870000 {
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 compatible = "samsung,s3c2440-i2c";
 503                 reg = <0x13870000 0x100>;
 504                 interrupts = <0 59 0>;
 505                 clocks = <&clock CLK_I2C1>;
 506                 clock-names = "i2c";
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&i2c1_bus>;
 509                 status = "disabled";
 510         };
 511
 512         i2c_2: i2c@13880000 {
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 compatible = "samsung,s3c2440-i2c";
 516                 reg = <0x13880000 0x100>;
 517                 interrupts = <0 60 0>;
 518                 clocks = <&clock CLK_I2C2>;
 519                 clock-names = "i2c";
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c2_bus>;
 522                 status = "disabled";
 523         };
 524
 525         i2c_3: i2c@13890000 {
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 compatible = "samsung,s3c2440-i2c";
 529                 reg = <0x13890000 0x100>;
 530                 interrupts = <0 61 0>;
 531                 clocks = <&clock CLK_I2C3>;
 532                 clock-names = "i2c";
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c3_bus>;
 535                 status = "disabled";
 536         };
 537
 538         i2c_4: i2c@138A0000 {
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 compatible = "samsung,s3c2440-i2c";
 542                 reg = <0x138A0000 0x100>;
 543                 interrupts = <0 62 0>;
 544                 clocks = <&clock CLK_I2C4>;
 545                 clock-names = "i2c";
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c4_bus>;
 548                 status = "disabled";
 549         };
 550
 551         i2c_5: i2c@138B0000 {
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 compatible = "samsung,s3c2440-i2c";
 555                 reg = <0x138B0000 0x100>;
 556                 interrupts = <0 63 0>;
 557                 clocks = <&clock CLK_I2C5>;
 558                 clock-names = "i2c";
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c5_bus>;
 561                 status = "disabled";
 562         };
 563
 564         i2c_6: i2c@138C0000 {
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 compatible = "samsung,s3c2440-i2c";
 568                 reg = <0x138C0000 0x100>;
 569                 interrupts = <0 64 0>;
 570                 clocks = <&clock CLK_I2C6>;
 571                 clock-names = "i2c";
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c6_bus>;
 574                 status = "disabled";
 575         };
 576
 577         i2c_7: i2c@138D0000 {
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 compatible = "samsung,s3c2440-i2c";
 581                 reg = <0x138D0000 0x100>;
 582                 interrupts = <0 65 0>;
 583                 clocks = <&clock CLK_I2C7>;
 584                 clock-names = "i2c";
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c7_bus>;
 587                 status = "disabled";
 588         };
 589
 590         i2c_8: i2c@138E0000 {
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 594                 reg = <0x138E0000 0x100>;
 595                 interrupts = <0 93 0>;
 596                 clocks = <&clock CLK_I2C_HDMI>;
 597                 clock-names = "i2c";
 598                 status = "disabled";
 599
 600                 hdmi_i2c_phy: hdmiphy@38 {
 601                         compatible = "exynos4210-hdmiphy";
 602                         reg = <0x38>;
 603                 };
 604         };
 605
 606         spi_0: spi@13920000 {
 607                 compatible = "samsung,exynos4210-spi";
 608                 reg = <0x13920000 0x100>;
 609                 interrupts = <0 66 0>;
 610                 dmas = <&pdma0 7>, <&pdma0 6>;
 611                 dma-names = "tx", "rx";
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 615                 clock-names = "spi", "spi_busclk0";
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&spi0_bus>;
 618                 status = "disabled";
 619         };
 620
 621         spi_1: spi@13930000 {
 622                 compatible = "samsung,exynos4210-spi";
 623                 reg = <0x13930000 0x100>;
 624                 interrupts = <0 67 0>;
 625                 dmas = <&pdma1 7>, <&pdma1 6>;
 626                 dma-names = "tx", "rx";
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 630                 clock-names = "spi", "spi_busclk0";
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&spi1_bus>;
 633                 status = "disabled";
 634         };
 635
 636         spi_2: spi@13940000 {
 637                 compatible = "samsung,exynos4210-spi";
 638                 reg = <0x13940000 0x100>;
 639                 interrupts = <0 68 0>;
 640                 dmas = <&pdma0 9>, <&pdma0 8>;
 641                 dma-names = "tx", "rx";
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 645                 clock-names = "spi", "spi_busclk0";
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&spi2_bus>;
 648                 status = "disabled";
 649         };
 650
 651         pwm: pwm@139D0000 {
 652                 compatible = "samsung,exynos4210-pwm";
 653                 reg = <0x139D0000 0x1000>;
 654                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 655                 clocks = <&clock CLK_PWM>;
 656                 clock-names = "timers";
 657                 #pwm-cells = <3>;
 658                 status = "disabled";
 659         };
 660
 661         amba {
 662                 #address-cells = <1>;
 663                 #size-cells = <1>;
 664                 compatible = "arm,amba-bus";
 665                 interrupt-parent = <&gic>;
 666                 ranges;
 667
 668                 pdma0: pdma@12680000 {
 669                         compatible = "arm,pl330", "arm,primecell";
 670                         reg = <0x12680000 0x1000>;
 671                         interrupts = <0 35 0>;
 672                         clocks = <&clock CLK_PDMA0>;
 673                         clock-names = "apb_pclk";
 674                         #dma-cells = <1>;
 675                         #dma-channels = <8>;
 676                         #dma-requests = <32>;
 677                 };
 678
 679                 pdma1: pdma@12690000 {
 680                         compatible = "arm,pl330", "arm,primecell";
 681                         reg = <0x12690000 0x1000>;
 682                         interrupts = <0 36 0>;
 683                         clocks = <&clock CLK_PDMA1>;
 684                         clock-names = "apb_pclk";
 685                         #dma-cells = <1>;
 686                         #dma-channels = <8>;
 687                         #dma-requests = <32>;
 688                 };
 689
 690                 mdma1: mdma@12850000 {
 691                         compatible = "arm,pl330", "arm,primecell";
 692                         reg = <0x12850000 0x1000>;
 693                         interrupts = <0 34 0>;
 694                         clocks = <&clock CLK_MDMA>;
 695                         clock-names = "apb_pclk";
 696                         #dma-cells = <1>;
 697                         #dma-channels = <8>;
 698                         #dma-requests = <1>;
 699                 };
 700         };
 701
 702         fimd: fimd@11c00000 {
 703                 compatible = "samsung,exynos4210-fimd";
 704                 interrupt-parent = <&combiner>;
 705                 reg = <0x11c00000 0x20000>;
 706                 interrupt-names = "fifo", "vsync", "lcd_sys";
 707                 interrupts = <11 0>, <11 1>, <11 2>;
 708                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 709                 clock-names = "sclk_fimd", "fimd";
 710                 power-domains = <&pd_lcd0>;
 711                 iommus = <&sysmmu_fimd0>;
 712                 samsung,sysreg = <&sys_reg>;
 713                 status = "disabled";
 714         };
 715
 716         tmu: tmu@100C0000 {
 717                 #include "exynos4412-tmu-sensor-conf.dtsi"
 718         };
 719
 720         jpeg_codec: jpeg-codec@11840000 {
 721                 compatible = "samsung,exynos4210-jpeg";
 722                 reg = <0x11840000 0x1000>;
 723                 interrupts = <0 88 0>;
 724                 clocks = <&clock CLK_JPEG>;
 725                 clock-names = "jpeg";
 726                 power-domains = <&pd_cam>;
 727                 iommus = <&sysmmu_jpeg>;
 728         };
 729
 730         hdmi: hdmi@12D00000 {
 731                 compatible = "samsung,exynos4210-hdmi";
 732                 reg = <0x12D00000 0x70000>;
 733                 interrupts = <0 92 0>;
 734                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
 735                         "mout_hdmi";
 736                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 737                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 738                         <&clock CLK_MOUT_HDMI>;
 739                 phy = <&hdmi_i2c_phy>;
 740                 power-domains = <&pd_tv>;
 741                 samsung,syscon-phandle = <&pmu_system_controller>;
 742                 status = "disabled";
 743         };
 744
 745         mixer: mixer@12C10000 {
 746                 compatible = "samsung,exynos4210-mixer";
 747                 interrupts = <0 91 0>;
 748                 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 749                 power-domains = <&pd_tv>;
 750                 iommus = <&sysmmu_tv>;
 751                 status = "disabled";
 752         };
 753
 754         ppmu_dmc0: ppmu_dmc0@106a0000 {
 755                 compatible = "samsung,exynos-ppmu";
 756                 reg = <0x106a0000 0x2000>;
 757                 clocks = <&clock CLK_PPMUDMC0>;
 758                 clock-names = "ppmu";
 759                 status = "disabled";
 760         };
 761
 762         ppmu_dmc1: ppmu_dmc1@106b0000 {
 763                 compatible = "samsung,exynos-ppmu";
 764                 reg = <0x106b0000 0x2000>;
 765                 clocks = <&clock CLK_PPMUDMC1>;
 766                 clock-names = "ppmu";
 767                 status = "disabled";
 768         };
 769
 770         ppmu_cpu: ppmu_cpu@106c0000 {
 771                 compatible = "samsung,exynos-ppmu";
 772                 reg = <0x106c0000 0x2000>;
 773                 clocks = <&clock CLK_PPMUCPU>;
 774                 clock-names = "ppmu";
 775                 status = "disabled";
 776         };
 777
 778         ppmu_acp: ppmu_acp@10ae0000 {
 779                 compatible = "samsung,exynos-ppmu";
 780                 reg = <0x106e0000 0x2000>;
 781                 status = "disabled";
 782         };
 783
 784         ppmu_rightbus: ppmu_rightbus@112a0000 {
 785                 compatible = "samsung,exynos-ppmu";
 786                 reg = <0x112a0000 0x2000>;
 787                 clocks = <&clock CLK_PPMURIGHT>;
 788                 clock-names = "ppmu";
 789                 status = "disabled";
 790         };
 791
 792         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 793                 compatible = "samsung,exynos-ppmu";
 794                 reg = <0x116a0000 0x2000>;
 795                 clocks = <&clock CLK_PPMULEFT>;
 796                 clock-names = "ppmu";
 797                 status = "disabled";
 798         };
 799
 800         ppmu_camif: ppmu_camif@11ac0000 {
 801                 compatible = "samsung,exynos-ppmu";
 802                 reg = <0x11ac0000 0x2000>;
 803                 clocks = <&clock CLK_PPMUCAMIF>;
 804                 clock-names = "ppmu";
 805                 status = "disabled";
 806         };
 807
 808         ppmu_lcd0: ppmu_lcd0@11e40000 {
 809                 compatible = "samsung,exynos-ppmu";
 810                 reg = <0x11e40000 0x2000>;
 811                 clocks = <&clock CLK_PPMULCD0>;
 812                 clock-names = "ppmu";
 813                 status = "disabled";
 814         };
 815
 816         ppmu_fsys: ppmu_g3d@12630000 {
 817                 compatible = "samsung,exynos-ppmu";
 818                 reg = <0x12630000 0x2000>;
 819                 status = "disabled";
 820         };
 821
 822         ppmu_image: ppmu_image@12aa0000 {
 823                 compatible = "samsung,exynos-ppmu";
 824                 reg = <0x12aa0000 0x2000>;
 825                 clocks = <&clock CLK_PPMUIMAGE>;
 826                 clock-names = "ppmu";
 827                 status = "disabled";
 828         };
 829
 830         ppmu_tv: ppmu_tv@12e40000 {
 831                 compatible = "samsung,exynos-ppmu";
 832                 reg = <0x12e40000 0x2000>;
 833                 clocks = <&clock CLK_PPMUTV>;
 834                 clock-names = "ppmu";
 835                 status = "disabled";
 836         };
 837
 838         ppmu_g3d: ppmu_g3d@13220000 {
 839                 compatible = "samsung,exynos-ppmu";
 840                 reg = <0x13220000 0x2000>;
 841                 clocks = <&clock CLK_PPMUG3D>;
 842                 clock-names = "ppmu";
 843                 status = "disabled";
 844         };
 845
 846         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 847                 compatible = "samsung,exynos-ppmu";
 848                 reg = <0x13660000 0x2000>;
 849                 clocks = <&clock CLK_PPMUMFC_L>;
 850                 clock-names = "ppmu";
 851                 status = "disabled";
 852         };
 853
 854         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 855                 compatible = "samsung,exynos-ppmu";
 856                 reg = <0x13670000 0x2000>;
 857                 clocks = <&clock CLK_PPMUMFC_R>;
 858                 clock-names = "ppmu";
 859                 status = "disabled";
 860         };
 861
 862         sysmmu_mfc_l: sysmmu@13620000 {
 863                 compatible = "samsung,exynos-sysmmu";
 864                 reg = <0x13620000 0x1000>;
 865                 interrupt-parent = <&combiner>;
 866                 interrupts = <5 5>;
 867                 clock-names = "sysmmu", "master";
 868                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 869                 power-domains = <&pd_mfc>;
 870                 #iommu-cells = <0>;
 871         };
 872
 873         sysmmu_mfc_r: sysmmu@13630000 {
 874                 compatible = "samsung,exynos-sysmmu";
 875                 reg = <0x13630000 0x1000>;
 876                 interrupt-parent = <&combiner>;
 877                 interrupts = <5 6>;
 878                 clock-names = "sysmmu", "master";
 879                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 880                 power-domains = <&pd_mfc>;
 881                 #iommu-cells = <0>;
 882         };
 883
 884         sysmmu_tv: sysmmu@12E20000 {
 885                 compatible = "samsung,exynos-sysmmu";
 886                 reg = <0x12E20000 0x1000>;
 887                 interrupt-parent = <&combiner>;
 888                 interrupts = <5 4>;
 889                 clock-names = "sysmmu", "master";
 890                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 891                 power-domains = <&pd_tv>;
 892                 #iommu-cells = <0>;
 893         };
 894
 895         sysmmu_fimc0: sysmmu@11A20000 {
 896                 compatible = "samsung,exynos-sysmmu";
 897                 reg = <0x11A20000 0x1000>;
 898                 interrupt-parent = <&combiner>;
 899                 interrupts = <4 2>;
 900                 clock-names = "sysmmu", "master";
 901                 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 902                 power-domains = <&pd_cam>;
 903                 #iommu-cells = <0>;
 904         };
 905
 906         sysmmu_fimc1: sysmmu@11A30000 {
 907                 compatible = "samsung,exynos-sysmmu";
 908                 reg = <0x11A30000 0x1000>;
 909                 interrupt-parent = <&combiner>;
 910                 interrupts = <4 3>;
 911                 clock-names = "sysmmu", "master";
 912                 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 913                 power-domains = <&pd_cam>;
 914                 #iommu-cells = <0>;
 915         };
 916
 917         sysmmu_fimc2: sysmmu@11A40000 {
 918                 compatible = "samsung,exynos-sysmmu";
 919                 reg = <0x11A40000 0x1000>;
 920                 interrupt-parent = <&combiner>;
 921                 interrupts = <4 4>;
 922                 clock-names = "sysmmu", "master";
 923                 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 924                 power-domains = <&pd_cam>;
 925                 #iommu-cells = <0>;
 926         };
 927
 928         sysmmu_fimc3: sysmmu@11A50000 {
 929                 compatible = "samsung,exynos-sysmmu";
 930                 reg = <0x11A50000 0x1000>;
 931                 interrupt-parent = <&combiner>;
 932                 interrupts = <4 5>;
 933                 clock-names = "sysmmu", "master";
 934                 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 935                 power-domains = <&pd_cam>;
 936                 #iommu-cells = <0>;
 937         };
 938
 939         sysmmu_jpeg: sysmmu@11A60000 {
 940                 compatible = "samsung,exynos-sysmmu";
 941                 reg = <0x11A60000 0x1000>;
 942                 interrupt-parent = <&combiner>;
 943                 interrupts = <4 6>;
 944                 clock-names = "sysmmu", "master";
 945                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 946                 power-domains = <&pd_cam>;
 947                 #iommu-cells = <0>;
 948         };
 949
 950         sysmmu_rotator: sysmmu@12A30000 {
 951                 compatible = "samsung,exynos-sysmmu";
 952                 reg = <0x12A30000 0x1000>;
 953                 interrupt-parent = <&combiner>;
 954                 interrupts = <5 0>;
 955                 clock-names = "sysmmu", "master";
 956                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 957                 power-domains = <&pd_lcd0>;
 958                 #iommu-cells = <0>;
 959         };
 960
 961         sysmmu_fimd0: sysmmu@11E20000 {
 962                 compatible = "samsung,exynos-sysmmu";
 963                 reg = <0x11E20000 0x1000>;
 964                 interrupt-parent = <&combiner>;
 965                 interrupts = <5 2>;
 966                 clock-names = "sysmmu", "master";
 967                 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
 968                 power-domains = <&pd_lcd0>;
 969                 #iommu-cells = <0>;
 970         };
 971 };