arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49                 usbdrdphy0 = &usbdrd_phy0;
  50                 usbdrdphy1 = &usbdrd_phy1;
  51         };
  52
  53         cluster_a15_opp_table: opp_table0 {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56                 opp@1800000000 {
  57                         opp-hz = /bits/ 64 <1800000000>;
  58                         opp-microvolt = <1250000>;
  59                         clock-latency-ns = <140000>;
  60                 };
  61                 opp@1700000000 {
  62                         opp-hz = /bits/ 64 <1700000000>;
  63                         opp-microvolt = <1212500>;
  64                         clock-latency-ns = <140000>;
  65                 };
  66                 opp@1600000000 {
  67                         opp-hz = /bits/ 64 <1600000000>;
  68                         opp-microvolt = <1175000>;
  69                         clock-latency-ns = <140000>;
  70                 };
  71                 opp@1500000000 {
  72                         opp-hz = /bits/ 64 <1500000000>;
  73                         opp-microvolt = <1137500>;
  74                         clock-latency-ns = <140000>;
  75                 };
  76                 opp@1400000000 {
  77                         opp-hz = /bits/ 64 <1400000000>;
  78                         opp-microvolt = <1112500>;
  79                         clock-latency-ns = <140000>;
  80                 };
  81                 opp@1300000000 {
  82                         opp-hz = /bits/ 64 <1300000000>;
  83                         opp-microvolt = <1062500>;
  84                         clock-latency-ns = <140000>;
  85                 };
  86                 opp@1200000000 {
  87                         opp-hz = /bits/ 64 <1200000000>;
  88                         opp-microvolt = <1037500>;
  89                         clock-latency-ns = <140000>;
  90                 };
  91                 opp@1100000000 {
  92                         opp-hz = /bits/ 64 <1100000000>;
  93                         opp-microvolt = <1012500>;
  94                         clock-latency-ns = <140000>;
  95                 };
  96                 opp@1000000000 {
  97                         opp-hz = /bits/ 64 <1000000000>;
  98                         opp-microvolt = < 987500>;
  99                         clock-latency-ns = <140000>;
 100                 };
 101                 opp@900000000 {
 102                         opp-hz = /bits/ 64 <900000000>;
 103                         opp-microvolt = < 962500>;
 104                         clock-latency-ns = <140000>;
 105                 };
 106                 opp@800000000 {
 107                         opp-hz = /bits/ 64 <800000000>;
 108                         opp-microvolt = < 937500>;
 109                         clock-latency-ns = <140000>;
 110                 };
 111                 opp@700000000 {
 112                         opp-hz = /bits/ 64 <700000000>;
 113                         opp-microvolt = < 912500>;
 114                         clock-latency-ns = <140000>;
 115                 };
 116         };
 117
 118         cluster_a7_opp_table: opp_table1 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121                 opp@1300000000 {
 122                         opp-hz = /bits/ 64 <1300000000>;
 123                         opp-microvolt = <1275000>;
 124                         clock-latency-ns = <140000>;
 125                 };
 126                 opp@1200000000 {
 127                         opp-hz = /bits/ 64 <1200000000>;
 128                         opp-microvolt = <1212500>;
 129                         clock-latency-ns = <140000>;
 130                 };
 131                 opp@1100000000 {
 132                         opp-hz = /bits/ 64 <1100000000>;
 133                         opp-microvolt = <1162500>;
 134                         clock-latency-ns = <140000>;
 135                 };
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         opp-microvolt = <1112500>;
 139                         clock-latency-ns = <140000>;
 140                 };
 141                 opp@900000000 {
 142                         opp-hz = /bits/ 64 <900000000>;
 143                         opp-microvolt = <1062500>;
 144                         clock-latency-ns = <140000>;
 145                 };
 146                 opp@800000000 {
 147                         opp-hz = /bits/ 64 <800000000>;
 148                         opp-microvolt = <1025000>;
 149                         clock-latency-ns = <140000>;
 150                 };
 151                 opp@700000000 {
 152                         opp-hz = /bits/ 64 <700000000>;
 153                         opp-microvolt = <975000>;
 154                         clock-latency-ns = <140000>;
 155                 };
 156                 opp@600000000 {
 157                         opp-hz = /bits/ 64 <600000000>;
 158                         opp-microvolt = <937500>;
 159                         clock-latency-ns = <140000>;
 160                 };
 161         };
 162
 163         /*
 164          * The 'cpus' node is not present here but instead it is provided
 165          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 166          */
 167
 168         cci: cci@10d20000 {
 169                 compatible = "arm,cci-400";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 reg = <0x10d20000 0x1000>;
 173                 ranges = <0x0 0x10d20000 0x6000>;
 174
 175                 cci_control0: slave-if@4000 {
 176                         compatible = "arm,cci-400-ctrl-if";
 177                         interface-type = "ace";
 178                         reg = <0x4000 0x1000>;
 179                 };
 180                 cci_control1: slave-if@5000 {
 181                         compatible = "arm,cci-400-ctrl-if";
 182                         interface-type = "ace";
 183                         reg = <0x5000 0x1000>;
 184                 };
 185         };
 186
 187         sysram@02020000 {
 188                 compatible = "mmio-sram";
 189                 reg = <0x02020000 0x54000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges = <0 0x02020000 0x54000>;
 193
 194                 smp-sysram@0 {
 195                         compatible = "samsung,exynos4210-sysram";
 196                         reg = <0x0 0x1000>;
 197                 };
 198
 199                 smp-sysram@53000 {
 200                         compatible = "samsung,exynos4210-sysram-ns";
 201                         reg = <0x53000 0x1000>;
 202                 };
 203         };
 204
 205         clock: clock-controller@10010000 {
 206                 compatible = "samsung,exynos5420-clock";
 207                 reg = <0x10010000 0x30000>;
 208                 #clock-cells = <1>;
 209         };
 210
 211         clock_audss: audss-clock-controller@3810000 {
 212                 compatible = "samsung,exynos5420-audss-clock";
 213                 reg = <0x03810000 0x0C>;
 214                 #clock-cells = <1>;
 215                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 216                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 217                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 218         };
 219
 220         mfc: codec@11000000 {
 221                 compatible = "samsung,mfc-v7";
 222                 reg = <0x11000000 0x10000>;
 223                 interrupts = <0 96 0>;
 224                 clocks = <&clock CLK_MFC>;
 225                 clock-names = "mfc";
 226                 power-domains = <&mfc_pd>;
 227                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 228                 iommu-names = "left", "right";
 229         };
 230
 231         mmc_0: mmc@12200000 {
 232                 compatible = "samsung,exynos5420-dw-mshc-smu";
 233                 interrupts = <0 75 0>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x12200000 0x2000>;
 237                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 238                 clock-names = "biu", "ciu";
 239                 fifo-depth = <0x40>;
 240                 status = "disabled";
 241         };
 242
 243         mmc_1: mmc@12210000 {
 244                 compatible = "samsung,exynos5420-dw-mshc-smu";
 245                 interrupts = <0 76 0>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 reg = <0x12210000 0x2000>;
 249                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 250                 clock-names = "biu", "ciu";
 251                 fifo-depth = <0x40>;
 252                 status = "disabled";
 253         };
 254
 255         mmc_2: mmc@12220000 {
 256                 compatible = "samsung,exynos5420-dw-mshc";
 257                 interrupts = <0 77 0>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 reg = <0x12220000 0x1000>;
 261                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 262                 clock-names = "biu", "ciu";
 263                 fifo-depth = <0x40>;
 264                 status = "disabled";
 265         };
 266
 267         mct: mct@101C0000 {
 268                 compatible = "samsung,exynos4210-mct";
 269                 reg = <0x101C0000 0x800>;
 270                 interrupt-controller;
 271                 #interrupt-cells = <1>;
 272                 interrupt-parent = <&mct_map>;
 273                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 274                                 <8>, <9>, <10>, <11>;
 275                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 276                 clock-names = "fin_pll", "mct";
 277
 278                 mct_map: mct-map {
 279                         #interrupt-cells = <1>;
 280                         #address-cells = <0>;
 281                         #size-cells = <0>;
 282                         interrupt-map = <0 &combiner 23 3>,
 283                                         <1 &combiner 23 4>,
 284                                         <2 &combiner 25 2>,
 285                                         <3 &combiner 25 3>,
 286                                         <4 &gic 0 120 0>,
 287                                         <5 &gic 0 121 0>,
 288                                         <6 &gic 0 122 0>,
 289                                         <7 &gic 0 123 0>,
 290                                         <8 &gic 0 128 0>,
 291                                         <9 &gic 0 129 0>,
 292                                         <10 &gic 0 130 0>,
 293                                         <11 &gic 0 131 0>;
 294                 };
 295         };
 296
 297         gsc_pd: power-domain@10044000 {
 298                 compatible = "samsung,exynos4210-pd";
 299                 reg = <0x10044000 0x20>;
 300                 #power-domain-cells = <0>;
 301                 clocks = <&clock CLK_FIN_PLL>,
 302                          <&clock CLK_MOUT_USER_ACLK300_GSCL>,
 303                          <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 304                 clock-names = "oscclk", "clk0", "asb0", "asb1";
 305         };
 306
 307         isp_pd: power-domain@10044020 {
 308                 compatible = "samsung,exynos4210-pd";
 309                 reg = <0x10044020 0x20>;
 310                 #power-domain-cells = <0>;
 311         };
 312
 313         mfc_pd: power-domain@10044060 {
 314                 compatible = "samsung,exynos4210-pd";
 315                 reg = <0x10044060 0x20>;
 316                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 317                 clock-names = "oscclk", "clk0";
 318                 #power-domain-cells = <0>;
 319         };
 320
 321         msc_pd: power-domain@10044120 {
 322                 compatible = "samsung,exynos4210-pd";
 323                 reg = <0x10044120 0x20>;
 324                 #power-domain-cells = <0>;
 325         };
 326
 327         disp_pd: power-domain@100440C0 {
 328                 compatible = "samsung,exynos4210-pd";
 329                 reg = <0x100440C0 0x20>;
 330                 #power-domain-cells = <0>;
 331                 clocks = <&clock CLK_FIN_PLL>,
 332                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 333                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 334                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 335                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 336                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 337         };
 338
 339         pinctrl_0: pinctrl@13400000 {
 340                 compatible = "samsung,exynos5420-pinctrl";
 341                 reg = <0x13400000 0x1000>;
 342                 interrupts = <0 45 0>;
 343
 344                 wakeup-interrupt-controller {
 345                         compatible = "samsung,exynos4210-wakeup-eint";
 346                         interrupt-parent = <&gic>;
 347                         interrupts = <0 32 0>;
 348                 };
 349         };
 350
 351         pinctrl_1: pinctrl@13410000 {
 352                 compatible = "samsung,exynos5420-pinctrl";
 353                 reg = <0x13410000 0x1000>;
 354                 interrupts = <0 78 0>;
 355         };
 356
 357         pinctrl_2: pinctrl@14000000 {
 358                 compatible = "samsung,exynos5420-pinctrl";
 359                 reg = <0x14000000 0x1000>;
 360                 interrupts = <0 46 0>;
 361         };
 362
 363         pinctrl_3: pinctrl@14010000 {
 364                 compatible = "samsung,exynos5420-pinctrl";
 365                 reg = <0x14010000 0x1000>;
 366                 interrupts = <0 50 0>;
 367         };
 368
 369         pinctrl_4: pinctrl@03860000 {
 370                 compatible = "samsung,exynos5420-pinctrl";
 371                 reg = <0x03860000 0x1000>;
 372                 interrupts = <0 47 0>;
 373         };
 374
 375         amba {
 376                 #address-cells = <1>;
 377                 #size-cells = <1>;
 378                 compatible = "simple-bus";
 379                 interrupt-parent = <&gic>;
 380                 ranges;
 381
 382                 adma: adma@03880000 {
 383                         compatible = "arm,pl330", "arm,primecell";
 384                         reg = <0x03880000 0x1000>;
 385                         interrupts = <0 110 0>;
 386                         clocks = <&clock_audss EXYNOS_ADMA>;
 387                         clock-names = "apb_pclk";
 388                         #dma-cells = <1>;
 389                         #dma-channels = <6>;
 390                         #dma-requests = <16>;
 391                 };
 392
 393                 pdma0: pdma@121A0000 {
 394                         compatible = "arm,pl330", "arm,primecell";
 395                         reg = <0x121A0000 0x1000>;
 396                         interrupts = <0 34 0>;
 397                         clocks = <&clock CLK_PDMA0>;
 398                         clock-names = "apb_pclk";
 399                         #dma-cells = <1>;
 400                         #dma-channels = <8>;
 401                         #dma-requests = <32>;
 402                 };
 403
 404                 pdma1: pdma@121B0000 {
 405                         compatible = "arm,pl330", "arm,primecell";
 406                         reg = <0x121B0000 0x1000>;
 407                         interrupts = <0 35 0>;
 408                         clocks = <&clock CLK_PDMA1>;
 409                         clock-names = "apb_pclk";
 410                         #dma-cells = <1>;
 411                         #dma-channels = <8>;
 412                         #dma-requests = <32>;
 413                 };
 414
 415                 mdma0: mdma@10800000 {
 416                         compatible = "arm,pl330", "arm,primecell";
 417                         reg = <0x10800000 0x1000>;
 418                         interrupts = <0 33 0>;
 419                         clocks = <&clock CLK_MDMA0>;
 420                         clock-names = "apb_pclk";
 421                         #dma-cells = <1>;
 422                         #dma-channels = <8>;
 423                         #dma-requests = <1>;
 424                 };
 425
 426                 mdma1: mdma@11C10000 {
 427                         compatible = "arm,pl330", "arm,primecell";
 428                         reg = <0x11C10000 0x1000>;
 429                         interrupts = <0 124 0>;
 430                         clocks = <&clock CLK_MDMA1>;
 431                         clock-names = "apb_pclk";
 432                         #dma-cells = <1>;
 433                         #dma-channels = <8>;
 434                         #dma-requests = <1>;
 435                         /*
 436                          * MDMA1 can support both secure and non-secure
 437                          * AXI transactions. When this is enabled in the kernel
 438                          * for boards that run in secure mode, we are getting
 439                          * imprecise external aborts causing the kernel to oops.
 440                          */
 441                         status = "disabled";
 442                 };
 443         };
 444
 445         i2s0: i2s@03830000 {
 446                 compatible = "samsung,exynos5420-i2s";
 447                 reg = <0x03830000 0x100>;
 448                 dmas = <&adma 0
 449                         &adma 2
 450                         &adma 1>;
 451                 dma-names = "tx", "rx", "tx-sec";
 452                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 453                         <&clock_audss EXYNOS_I2S_BUS>,
 454                         <&clock_audss EXYNOS_SCLK_I2S>;
 455                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 456                 #clock-cells = <1>;
 457                 clock-output-names = "i2s_cdclk0";
 458                 #sound-dai-cells = <1>;
 459                 samsung,idma-addr = <0x03000000>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&i2s0_bus>;
 462                 status = "disabled";
 463         };
 464
 465         i2s1: i2s@12D60000 {
 466                 compatible = "samsung,exynos5420-i2s";
 467                 reg = <0x12D60000 0x100>;
 468                 dmas = <&pdma1 12
 469                         &pdma1 11>;
 470                 dma-names = "tx", "rx";
 471                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 472                 clock-names = "iis", "i2s_opclk0";
 473                 #clock-cells = <1>;
 474                 clock-output-names = "i2s_cdclk1";
 475                 #sound-dai-cells = <1>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&i2s1_bus>;
 478                 status = "disabled";
 479         };
 480
 481         i2s2: i2s@12D70000 {
 482                 compatible = "samsung,exynos5420-i2s";
 483                 reg = <0x12D70000 0x100>;
 484                 dmas = <&pdma0 12
 485                         &pdma0 11>;
 486                 dma-names = "tx", "rx";
 487                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 488                 clock-names = "iis", "i2s_opclk0";
 489                 #clock-cells = <1>;
 490                 clock-output-names = "i2s_cdclk2";
 491                 #sound-dai-cells = <1>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&i2s2_bus>;
 494                 status = "disabled";
 495         };
 496
 497         spi_0: spi@12d20000 {
 498                 compatible = "samsung,exynos4210-spi";
 499                 reg = <0x12d20000 0x100>;
 500                 interrupts = <0 68 0>;
 501                 dmas = <&pdma0 5
 502                         &pdma0 4>;
 503                 dma-names = "tx", "rx";
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&spi0_bus>;
 508                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 509                 clock-names = "spi", "spi_busclk0";
 510                 status = "disabled";
 511         };
 512
 513         spi_1: spi@12d30000 {
 514                 compatible = "samsung,exynos4210-spi";
 515                 reg = <0x12d30000 0x100>;
 516                 interrupts = <0 69 0>;
 517                 dmas = <&pdma1 5
 518                         &pdma1 4>;
 519                 dma-names = "tx", "rx";
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&spi1_bus>;
 524                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 525                 clock-names = "spi", "spi_busclk0";
 526                 status = "disabled";
 527         };
 528
 529         spi_2: spi@12d40000 {
 530                 compatible = "samsung,exynos4210-spi";
 531                 reg = <0x12d40000 0x100>;
 532                 interrupts = <0 70 0>;
 533                 dmas = <&pdma0 7
 534                         &pdma0 6>;
 535                 dma-names = "tx", "rx";
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&spi2_bus>;
 540                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 541                 clock-names = "spi", "spi_busclk0";
 542                 status = "disabled";
 543         };
 544
 545         pwm: pwm@12dd0000 {
 546                 compatible = "samsung,exynos4210-pwm";
 547                 reg = <0x12dd0000 0x100>;
 548                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 549                 #pwm-cells = <3>;
 550                 clocks = <&clock CLK_PWM>;
 551                 clock-names = "timers";
 552         };
 553
 554         dp_phy: dp-video-phy {
 555                 compatible = "samsung,exynos5420-dp-video-phy";
 556                 samsung,pmu-syscon = <&pmu_system_controller>;
 557                 #phy-cells = <0>;
 558         };
 559
 560         mipi_phy: mipi-video-phy {
 561                 compatible = "samsung,s5pv210-mipi-video-phy";
 562                 syscon = <&pmu_system_controller>;
 563                 #phy-cells = <1>;
 564         };
 565
 566         dsi@14500000 {
 567                 compatible = "samsung,exynos5410-mipi-dsi";
 568                 reg = <0x14500000 0x10000>;
 569                 interrupts = <0 82 0>;
 570                 phys = <&mipi_phy 1>;
 571                 phy-names = "dsim";
 572                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 573                 clock-names = "bus_clk", "pll_clk";
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         adc: adc@12D10000 {
 580                 compatible = "samsung,exynos-adc-v2";
 581                 reg = <0x12D10000 0x100>;
 582                 interrupts = <0 106 0>;
 583                 clocks = <&clock CLK_TSADC>;
 584                 clock-names = "adc";
 585                 #io-channel-cells = <1>;
 586                 io-channel-ranges;
 587                 samsung,syscon-phandle = <&pmu_system_controller>;
 588                 status = "disabled";
 589         };
 590
 591         i2c_0: i2c@12C60000 {
 592                 compatible = "samsung,s3c2440-i2c";
 593                 reg = <0x12C60000 0x100>;
 594                 interrupts = <0 56 0>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 clocks = <&clock CLK_I2C0>;
 598                 clock-names = "i2c";
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&i2c0_bus>;
 601                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 602                 status = "disabled";
 603         };
 604
 605         i2c_1: i2c@12C70000 {
 606                 compatible = "samsung,s3c2440-i2c";
 607                 reg = <0x12C70000 0x100>;
 608                 interrupts = <0 57 0>;
 609                 #address-cells = <1>;
 610                 #size-cells = <0>;
 611                 clocks = <&clock CLK_I2C1>;
 612                 clock-names = "i2c";
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&i2c1_bus>;
 615                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 616                 status = "disabled";
 617         };
 618
 619         i2c_2: i2c@12C80000 {
 620                 compatible = "samsung,s3c2440-i2c";
 621                 reg = <0x12C80000 0x100>;
 622                 interrupts = <0 58 0>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 clocks = <&clock CLK_I2C2>;
 626                 clock-names = "i2c";
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&i2c2_bus>;
 629                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 630                 status = "disabled";
 631         };
 632
 633         i2c_3: i2c@12C90000 {
 634                 compatible = "samsung,s3c2440-i2c";
 635                 reg = <0x12C90000 0x100>;
 636                 interrupts = <0 59 0>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 clocks = <&clock CLK_I2C3>;
 640                 clock-names = "i2c";
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&i2c3_bus>;
 643                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 644                 status = "disabled";
 645         };
 646
 647         hsi2c_4: i2c@12CA0000 {
 648                 compatible = "samsung,exynos5-hsi2c";
 649                 reg = <0x12CA0000 0x1000>;
 650                 interrupts = <0 60 0>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&i2c4_hs_bus>;
 655                 clocks = <&clock CLK_USI0>;
 656                 clock-names = "hsi2c";
 657                 status = "disabled";
 658         };
 659
 660         hsi2c_5: i2c@12CB0000 {
 661                 compatible = "samsung,exynos5-hsi2c";
 662                 reg = <0x12CB0000 0x1000>;
 663                 interrupts = <0 61 0>;
 664                 #address-cells = <1>;
 665                 #size-cells = <0>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&i2c5_hs_bus>;
 668                 clocks = <&clock CLK_USI1>;
 669                 clock-names = "hsi2c";
 670                 status = "disabled";
 671         };
 672
 673         hsi2c_6: i2c@12CC0000 {
 674                 compatible = "samsung,exynos5-hsi2c";
 675                 reg = <0x12CC0000 0x1000>;
 676                 interrupts = <0 62 0>;
 677                 #address-cells = <1>;
 678                 #size-cells = <0>;
 679                 pinctrl-names = "default";
 680                 pinctrl-0 = <&i2c6_hs_bus>;
 681                 clocks = <&clock CLK_USI2>;
 682                 clock-names = "hsi2c";
 683                 status = "disabled";
 684         };
 685
 686         hsi2c_7: i2c@12CD0000 {
 687                 compatible = "samsung,exynos5-hsi2c";
 688                 reg = <0x12CD0000 0x1000>;
 689                 interrupts = <0 63 0>;
 690                 #address-cells = <1>;
 691                 #size-cells = <0>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&i2c7_hs_bus>;
 694                 clocks = <&clock CLK_USI3>;
 695                 clock-names = "hsi2c";
 696                 status = "disabled";
 697         };
 698
 699         hsi2c_8: i2c@12E00000 {
 700                 compatible = "samsung,exynos5-hsi2c";
 701                 reg = <0x12E00000 0x1000>;
 702                 interrupts = <0 87 0>;
 703                 #address-cells = <1>;
 704                 #size-cells = <0>;
 705                 pinctrl-names = "default";
 706                 pinctrl-0 = <&i2c8_hs_bus>;
 707                 clocks = <&clock CLK_USI4>;
 708                 clock-names = "hsi2c";
 709                 status = "disabled";
 710         };
 711
 712         hsi2c_9: i2c@12E10000 {
 713                 compatible = "samsung,exynos5-hsi2c";
 714                 reg = <0x12E10000 0x1000>;
 715                 interrupts = <0 88 0>;
 716                 #address-cells = <1>;
 717                 #size-cells = <0>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&i2c9_hs_bus>;
 720                 clocks = <&clock CLK_USI5>;
 721                 clock-names = "hsi2c";
 722                 status = "disabled";
 723         };
 724
 725         hsi2c_10: i2c@12E20000 {
 726                 compatible = "samsung,exynos5-hsi2c";
 727                 reg = <0x12E20000 0x1000>;
 728                 interrupts = <0 203 0>;
 729                 #address-cells = <1>;
 730                 #size-cells = <0>;
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&i2c10_hs_bus>;
 733                 clocks = <&clock CLK_USI6>;
 734                 clock-names = "hsi2c";
 735                 status = "disabled";
 736         };
 737
 738         hdmi: hdmi@14530000 {
 739                 compatible = "samsung,exynos5420-hdmi";
 740                 reg = <0x14530000 0x70000>;
 741                 interrupts = <0 95 0>;
 742                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 743                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 744                          <&clock CLK_MOUT_HDMI>;
 745                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 746                         "sclk_hdmiphy", "mout_hdmi";
 747                 phy = <&hdmiphy>;
 748                 samsung,syscon-phandle = <&pmu_system_controller>;
 749                 status = "disabled";
 750                 power-domains = <&disp_pd>;
 751         };
 752
 753         hdmiphy: hdmiphy@145D0000 {
 754                 reg = <0x145D0000 0x20>;
 755         };
 756
 757         mixer: mixer@14450000 {
 758                 compatible = "samsung,exynos5420-mixer";
 759                 reg = <0x14450000 0x10000>;
 760                 interrupts = <0 94 0>;
 761                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 762                          <&clock CLK_SCLK_HDMI>;
 763                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 764                 power-domains = <&disp_pd>;
 765                 iommus = <&sysmmu_tv>;
 766         };
 767
 768         rotator: rotator@11C00000 {
 769                 compatible = "samsung,exynos5250-rotator";
 770                 reg = <0x11C00000 0x64>;
 771                 interrupts = <0 84 0>;
 772                 clocks = <&clock CLK_ROTATOR>;
 773                 clock-names = "rotator";
 774                 iommus = <&sysmmu_rotator>;
 775         };
 776
 777         gsc_0: video-scaler@13e00000 {
 778                 compatible = "samsung,exynos5-gsc";
 779                 reg = <0x13e00000 0x1000>;
 780                 interrupts = <0 85 0>;
 781                 clocks = <&clock CLK_GSCL0>;
 782                 clock-names = "gscl";
 783                 power-domains = <&gsc_pd>;
 784                 iommus = <&sysmmu_gscl0>;
 785         };
 786
 787         gsc_1: video-scaler@13e10000 {
 788                 compatible = "samsung,exynos5-gsc";
 789                 reg = <0x13e10000 0x1000>;
 790                 interrupts = <0 86 0>;
 791                 clocks = <&clock CLK_GSCL1>;
 792                 clock-names = "gscl";
 793                 power-domains = <&gsc_pd>;
 794                 iommus = <&sysmmu_gscl1>;
 795         };
 796
 797         jpeg_0: jpeg@11F50000 {
 798                 compatible = "samsung,exynos5420-jpeg";
 799                 reg = <0x11F50000 0x1000>;
 800                 interrupts = <0 89 0>;
 801                 clock-names = "jpeg";
 802                 clocks = <&clock CLK_JPEG>;
 803                 iommus = <&sysmmu_jpeg0>;
 804         };
 805
 806         jpeg_1: jpeg@11F60000 {
 807                 compatible = "samsung,exynos5420-jpeg";
 808                 reg = <0x11F60000 0x1000>;
 809                 interrupts = <0 168 0>;
 810                 clock-names = "jpeg";
 811                 clocks = <&clock CLK_JPEG2>;
 812                 iommus = <&sysmmu_jpeg1>;
 813         };
 814
 815         pmu_system_controller: system-controller@10040000 {
 816                 compatible = "samsung,exynos5420-pmu", "syscon";
 817                 reg = <0x10040000 0x5000>;
 818                 clock-names = "clkout16";
 819                 clocks = <&clock CLK_FIN_PLL>;
 820                 #clock-cells = <1>;
 821                 interrupt-controller;
 822                 #interrupt-cells = <3>;
 823                 interrupt-parent = <&gic>;
 824         };
 825
 826         sysreg_system_controller: syscon@10050000 {
 827                 compatible = "samsung,exynos5-sysreg", "syscon";
 828                 reg = <0x10050000 0x5000>;
 829         };
 830
 831         tmu_cpu0: tmu@10060000 {
 832                 compatible = "samsung,exynos5420-tmu";
 833                 reg = <0x10060000 0x100>;
 834                 interrupts = <0 65 0>;
 835                 clocks = <&clock CLK_TMU>;
 836                 clock-names = "tmu_apbif";
 837                 #include "exynos4412-tmu-sensor-conf.dtsi"
 838         };
 839
 840         tmu_cpu1: tmu@10064000 {
 841                 compatible = "samsung,exynos5420-tmu";
 842                 reg = <0x10064000 0x100>;
 843                 interrupts = <0 183 0>;
 844                 clocks = <&clock CLK_TMU>;
 845                 clock-names = "tmu_apbif";
 846                 #include "exynos4412-tmu-sensor-conf.dtsi"
 847         };
 848
 849         tmu_cpu2: tmu@10068000 {
 850                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 851                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 852                 interrupts = <0 184 0>;
 853                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 854                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 855                 #include "exynos4412-tmu-sensor-conf.dtsi"
 856         };
 857
 858         tmu_cpu3: tmu@1006c000 {
 859                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 860                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 861                 interrupts = <0 185 0>;
 862                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 863                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 864                 #include "exynos4412-tmu-sensor-conf.dtsi"
 865         };
 866
 867         tmu_gpu: tmu@100a0000 {
 868                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 869                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 870                 interrupts = <0 215 0>;
 871                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 872                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 873                 #include "exynos4412-tmu-sensor-conf.dtsi"
 874         };
 875
 876         thermal-zones {
 877                 cpu0_thermal: cpu0-thermal {
 878                         thermal-sensors = <&tmu_cpu0>;
 879                         #include "exynos5420-trip-points.dtsi"
 880                 };
 881                 cpu1_thermal: cpu1-thermal {
 882                        thermal-sensors = <&tmu_cpu1>;
 883                        #include "exynos5420-trip-points.dtsi"
 884                 };
 885                 cpu2_thermal: cpu2-thermal {
 886                        thermal-sensors = <&tmu_cpu2>;
 887                        #include "exynos5420-trip-points.dtsi"
 888                 };
 889                 cpu3_thermal: cpu3-thermal {
 890                        thermal-sensors = <&tmu_cpu3>;
 891                        #include "exynos5420-trip-points.dtsi"
 892                 };
 893                 gpu_thermal: gpu-thermal {
 894                        thermal-sensors = <&tmu_gpu>;
 895                        #include "exynos5420-trip-points.dtsi"
 896                 };
 897         };
 898
 899         watchdog: watchdog@101D0000 {
 900                 compatible = "samsung,exynos5420-wdt";
 901                 reg = <0x101D0000 0x100>;
 902                 interrupts = <0 42 0>;
 903                 clocks = <&clock CLK_WDT>;
 904                 clock-names = "watchdog";
 905                 samsung,syscon-phandle = <&pmu_system_controller>;
 906         };
 907
 908         sss: sss@10830000 {
 909                 compatible = "samsung,exynos4210-secss";
 910                 reg = <0x10830000 0x300>;
 911                 interrupts = <0 112 0>;
 912                 clocks = <&clock CLK_SSS>;
 913                 clock-names = "secss";
 914         };
 915
 916         usbdrd3_0: usb3-0 {
 917                 compatible = "samsung,exynos5250-dwusb3";
 918                 clocks = <&clock CLK_USBD300>;
 919                 clock-names = "usbdrd30";
 920                 #address-cells = <1>;
 921                 #size-cells = <1>;
 922                 ranges;
 923
 924                 usbdrd_dwc3_0: dwc3@12000000 {
 925                         compatible = "snps,dwc3";
 926                         reg = <0x12000000 0x10000>;
 927                         interrupts = <0 72 0>;
 928                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 929                         phy-names = "usb2-phy", "usb3-phy";
 930                 };
 931         };
 932
 933         usbdrd_phy0: phy@12100000 {
 934                 compatible = "samsung,exynos5420-usbdrd-phy";
 935                 reg = <0x12100000 0x100>;
 936                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 937                 clock-names = "phy", "ref";
 938                 samsung,pmu-syscon = <&pmu_system_controller>;
 939                 #phy-cells = <1>;
 940         };
 941
 942         usbdrd3_1: usb3-1 {
 943                 compatible = "samsung,exynos5250-dwusb3";
 944                 clocks = <&clock CLK_USBD301>;
 945                 clock-names = "usbdrd30";
 946                 #address-cells = <1>;
 947                 #size-cells = <1>;
 948                 ranges;
 949
 950                 usbdrd_dwc3_1: dwc3@12400000 {
 951                         compatible = "snps,dwc3";
 952                         reg = <0x12400000 0x10000>;
 953                         interrupts = <0 73 0>;
 954                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 955                         phy-names = "usb2-phy", "usb3-phy";
 956                 };
 957         };
 958
 959         usbdrd_phy1: phy@12500000 {
 960                 compatible = "samsung,exynos5420-usbdrd-phy";
 961                 reg = <0x12500000 0x100>;
 962                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 963                 clock-names = "phy", "ref";
 964                 samsung,pmu-syscon = <&pmu_system_controller>;
 965                 #phy-cells = <1>;
 966         };
 967
 968         usbhost2: usb@12110000 {
 969                 compatible = "samsung,exynos4210-ehci";
 970                 reg = <0x12110000 0x100>;
 971                 interrupts = <0 71 0>;
 972
 973                 clocks = <&clock CLK_USBH20>;
 974                 clock-names = "usbhost";
 975                 #address-cells = <1>;
 976                 #size-cells = <0>;
 977                 port@0 {
 978                         reg = <0>;
 979                         phys = <&usb2_phy 1>;
 980                 };
 981         };
 982
 983         usbhost1: usb@12120000 {
 984                 compatible = "samsung,exynos4210-ohci";
 985                 reg = <0x12120000 0x100>;
 986                 interrupts = <0 71 0>;
 987
 988                 clocks = <&clock CLK_USBH20>;
 989                 clock-names = "usbhost";
 990                 #address-cells = <1>;
 991                 #size-cells = <0>;
 992                 port@0 {
 993                         reg = <0>;
 994                         phys = <&usb2_phy 1>;
 995                 };
 996         };
 997
 998         usb2_phy: phy@12130000 {
 999                 compatible = "samsung,exynos5250-usb2-phy";
1000                 reg = <0x12130000 0x100>;
1001                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1002                 clock-names = "phy", "ref";
1003                 #phy-cells = <1>;
1004                 samsung,sysreg-phandle = <&sysreg_system_controller>;
1005                 samsung,pmureg-phandle = <&pmu_system_controller>;
1006         };
1007
1008         sysmmu_g2dr: sysmmu@0x10A60000 {
1009                 compatible = "samsung,exynos-sysmmu";
1010                 reg = <0x10A60000 0x1000>;
1011                 interrupt-parent = <&combiner>;
1012                 interrupts = <24 5>;
1013                 clock-names = "sysmmu", "master";
1014                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1015                 #iommu-cells = <0>;
1016         };
1017
1018         sysmmu_g2dw: sysmmu@0x10A70000 {
1019                 compatible = "samsung,exynos-sysmmu";
1020                 reg = <0x10A70000 0x1000>;
1021                 interrupt-parent = <&combiner>;
1022                 interrupts = <22 2>;
1023                 clock-names = "sysmmu", "master";
1024                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1025                 #iommu-cells = <0>;
1026         };
1027
1028         sysmmu_tv: sysmmu@0x14650000 {
1029                 compatible = "samsung,exynos-sysmmu";
1030                 reg = <0x14650000 0x1000>;
1031                 interrupt-parent = <&combiner>;
1032                 interrupts = <7 4>;
1033                 clock-names = "sysmmu", "master";
1034                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1035                 power-domains = <&disp_pd>;
1036                 #iommu-cells = <0>;
1037         };
1038
1039         sysmmu_gscl0: sysmmu@0x13E80000 {
1040                 compatible = "samsung,exynos-sysmmu";
1041                 reg = <0x13E80000 0x1000>;
1042                 interrupt-parent = <&combiner>;
1043                 interrupts = <2 0>;
1044                 clock-names = "sysmmu", "master";
1045                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1046                 power-domains = <&gsc_pd>;
1047                 #iommu-cells = <0>;
1048         };
1049
1050         sysmmu_gscl1: sysmmu@0x13E90000 {
1051                 compatible = "samsung,exynos-sysmmu";
1052                 reg = <0x13E90000 0x1000>;
1053                 interrupt-parent = <&combiner>;
1054                 interrupts = <2 2>;
1055                 clock-names = "sysmmu", "master";
1056                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1057                 power-domains = <&gsc_pd>;
1058                 #iommu-cells = <0>;
1059         };
1060
1061         sysmmu_scaler0r: sysmmu@0x12880000 {
1062                 compatible = "samsung,exynos-sysmmu";
1063                 reg = <0x12880000 0x1000>;
1064                 interrupt-parent = <&combiner>;
1065                 interrupts = <22 4>;
1066                 clock-names = "sysmmu", "master";
1067                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1068                 #iommu-cells = <0>;
1069         };
1070
1071         sysmmu_scaler1r: sysmmu@0x12890000 {
1072                 compatible = "samsung,exynos-sysmmu";
1073                 reg = <0x12890000 0x1000>;
1074                 interrupts = <0 186 0>;
1075                 clock-names = "sysmmu", "master";
1076                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1077                 #iommu-cells = <0>;
1078         };
1079
1080         sysmmu_scaler2r: sysmmu@0x128A0000 {
1081                 compatible = "samsung,exynos-sysmmu";
1082                 reg = <0x128A0000 0x1000>;
1083                 interrupts = <0 188 0>;
1084                 clock-names = "sysmmu", "master";
1085                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1086                 #iommu-cells = <0>;
1087         };
1088
1089         sysmmu_scaler0w: sysmmu@0x128C0000 {
1090                 compatible = "samsung,exynos-sysmmu";
1091                 reg = <0x128C0000 0x1000>;
1092                 interrupt-parent = <&combiner>;
1093                 interrupts = <27 2>;
1094                 clock-names = "sysmmu", "master";
1095                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1096                 #iommu-cells = <0>;
1097         };
1098
1099         sysmmu_scaler1w: sysmmu@0x128D0000 {
1100                 compatible = "samsung,exynos-sysmmu";
1101                 reg = <0x128D0000 0x1000>;
1102                 interrupt-parent = <&combiner>;
1103                 interrupts = <22 6>;
1104                 clock-names = "sysmmu", "master";
1105                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1106                 #iommu-cells = <0>;
1107         };
1108
1109         sysmmu_scaler2w: sysmmu@0x128E0000 {
1110                 compatible = "samsung,exynos-sysmmu";
1111                 reg = <0x128E0000 0x1000>;
1112                 interrupt-parent = <&combiner>;
1113                 interrupts = <19 6>;
1114                 clock-names = "sysmmu", "master";
1115                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1116                 #iommu-cells = <0>;
1117         };
1118
1119         sysmmu_rotator: sysmmu@0x11D40000 {
1120                 compatible = "samsung,exynos-sysmmu";
1121                 reg = <0x11D40000 0x1000>;
1122                 interrupt-parent = <&combiner>;
1123                 interrupts = <4 0>;
1124                 clock-names = "sysmmu", "master";
1125                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1126                 #iommu-cells = <0>;
1127         };
1128
1129         sysmmu_jpeg0: sysmmu@0x11F10000 {
1130                 compatible = "samsung,exynos-sysmmu";
1131                 reg = <0x11F10000 0x1000>;
1132                 interrupt-parent = <&combiner>;
1133                 interrupts = <4 2>;
1134                 clock-names = "sysmmu", "master";
1135                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1136                 #iommu-cells = <0>;
1137         };
1138
1139         sysmmu_jpeg1: sysmmu@0x11F20000 {
1140                 compatible = "samsung,exynos-sysmmu";
1141                 reg = <0x11F20000 0x1000>;
1142                 interrupts = <0 169 0>;
1143                 clock-names = "sysmmu", "master";
1144                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1145                 #iommu-cells = <0>;
1146         };
1147
1148         sysmmu_mfc_l: sysmmu@0x11200000 {
1149                 compatible = "samsung,exynos-sysmmu";
1150                 reg = <0x11200000 0x1000>;
1151                 interrupt-parent = <&combiner>;
1152                 interrupts = <6 2>;
1153                 clock-names = "sysmmu", "master";
1154                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1155                 power-domains = <&mfc_pd>;
1156                 #iommu-cells = <0>;
1157         };
1158
1159         sysmmu_mfc_r: sysmmu@0x11210000 {
1160                 compatible = "samsung,exynos-sysmmu";
1161                 reg = <0x11210000 0x1000>;
1162                 interrupt-parent = <&combiner>;
1163                 interrupts = <8 5>;
1164                 clock-names = "sysmmu", "master";
1165                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1166                 power-domains = <&mfc_pd>;
1167                 #iommu-cells = <0>;
1168         };
1169
1170         sysmmu_fimd1_0: sysmmu@0x14640000 {
1171                 compatible = "samsung,exynos-sysmmu";
1172                 reg = <0x14640000 0x1000>;
1173                 interrupt-parent = <&combiner>;
1174                 interrupts = <3 2>;
1175                 clock-names = "sysmmu", "master";
1176                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1177                 power-domains = <&disp_pd>;
1178                 #iommu-cells = <0>;
1179         };
1180
1181         sysmmu_fimd1_1: sysmmu@0x14680000 {
1182                 compatible = "samsung,exynos-sysmmu";
1183                 reg = <0x14680000 0x1000>;
1184                 interrupt-parent = <&combiner>;
1185                 interrupts = <3 0>;
1186                 clock-names = "sysmmu", "master";
1187                 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1188                 power-domains = <&disp_pd>;
1189                 #iommu-cells = <0>;
1190         };
1191 };
1192
1193 &dp {
1194         clocks = <&clock CLK_DP1>;
1195         clock-names = "dp";
1196         phys = <&dp_phy>;
1197         phy-names = "dp";
1198         power-domains = <&disp_pd>;
1199 };
1200
1201 &fimd {
1202         compatible = "samsung,exynos5420-fimd";
1203         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1204         clock-names = "sclk_fimd", "fimd";
1205         power-domains = <&disp_pd>;
1206         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1207         iommu-names = "m0", "m1";
1208 };
1209
1210 &rtc {
1211         clocks = <&clock CLK_RTC>;
1212         clock-names = "rtc";
1213         interrupt-parent = <&pmu_system_controller>;
1214         status = "disabled";
1215 };
1216
1217 &serial_0 {
1218         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1219         clock-names = "uart", "clk_uart_baud0";
1220 };
1221
1222 &serial_1 {
1223         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1224         clock-names = "uart", "clk_uart_baud0";
1225 };
1226
1227 &serial_2 {
1228         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1229         clock-names = "uart", "clk_uart_baud0";
1230 };
1231
1232 &serial_3 {
1233         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1234         clock-names = "uart", "clk_uart_baud0";
1235 };
1236
1237 #include "exynos5420-pinctrl.dtsi"