arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 ipu1 = &ipu2;
  18                 spi4 = &ecspi5;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         reg = <0>;
  29                         next-level-cache = <&L2>;
  30                         operating-points = <
  31                                 /* kHz    uV */
  32                                 1200000 1275000
  33                                 996000  1250000
  34                                 852000  1250000
  35                                 792000  1175000
  36                                 396000  975000
  37                         >;
  38                         fsl,soc-operating-points = <
  39                                 /* ARM kHz  SOC-PU uV */
  40                                 1200000 1275000
  41                                 996000  1250000
  42                                 852000  1250000
  43                                 792000  1175000
  44                                 396000  1175000
  45                         >;
  46                         clock-latency = <61036>; /* two CLK32 periods */
  47                         clocks = <&clks IMX6QDL_CLK_ARM>,
  48                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  49                                  <&clks IMX6QDL_CLK_STEP>,
  50                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  51                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  52                         clock-names = "arm", "pll2_pfd2_396m", "step",
  53                                       "pll1_sw", "pll1_sys";
  54                         arm-supply = <&reg_arm>;
  55                         pu-supply = <&reg_pu>;
  56                         soc-supply = <&reg_soc>;
  57                 };
  58
  59                 cpu@1 {
  60                         compatible = "arm,cortex-a9";
  61                         device_type = "cpu";
  62                         reg = <1>;
  63                         next-level-cache = <&L2>;
  64                 };
  65
  66                 cpu@2 {
  67                         compatible = "arm,cortex-a9";
  68                         device_type = "cpu";
  69                         reg = <2>;
  70                         next-level-cache = <&L2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a9";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                 };
  79         };
  80
  81         soc {
  82                 ocram: sram@00900000 {
  83                         compatible = "mmio-sram";
  84                         reg = <0x00900000 0x40000>;
  85                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  86                 };
  87
  88                 aips-bus@02000000 { /* AIPS1 */
  89                         spba-bus@02000000 {
  90                                 ecspi5: ecspi@02018000 {
  91                                         #address-cells = <1>;
  92                                         #size-cells = <0>;
  93                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
  94                                         reg = <0x02018000 0x4000>;
  95                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  96                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
  97                                                  <&clks IMX6Q_CLK_ECSPI5>;
  98                                         clock-names = "ipg", "per";
  99                                         dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
 100                                         dma-names = "rx", "tx";
 101                                         status = "disabled";
 102                                 };
 103                         };
 104
 105                         iomuxc: iomuxc@020e0000 {
 106                                 compatible = "fsl,imx6q-iomuxc";
 107
 108                                 ipu2 {
 109                                         pinctrl_ipu2_1: ipu2grp-1 {
 110                                                 fsl,pins = <
 111                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
 112                                                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
 113                                                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
 114                                                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
 115                                                         MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
 116                                                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
 117                                                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
 118                                                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
 119                                                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
 120                                                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
 121                                                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
 122                                                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
 123                                                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
 124                                                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
 125                                                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
 126                                                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
 127                                                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
 128                                                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
 129                                                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
 130                                                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
 131                                                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
 132                                                         MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
 133                                                         MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
 134                                                         MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
 135                                                         MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
 136                                                         MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
 137                                                         MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
 138                                                         MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
 139                                                         MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
 140                                                 >;
 141                                         };
 142                                 };
 143                         };
 144                 };
 145
 146                 sata: sata@02200000 {
 147                         compatible = "fsl,imx6q-ahci";
 148                         reg = <0x02200000 0x4000>;
 149                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&clks IMX6QDL_CLK_SATA>,
 151                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 152                                  <&clks IMX6QDL_CLK_AHB>;
 153                         clock-names = "sata", "sata_ref", "ahb";
 154                         status = "disabled";
 155                 };
 156
 157                 gpu_vg: gpu@02204000 {
 158                         compatible = "vivante,gc";
 159                         reg = <0x02204000 0x4000>;
 160                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 161                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 162                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 163                         clock-names = "bus", "core";
 164                         power-domains = <&gpc 1>;
 165                 };
 166
 167                 ipu2: ipu@02800000 {
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         compatible = "fsl,imx6q-ipu";
 171                         reg = <0x02800000 0x400000>;
 172                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 175                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 176                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 177                         clock-names = "bus", "di0", "di1";
 178                         resets = <&src 4>;
 179
 180                         ipu2_csi0: port@0 {
 181                                 reg = <0>;
 182                         };
 183
 184                         ipu2_csi1: port@1 {
 185                                 reg = <1>;
 186                         };
 187
 188                         ipu2_di0: port@2 {
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191                                 reg = <2>;
 192
 193                                 ipu2_di0_disp0: endpoint@0 {
 194                                 };
 195
 196                                 ipu2_di0_hdmi: endpoint@1 {
 197                                         remote-endpoint = <&hdmi_mux_2>;
 198                                 };
 199
 200                                 ipu2_di0_mipi: endpoint@2 {
 201                                 };
 202
 203                                 ipu2_di0_lvds0: endpoint@3 {
 204                                         remote-endpoint = <&lvds0_mux_2>;
 205                                 };
 206
 207                                 ipu2_di0_lvds1: endpoint@4 {
 208                                         remote-endpoint = <&lvds1_mux_2>;
 209                                 };
 210                         };
 211
 212                         ipu2_di1: port@3 {
 213                                 #address-cells = <1>;
 214                                 #size-cells = <0>;
 215                                 reg = <3>;
 216
 217                                 ipu2_di1_hdmi: endpoint@1 {
 218                                         remote-endpoint = <&hdmi_mux_3>;
 219                                 };
 220
 221                                 ipu2_di1_mipi: endpoint@2 {
 222                                 };
 223
 224                                 ipu2_di1_lvds0: endpoint@3 {
 225                                         remote-endpoint = <&lvds0_mux_3>;
 226                                 };
 227
 228                                 ipu2_di1_lvds1: endpoint@4 {
 229                                         remote-endpoint = <&lvds1_mux_3>;
 230                                 };
 231                         };
 232                 };
 233         };
 234
 235         display-subsystem {
 236                 compatible = "fsl,imx-display-subsystem";
 237                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 238         };
 239
 240         gpu-subsystem {
 241                 compatible = "fsl,imx-gpu-subsystem";
 242                 cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
 243         };
 244 };
 245
 246 &hdmi {
 247         compatible = "fsl,imx6q-hdmi";
 248
 249         port@2 {
 250                 reg = <2>;
 251
 252                 hdmi_mux_2: endpoint {
 253                         remote-endpoint = <&ipu2_di0_hdmi>;
 254                 };
 255         };
 256
 257         port@3 {
 258                 reg = <3>;
 259
 260                 hdmi_mux_3: endpoint {
 261                         remote-endpoint = <&ipu2_di1_hdmi>;
 262                 };
 263         };
 264 };
 265
 266 &ldb {
 267         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 268                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 269                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 270                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 271         clock-names = "di0_pll", "di1_pll",
 272                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 273                       "di0", "di1";
 274
 275         lvds-channel@0 {
 276                 port@2 {
 277                         reg = <2>;
 278
 279                         lvds0_mux_2: endpoint {
 280                                 remote-endpoint = <&ipu2_di0_lvds0>;
 281                         };
 282                 };
 283
 284                 port@3 {
 285                         reg = <3>;
 286
 287                         lvds0_mux_3: endpoint {
 288                                 remote-endpoint = <&ipu2_di1_lvds0>;
 289                         };
 290                 };
 291         };
 292
 293         lvds-channel@1 {
 294                 port@2 {
 295                         reg = <2>;
 296
 297                         lvds1_mux_2: endpoint {
 298                                 remote-endpoint = <&ipu2_di0_lvds1>;
 299                         };
 300                 };
 301
 302                 port@3 {
 303                         reg = <3>;
 304
 305                         lvds1_mux_3: endpoint {
 306                                 remote-endpoint = <&ipu2_di1_lvds1>;
 307                         };
 308                 };
 309         };
 310 };
 311
 312 &mipi_dsi {
 313         ports {
 314                 port@2 {
 315                         reg = <2>;
 316
 317                         mipi_mux_2: endpoint {
 318                                 remote-endpoint = <&ipu2_di0_mipi>;
 319                         };
 320                 };
 321
 322                 port@3 {
 323                         reg = <3>;
 324
 325                         mipi_mux_3: endpoint {
 326                                 remote-endpoint = <&ipu2_di1_mipi>;
 327                         };
 328                 };
 329         };
 330 };
 331
 332 &vpu {
 333         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 334 };