arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 ethernet0 = &fec;
  20                 can0 = &can1;
  21                 can1 = &can2;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 spi0 = &ecspi1;
  42                 spi1 = &ecspi2;
  43                 spi2 = &ecspi3;
  44                 spi3 = &ecspi4;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         intc: interrupt-controller@00a01000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0x00a01000 0x1000>,
  54                       <0x00a00100 0x100>;
  55         };
  56
  57         clocks {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 ckil {
  62                         compatible = "fsl,imx-ckil", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <0>;
  71                 };
  72
  73                 osc {
  74                         compatible = "fsl,imx-osc", "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 dma_apbh: dma-apbh@00110000 {
  88                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  89                         reg = <0x00110000 0x2000>;
  90                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  95                         #dma-cells = <1>;
  96                         dma-channels = <4>;
  97                         clocks = <&clks 106>;
  98                 };
  99
 100                 gpmi: gpmi-nand@00112000 {
 101                         compatible = "fsl,imx6q-gpmi-nand";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 105                         reg-names = "gpmi-nand", "bch";
 106                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "bch";
 108                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 109                                  <&clks 150>, <&clks 149>;
 110                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 111                                       "gpmi_bch_apb", "per1_bch";
 112                         dmas = <&dma_apbh 0>;
 113                         dma-names = "rx-tx";
 114                         status = "disabled";
 115                 };
 116
 117                 timer@00a00600 {
 118                         compatible = "arm,cortex-a9-twd-timer";
 119                         reg = <0x00a00600 0x20>;
 120                         interrupts = <1 13 0xf01>;
 121                         clocks = <&clks 15>;
 122                 };
 123
 124                 L2: l2-cache@00a02000 {
 125                         compatible = "arm,pl310-cache";
 126                         reg = <0x00a02000 0x1000>;
 127                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 128                         cache-unified;
 129                         cache-level = <2>;
 130                         arm,tag-latency = <4 2 3>;
 131                         arm,data-latency = <4 2 3>;
 132                 };
 133
 134                 pcie: pcie@0x01000000 {
 135                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 136                         reg = <0x01ffc000 0x4000>; /* DBI */
 137                         #address-cells = <3>;
 138                         #size-cells = <2>;
 139                         device_type = "pci";
 140                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 141                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 142                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 143                         num-lanes = <1>;
 144                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 145                         #interrupt-cells = <1>;
 146                         interrupt-map-mask = <0 0 0 0x7>;
 147                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 148                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 149                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 150                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 151                         clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
 152                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 153                         status = "disabled";
 154                 };
 155
 156                 pmu {
 157                         compatible = "arm,cortex-a9-pmu";
 158                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 aips-bus@02000000 { /* AIPS1 */
 162                         compatible = "fsl,aips-bus", "simple-bus";
 163                         #address-cells = <1>;
 164                         #size-cells = <1>;
 165                         reg = <0x02000000 0x100000>;
 166                         ranges;
 167
 168                         spba-bus@02000000 {
 169                                 compatible = "fsl,spba-bus", "simple-bus";
 170                                 #address-cells = <1>;
 171                                 #size-cells = <1>;
 172                                 reg = <0x02000000 0x40000>;
 173                                 ranges;
 174
 175                                 spdif: spdif@02004000 {
 176                                         compatible = "fsl,imx35-spdif";
 177                                         reg = <0x02004000 0x4000>;
 178                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 179                                         dmas = <&sdma 14 18 0>,
 180                                                <&sdma 15 18 0>;
 181                                         dma-names = "rx", "tx";
 182                                         clocks = <&clks 197>, <&clks 3>,
 183                                                  <&clks 197>, <&clks 107>,
 184                                                  <&clks 0>,   <&clks 118>,
 185                                                  <&clks 0>,  <&clks 139>,
 186                                                  <&clks 0>;
 187                                         clock-names = "core",  "rxtx0",
 188                                                       "rxtx1", "rxtx2",
 189                                                       "rxtx3", "rxtx4",
 190                                                       "rxtx5", "rxtx6",
 191                                                       "rxtx7";
 192                                         status = "disabled";
 193                                 };
 194
 195                                 ecspi1: ecspi@02008000 {
 196                                         #address-cells = <1>;
 197                                         #size-cells = <0>;
 198                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 199                                         reg = <0x02008000 0x4000>;
 200                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 201                                         clocks = <&clks 112>, <&clks 112>;
 202                                         clock-names = "ipg", "per";
 203                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 204                                         dma-names = "rx", "tx";
 205                                         status = "disabled";
 206                                 };
 207
 208                                 ecspi2: ecspi@0200c000 {
 209                                         #address-cells = <1>;
 210                                         #size-cells = <0>;
 211                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 212                                         reg = <0x0200c000 0x4000>;
 213                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 214                                         clocks = <&clks 113>, <&clks 113>;
 215                                         clock-names = "ipg", "per";
 216                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 217                                         dma-names = "rx", "tx";
 218                                         status = "disabled";
 219                                 };
 220
 221                                 ecspi3: ecspi@02010000 {
 222                                         #address-cells = <1>;
 223                                         #size-cells = <0>;
 224                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 225                                         reg = <0x02010000 0x4000>;
 226                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks 114>, <&clks 114>;
 228                                         clock-names = "ipg", "per";
 229                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 230                                         dma-names = "rx", "tx";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 ecspi4: ecspi@02014000 {
 235                                         #address-cells = <1>;
 236                                         #size-cells = <0>;
 237                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 238                                         reg = <0x02014000 0x4000>;
 239                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks 115>, <&clks 115>;
 241                                         clock-names = "ipg", "per";
 242                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 243                                         dma-names = "rx", "tx";
 244                                         status = "disabled";
 245                                 };
 246
 247                                 uart1: serial@02020000 {
 248                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 249                                         reg = <0x02020000 0x4000>;
 250                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 251                                         clocks = <&clks 160>, <&clks 161>;
 252                                         clock-names = "ipg", "per";
 253                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 254                                         dma-names = "rx", "tx";
 255                                         status = "disabled";
 256                                 };
 257
 258                                 esai: esai@02024000 {
 259                                         reg = <0x02024000 0x4000>;
 260                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 261                                 };
 262
 263                                 ssi1: ssi@02028000 {
 264                                         compatible = "fsl,imx6q-ssi",
 265                                                         "fsl,imx51-ssi",
 266                                                         "fsl,imx21-ssi";
 267                                         reg = <0x02028000 0x4000>;
 268                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks 178>;
 270                                         dmas = <&sdma 37 1 0>,
 271                                                <&sdma 38 1 0>;
 272                                         dma-names = "rx", "tx";
 273                                         fsl,fifo-depth = <15>;
 274                                         fsl,ssi-dma-events = <38 37>;
 275                                         status = "disabled";
 276                                 };
 277
 278                                 ssi2: ssi@0202c000 {
 279                                         compatible = "fsl,imx6q-ssi",
 280                                                         "fsl,imx51-ssi",
 281                                                         "fsl,imx21-ssi";
 282                                         reg = <0x0202c000 0x4000>;
 283                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 284                                         clocks = <&clks 179>;
 285                                         dmas = <&sdma 41 1 0>,
 286                                                <&sdma 42 1 0>;
 287                                         dma-names = "rx", "tx";
 288                                         fsl,fifo-depth = <15>;
 289                                         fsl,ssi-dma-events = <42 41>;
 290                                         status = "disabled";
 291                                 };
 292
 293                                 ssi3: ssi@02030000 {
 294                                         compatible = "fsl,imx6q-ssi",
 295                                                         "fsl,imx51-ssi",
 296                                                         "fsl,imx21-ssi";
 297                                         reg = <0x02030000 0x4000>;
 298                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 299                                         clocks = <&clks 180>;
 300                                         dmas = <&sdma 45 1 0>,
 301                                                <&sdma 46 1 0>;
 302                                         dma-names = "rx", "tx";
 303                                         fsl,fifo-depth = <15>;
 304                                         fsl,ssi-dma-events = <46 45>;
 305                                         status = "disabled";
 306                                 };
 307
 308                                 asrc: asrc@02034000 {
 309                                         reg = <0x02034000 0x4000>;
 310                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 311                                 };
 312
 313                                 spba@0203c000 {
 314                                         reg = <0x0203c000 0x4000>;
 315                                 };
 316                         };
 317
 318                         vpu: vpu@02040000 {
 319                                 reg = <0x02040000 0x3c000>;
 320                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 321                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 322                         };
 323
 324                         aipstz@0207c000 { /* AIPSTZ1 */
 325                                 reg = <0x0207c000 0x4000>;
 326                         };
 327
 328                         pwm1: pwm@02080000 {
 329                                 #pwm-cells = <2>;
 330                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 331                                 reg = <0x02080000 0x4000>;
 332                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 333                                 clocks = <&clks 62>, <&clks 145>;
 334                                 clock-names = "ipg", "per";
 335                         };
 336
 337                         pwm2: pwm@02084000 {
 338                                 #pwm-cells = <2>;
 339                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 340                                 reg = <0x02084000 0x4000>;
 341                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 342                                 clocks = <&clks 62>, <&clks 146>;
 343                                 clock-names = "ipg", "per";
 344                         };
 345
 346                         pwm3: pwm@02088000 {
 347                                 #pwm-cells = <2>;
 348                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 349                                 reg = <0x02088000 0x4000>;
 350                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&clks 62>, <&clks 147>;
 352                                 clock-names = "ipg", "per";
 353                         };
 354
 355                         pwm4: pwm@0208c000 {
 356                                 #pwm-cells = <2>;
 357                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 358                                 reg = <0x0208c000 0x4000>;
 359                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clks 62>, <&clks 148>;
 361                                 clock-names = "ipg", "per";
 362                         };
 363
 364                         can1: flexcan@02090000 {
 365                                 compatible = "fsl,imx6q-flexcan";
 366                                 reg = <0x02090000 0x4000>;
 367                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks 108>, <&clks 109>;
 369                                 clock-names = "ipg", "per";
 370                                 status = "disabled";
 371                         };
 372
 373                         can2: flexcan@02094000 {
 374                                 compatible = "fsl,imx6q-flexcan";
 375                                 reg = <0x02094000 0x4000>;
 376                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 377                                 clocks = <&clks 110>, <&clks 111>;
 378                                 clock-names = "ipg", "per";
 379                                 status = "disabled";
 380                         };
 381
 382                         gpt: gpt@02098000 {
 383                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 384                                 reg = <0x02098000 0x4000>;
 385                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clks 119>, <&clks 120>;
 387                                 clock-names = "ipg", "per";
 388                         };
 389
 390                         gpio1: gpio@0209c000 {
 391                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 392                                 reg = <0x0209c000 0x4000>;
 393                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 394                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 395                                 gpio-controller;
 396                                 #gpio-cells = <2>;
 397                                 interrupt-controller;
 398                                 #interrupt-cells = <2>;
 399                         };
 400
 401                         gpio2: gpio@020a0000 {
 402                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 403                                 reg = <0x020a0000 0x4000>;
 404                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 405                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                         };
 411
 412                         gpio3: gpio@020a4000 {
 413                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 414                                 reg = <0x020a4000 0x4000>;
 415                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 416                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 417                                 gpio-controller;
 418                                 #gpio-cells = <2>;
 419                                 interrupt-controller;
 420                                 #interrupt-cells = <2>;
 421                         };
 422
 423                         gpio4: gpio@020a8000 {
 424                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 425                                 reg = <0x020a8000 0x4000>;
 426                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 427                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 428                                 gpio-controller;
 429                                 #gpio-cells = <2>;
 430                                 interrupt-controller;
 431                                 #interrupt-cells = <2>;
 432                         };
 433
 434                         gpio5: gpio@020ac000 {
 435                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 436                                 reg = <0x020ac000 0x4000>;
 437                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 438                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 439                                 gpio-controller;
 440                                 #gpio-cells = <2>;
 441                                 interrupt-controller;
 442                                 #interrupt-cells = <2>;
 443                         };
 444
 445                         gpio6: gpio@020b0000 {
 446                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 447                                 reg = <0x020b0000 0x4000>;
 448                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 449                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 450                                 gpio-controller;
 451                                 #gpio-cells = <2>;
 452                                 interrupt-controller;
 453                                 #interrupt-cells = <2>;
 454                         };
 455
 456                         gpio7: gpio@020b4000 {
 457                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 458                                 reg = <0x020b4000 0x4000>;
 459                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 460                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 461                                 gpio-controller;
 462                                 #gpio-cells = <2>;
 463                                 interrupt-controller;
 464                                 #interrupt-cells = <2>;
 465                         };
 466
 467                         kpp: kpp@020b8000 {
 468                                 reg = <0x020b8000 0x4000>;
 469                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 470                         };
 471
 472                         wdog1: wdog@020bc000 {
 473                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 474                                 reg = <0x020bc000 0x4000>;
 475                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 476                                 clocks = <&clks 0>;
 477                         };
 478
 479                         wdog2: wdog@020c0000 {
 480                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 481                                 reg = <0x020c0000 0x4000>;
 482                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks 0>;
 484                                 status = "disabled";
 485                         };
 486
 487                         clks: ccm@020c4000 {
 488                                 compatible = "fsl,imx6q-ccm";
 489                                 reg = <0x020c4000 0x4000>;
 490                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 491                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 492                                 #clock-cells = <1>;
 493                         };
 494
 495                         anatop: anatop@020c8000 {
 496                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 497                                 reg = <0x020c8000 0x1000>;
 498                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 499                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 500                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 501
 502                                 regulator-1p1@110 {
 503                                         compatible = "fsl,anatop-regulator";
 504                                         regulator-name = "vdd1p1";
 505                                         regulator-min-microvolt = <800000>;
 506                                         regulator-max-microvolt = <1375000>;
 507                                         regulator-always-on;
 508                                         anatop-reg-offset = <0x110>;
 509                                         anatop-vol-bit-shift = <8>;
 510                                         anatop-vol-bit-width = <5>;
 511                                         anatop-min-bit-val = <4>;
 512                                         anatop-min-voltage = <800000>;
 513                                         anatop-max-voltage = <1375000>;
 514                                 };
 515
 516                                 regulator-3p0@120 {
 517                                         compatible = "fsl,anatop-regulator";
 518                                         regulator-name = "vdd3p0";
 519                                         regulator-min-microvolt = <2800000>;
 520                                         regulator-max-microvolt = <3150000>;
 521                                         regulator-always-on;
 522                                         anatop-reg-offset = <0x120>;
 523                                         anatop-vol-bit-shift = <8>;
 524                                         anatop-vol-bit-width = <5>;
 525                                         anatop-min-bit-val = <0>;
 526                                         anatop-min-voltage = <2625000>;
 527                                         anatop-max-voltage = <3400000>;
 528                                 };
 529
 530                                 regulator-2p5@130 {
 531                                         compatible = "fsl,anatop-regulator";
 532                                         regulator-name = "vdd2p5";
 533                                         regulator-min-microvolt = <2000000>;
 534                                         regulator-max-microvolt = <2750000>;
 535                                         regulator-always-on;
 536                                         anatop-reg-offset = <0x130>;
 537                                         anatop-vol-bit-shift = <8>;
 538                                         anatop-vol-bit-width = <5>;
 539                                         anatop-min-bit-val = <0>;
 540                                         anatop-min-voltage = <2000000>;
 541                                         anatop-max-voltage = <2750000>;
 542                                 };
 543
 544                                 reg_arm: regulator-vddcore@140 {
 545                                         compatible = "fsl,anatop-regulator";
 546                                         regulator-name = "vddarm";
 547                                         regulator-min-microvolt = <725000>;
 548                                         regulator-max-microvolt = <1450000>;
 549                                         regulator-always-on;
 550                                         anatop-reg-offset = <0x140>;
 551                                         anatop-vol-bit-shift = <0>;
 552                                         anatop-vol-bit-width = <5>;
 553                                         anatop-delay-reg-offset = <0x170>;
 554                                         anatop-delay-bit-shift = <24>;
 555                                         anatop-delay-bit-width = <2>;
 556                                         anatop-min-bit-val = <1>;
 557                                         anatop-min-voltage = <725000>;
 558                                         anatop-max-voltage = <1450000>;
 559                                 };
 560
 561                                 reg_pu: regulator-vddpu@140 {
 562                                         compatible = "fsl,anatop-regulator";
 563                                         regulator-name = "vddpu";
 564                                         regulator-min-microvolt = <725000>;
 565                                         regulator-max-microvolt = <1450000>;
 566                                         regulator-always-on;
 567                                         anatop-reg-offset = <0x140>;
 568                                         anatop-vol-bit-shift = <9>;
 569                                         anatop-vol-bit-width = <5>;
 570                                         anatop-delay-reg-offset = <0x170>;
 571                                         anatop-delay-bit-shift = <26>;
 572                                         anatop-delay-bit-width = <2>;
 573                                         anatop-min-bit-val = <1>;
 574                                         anatop-min-voltage = <725000>;
 575                                         anatop-max-voltage = <1450000>;
 576                                 };
 577
 578                                 reg_soc: regulator-vddsoc@140 {
 579                                         compatible = "fsl,anatop-regulator";
 580                                         regulator-name = "vddsoc";
 581                                         regulator-min-microvolt = <725000>;
 582                                         regulator-max-microvolt = <1450000>;
 583                                         regulator-always-on;
 584                                         anatop-reg-offset = <0x140>;
 585                                         anatop-vol-bit-shift = <18>;
 586                                         anatop-vol-bit-width = <5>;
 587                                         anatop-delay-reg-offset = <0x170>;
 588                                         anatop-delay-bit-shift = <28>;
 589                                         anatop-delay-bit-width = <2>;
 590                                         anatop-min-bit-val = <1>;
 591                                         anatop-min-voltage = <725000>;
 592                                         anatop-max-voltage = <1450000>;
 593                                 };
 594                         };
 595
 596                         tempmon: tempmon {
 597                                 compatible = "fsl,imx6q-tempmon";
 598                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 599                                 fsl,tempmon = <&anatop>;
 600                                 fsl,tempmon-data = <&ocotp>;
 601                                 clocks = <&clks 172>;
 602                         };
 603
 604                         usbphy1: usbphy@020c9000 {
 605                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 606                                 reg = <0x020c9000 0x1000>;
 607                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&clks 182>;
 609                                 fsl,anatop = <&anatop>;
 610                         };
 611
 612                         usbphy2: usbphy@020ca000 {
 613                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 614                                 reg = <0x020ca000 0x1000>;
 615                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clks 183>;
 617                                 fsl,anatop = <&anatop>;
 618                         };
 619
 620                         snvs@020cc000 {
 621                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 622                                 #address-cells = <1>;
 623                                 #size-cells = <1>;
 624                                 ranges = <0 0x020cc000 0x4000>;
 625
 626                                 snvs-rtc-lp@34 {
 627                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 628                                         reg = <0x34 0x58>;
 629                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 630                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 631                                 };
 632                         };
 633
 634                         epit1: epit@020d0000 { /* EPIT1 */
 635                                 reg = <0x020d0000 0x4000>;
 636                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 637                         };
 638
 639                         epit2: epit@020d4000 { /* EPIT2 */
 640                                 reg = <0x020d4000 0x4000>;
 641                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 642                         };
 643
 644                         src: src@020d8000 {
 645                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 646                                 reg = <0x020d8000 0x4000>;
 647                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 648                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 649                                 #reset-cells = <1>;
 650                         };
 651
 652                         gpc: gpc@020dc000 {
 653                                 compatible = "fsl,imx6q-gpc";
 654                                 reg = <0x020dc000 0x4000>;
 655                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 656                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 657                         };
 658
 659                         gpr: iomuxc-gpr@020e0000 {
 660                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 661                                 reg = <0x020e0000 0x38>;
 662                         };
 663
 664                         iomuxc: iomuxc@020e0000 {
 665                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 666                                 reg = <0x020e0000 0x4000>;
 667                         };
 668
 669                         ldb: ldb@020e0008 {
 670                                 #address-cells = <1>;
 671                                 #size-cells = <0>;
 672                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 673                                 gpr = <&gpr>;
 674                                 status = "disabled";
 675
 676                                 lvds-channel@0 {
 677                                         #address-cells = <1>;
 678                                         #size-cells = <0>;
 679                                         reg = <0>;
 680                                         status = "disabled";
 681
 682                                         port@0 {
 683                                                 reg = <0>;
 684
 685                                                 lvds0_mux_0: endpoint {
 686                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 687                                                 };
 688                                         };
 689
 690                                         port@1 {
 691                                                 reg = <1>;
 692
 693                                                 lvds0_mux_1: endpoint {
 694                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 695                                                 };
 696                                         };
 697                                 };
 698
 699                                 lvds-channel@1 {
 700                                         #address-cells = <1>;
 701                                         #size-cells = <0>;
 702                                         reg = <1>;
 703                                         status = "disabled";
 704
 705                                         port@0 {
 706                                                 reg = <0>;
 707
 708                                                 lvds1_mux_0: endpoint {
 709                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 710                                                 };
 711                                         };
 712
 713                                         port@1 {
 714                                                 reg = <1>;
 715
 716                                                 lvds1_mux_1: endpoint {
 717                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 718                                                 };
 719                                         };
 720                                 };
 721                         };
 722
 723                         hdmi: hdmi@0120000 {
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 reg = <0x00120000 0x9000>;
 727                                 interrupts = <0 115 0x04>;
 728                                 gpr = <&gpr>;
 729                                 clocks = <&clks 123>, <&clks 124>;
 730                                 clock-names = "iahb", "isfr";
 731                                 status = "disabled";
 732
 733                                 port@0 {
 734                                         reg = <0>;
 735
 736                                         hdmi_mux_0: endpoint {
 737                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 738                                         };
 739                                 };
 740
 741                                 port@1 {
 742                                         reg = <1>;
 743
 744                                         hdmi_mux_1: endpoint {
 745                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 746                                         };
 747                                 };
 748                         };
 749
 750                         dcic1: dcic@020e4000 {
 751                                 reg = <0x020e4000 0x4000>;
 752                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 753                         };
 754
 755                         dcic2: dcic@020e8000 {
 756                                 reg = <0x020e8000 0x4000>;
 757                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 758                         };
 759
 760                         sdma: sdma@020ec000 {
 761                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 762                                 reg = <0x020ec000 0x4000>;
 763                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 764                                 clocks = <&clks 155>, <&clks 155>;
 765                                 clock-names = "ipg", "ahb";
 766                                 #dma-cells = <3>;
 767                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 768                         };
 769                 };
 770
 771                 aips-bus@02100000 { /* AIPS2 */
 772                         compatible = "fsl,aips-bus", "simple-bus";
 773                         #address-cells = <1>;
 774                         #size-cells = <1>;
 775                         reg = <0x02100000 0x100000>;
 776                         ranges;
 777
 778                         caam@02100000 {
 779                                 reg = <0x02100000 0x40000>;
 780                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 781                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 782                         };
 783
 784                         aipstz@0217c000 { /* AIPSTZ2 */
 785                                 reg = <0x0217c000 0x4000>;
 786                         };
 787
 788                         usbotg: usb@02184000 {
 789                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 790                                 reg = <0x02184000 0x200>;
 791                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 792                                 clocks = <&clks 162>;
 793                                 fsl,usbphy = <&usbphy1>;
 794                                 fsl,usbmisc = <&usbmisc 0>;
 795                                 status = "disabled";
 796                         };
 797
 798                         usbh1: usb@02184200 {
 799                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 800                                 reg = <0x02184200 0x200>;
 801                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clks 162>;
 803                                 fsl,usbphy = <&usbphy2>;
 804                                 fsl,usbmisc = <&usbmisc 1>;
 805                                 status = "disabled";
 806                         };
 807
 808                         usbh2: usb@02184400 {
 809                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 810                                 reg = <0x02184400 0x200>;
 811                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 812                                 clocks = <&clks 162>;
 813                                 fsl,usbmisc = <&usbmisc 2>;
 814                                 status = "disabled";
 815                         };
 816
 817                         usbh3: usb@02184600 {
 818                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 819                                 reg = <0x02184600 0x200>;
 820                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks 162>;
 822                                 fsl,usbmisc = <&usbmisc 3>;
 823                                 status = "disabled";
 824                         };
 825
 826                         usbmisc: usbmisc@02184800 {
 827                                 #index-cells = <1>;
 828                                 compatible = "fsl,imx6q-usbmisc";
 829                                 reg = <0x02184800 0x200>;
 830                                 clocks = <&clks 162>;
 831                         };
 832
 833                         fec: ethernet@02188000 {
 834                                 compatible = "fsl,imx6q-fec";
 835                                 reg = <0x02188000 0x4000>;
 836                                 interrupts-extended =
 837                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 838                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 840                                 clock-names = "ipg", "ahb", "ptp";
 841                                 status = "disabled";
 842                         };
 843
 844                         mlb@0218c000 {
 845                                 reg = <0x0218c000 0x4000>;
 846                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 847                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 848                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 849                         };
 850
 851                         usdhc1: usdhc@02190000 {
 852                                 compatible = "fsl,imx6q-usdhc";
 853                                 reg = <0x02190000 0x4000>;
 854                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 856                                 clock-names = "ipg", "ahb", "per";
 857                                 bus-width = <4>;
 858                                 status = "disabled";
 859                         };
 860
 861                         usdhc2: usdhc@02194000 {
 862                                 compatible = "fsl,imx6q-usdhc";
 863                                 reg = <0x02194000 0x4000>;
 864                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 866                                 clock-names = "ipg", "ahb", "per";
 867                                 bus-width = <4>;
 868                                 status = "disabled";
 869                         };
 870
 871                         usdhc3: usdhc@02198000 {
 872                                 compatible = "fsl,imx6q-usdhc";
 873                                 reg = <0x02198000 0x4000>;
 874                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 876                                 clock-names = "ipg", "ahb", "per";
 877                                 bus-width = <4>;
 878                                 status = "disabled";
 879                         };
 880
 881                         usdhc4: usdhc@0219c000 {
 882                                 compatible = "fsl,imx6q-usdhc";
 883                                 reg = <0x0219c000 0x4000>;
 884                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 886                                 clock-names = "ipg", "ahb", "per";
 887                                 bus-width = <4>;
 888                                 status = "disabled";
 889                         };
 890
 891                         i2c1: i2c@021a0000 {
 892                                 #address-cells = <1>;
 893                                 #size-cells = <0>;
 894                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 895                                 reg = <0x021a0000 0x4000>;
 896                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 897                                 clocks = <&clks 125>;
 898                                 status = "disabled";
 899                         };
 900
 901                         i2c2: i2c@021a4000 {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 905                                 reg = <0x021a4000 0x4000>;
 906                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&clks 126>;
 908                                 status = "disabled";
 909                         };
 910
 911                         i2c3: i2c@021a8000 {
 912                                 #address-cells = <1>;
 913                                 #size-cells = <0>;
 914                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 915                                 reg = <0x021a8000 0x4000>;
 916                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 917                                 clocks = <&clks 127>;
 918                                 status = "disabled";
 919                         };
 920
 921                         romcp@021ac000 {
 922                                 reg = <0x021ac000 0x4000>;
 923                         };
 924
 925                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 926                                 compatible = "fsl,imx6q-mmdc";
 927                                 reg = <0x021b0000 0x4000>;
 928                         };
 929
 930                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 931                                 reg = <0x021b4000 0x4000>;
 932                         };
 933
 934                         weim: weim@021b8000 {
 935                                 compatible = "fsl,imx6q-weim";
 936                                 reg = <0x021b8000 0x4000>;
 937                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 938                                 clocks = <&clks 196>;
 939                         };
 940
 941                         ocotp: ocotp@021bc000 {
 942                                 compatible = "fsl,imx6q-ocotp", "syscon";
 943                                 reg = <0x021bc000 0x4000>;
 944                         };
 945
 946                         tzasc@021d0000 { /* TZASC1 */
 947                                 reg = <0x021d0000 0x4000>;
 948                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 949                         };
 950
 951                         tzasc@021d4000 { /* TZASC2 */
 952                                 reg = <0x021d4000 0x4000>;
 953                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 954                         };
 955
 956                         audmux: audmux@021d8000 {
 957                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 958                                 reg = <0x021d8000 0x4000>;
 959                                 status = "disabled";
 960                         };
 961
 962                         mipi_csi: mipi@021dc000 {
 963                                 reg = <0x021dc000 0x4000>;
 964                         };
 965
 966                         mipi_dsi: mipi@021e0000 {
 967                                 #address-cells = <1>;
 968                                 #size-cells = <0>;
 969                                 reg = <0x021e0000 0x4000>;
 970                                 status = "disabled";
 971
 972                                 port@0 {
 973                                         reg = <0>;
 974
 975                                         mipi_mux_0: endpoint {
 976                                                 remote-endpoint = <&ipu1_di0_mipi>;
 977                                         };
 978                                 };
 979
 980                                 port@1 {
 981                                         reg = <1>;
 982
 983                                         mipi_mux_1: endpoint {
 984                                                 remote-endpoint = <&ipu1_di1_mipi>;
 985                                         };
 986                                 };
 987                         };
 988
 989                         vdoa@021e4000 {
 990                                 reg = <0x021e4000 0x4000>;
 991                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 992                         };
 993
 994                         uart2: serial@021e8000 {
 995                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 996                                 reg = <0x021e8000 0x4000>;
 997                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 998                                 clocks = <&clks 160>, <&clks 161>;
 999                                 clock-names = "ipg", "per";
1000                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1001                                 dma-names = "rx", "tx";
1002                                 status = "disabled";
1003                         };
1004
1005                         uart3: serial@021ec000 {
1006                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1007                                 reg = <0x021ec000 0x4000>;
1008                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clks 160>, <&clks 161>;
1010                                 clock-names = "ipg", "per";
1011                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1012                                 dma-names = "rx", "tx";
1013                                 status = "disabled";
1014                         };
1015
1016                         uart4: serial@021f0000 {
1017                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1018                                 reg = <0x021f0000 0x4000>;
1019                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1020                                 clocks = <&clks 160>, <&clks 161>;
1021                                 clock-names = "ipg", "per";
1022                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1023                                 dma-names = "rx", "tx";
1024                                 status = "disabled";
1025                         };
1026
1027                         uart5: serial@021f4000 {
1028                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1029                                 reg = <0x021f4000 0x4000>;
1030                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1031                                 clocks = <&clks 160>, <&clks 161>;
1032                                 clock-names = "ipg", "per";
1033                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1034                                 dma-names = "rx", "tx";
1035                                 status = "disabled";
1036                         };
1037                 };
1038
1039                 ipu1: ipu@02400000 {
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042                         compatible = "fsl,imx6q-ipu";
1043                         reg = <0x02400000 0x400000>;
1044                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1045                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1046                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1047                         clock-names = "bus", "di0", "di1";
1048                         resets = <&src 2>;
1049
1050                         ipu1_di0: port@2 {
1051                                 #address-cells = <1>;
1052                                 #size-cells = <0>;
1053                                 reg = <2>;
1054
1055                                 ipu1_di0_disp0: endpoint@0 {
1056                                 };
1057
1058                                 ipu1_di0_hdmi: endpoint@1 {
1059                                         remote-endpoint = <&hdmi_mux_0>;
1060                                 };
1061
1062                                 ipu1_di0_mipi: endpoint@2 {
1063                                         remote-endpoint = <&mipi_mux_0>;
1064                                 };
1065
1066                                 ipu1_di0_lvds0: endpoint@3 {
1067                                         remote-endpoint = <&lvds0_mux_0>;
1068                                 };
1069
1070                                 ipu1_di0_lvds1: endpoint@4 {
1071                                         remote-endpoint = <&lvds1_mux_0>;
1072                                 };
1073                         };
1074
1075                         ipu1_di1: port@3 {
1076                                 #address-cells = <1>;
1077                                 #size-cells = <0>;
1078                                 reg = <3>;
1079
1080                                 ipu1_di0_disp1: endpoint@0 {
1081                                 };
1082
1083                                 ipu1_di1_hdmi: endpoint@1 {
1084                                         remote-endpoint = <&hdmi_mux_1>;
1085                                 };
1086
1087                                 ipu1_di1_mipi: endpoint@2 {
1088                                         remote-endpoint = <&mipi_mux_1>;
1089                                 };
1090
1091                                 ipu1_di1_lvds0: endpoint@3 {
1092                                         remote-endpoint = <&lvds0_mux_1>;
1093                                 };
1094
1095                                 ipu1_di1_lvds1: endpoint@4 {
1096                                         remote-endpoint = <&lvds1_mux_1>;
1097                                 };
1098                         };
1099                 };
1100         };
1101 };