arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  50
  51 / {
  52         clocks {
  53                 clk_hse: clk-hse {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <0>;
  57                 };
  58         };
  59
  60         soc {
  61                 dma-ranges = <0xc0000000 0x0 0x10000000>;
  62
  63                 timer2: timer@40000000 {
  64                         compatible = "st,stm32-timer";
  65                         reg = <0x40000000 0x400>;
  66                         interrupts = <28>;
  67                         clocks = <&rcc 0 128>;
  68                         status = "disabled";
  69                 };
  70
  71                 timer3: timer@40000400 {
  72                         compatible = "st,stm32-timer";
  73                         reg = <0x40000400 0x400>;
  74                         interrupts = <29>;
  75                         clocks = <&rcc 0 129>;
  76                         status = "disabled";
  77                 };
  78
  79                 timer4: timer@40000800 {
  80                         compatible = "st,stm32-timer";
  81                         reg = <0x40000800 0x400>;
  82                         interrupts = <30>;
  83                         clocks = <&rcc 0 130>;
  84                         status = "disabled";
  85                 };
  86
  87                 timer5: timer@40000c00 {
  88                         compatible = "st,stm32-timer";
  89                         reg = <0x40000c00 0x400>;
  90                         interrupts = <50>;
  91                         clocks = <&rcc 0 131>;
  92                 };
  93
  94                 timer6: timer@40001000 {
  95                         compatible = "st,stm32-timer";
  96                         reg = <0x40001000 0x400>;
  97                         interrupts = <54>;
  98                         clocks = <&rcc 0 132>;
  99                         status = "disabled";
 100                 };
 101
 102                 timer7: timer@40001400 {
 103                         compatible = "st,stm32-timer";
 104                         reg = <0x40001400 0x400>;
 105                         interrupts = <55>;
 106                         clocks = <&rcc 0 133>;
 107                         status = "disabled";
 108                 };
 109
 110                 usart2: serial@40004400 {
 111                         compatible = "st,stm32-usart", "st,stm32-uart";
 112                         reg = <0x40004400 0x400>;
 113                         interrupts = <38>;
 114                         clocks =  <&rcc 0 145>;
 115                         status = "disabled";
 116                 };
 117
 118                 usart3: serial@40004800 {
 119                         compatible = "st,stm32-usart", "st,stm32-uart";
 120                         reg = <0x40004800 0x400>;
 121                         interrupts = <39>;
 122                         clocks = <&rcc 0 146>;
 123                         status = "disabled";
 124                 };
 125
 126                 usart4: serial@40004c00 {
 127                         compatible = "st,stm32-uart";
 128                         reg = <0x40004c00 0x400>;
 129                         interrupts = <52>;
 130                         clocks = <&rcc 0 147>;
 131                         status = "disabled";
 132                 };
 133
 134                 usart5: serial@40005000 {
 135                         compatible = "st,stm32-uart";
 136                         reg = <0x40005000 0x400>;
 137                         interrupts = <53>;
 138                         clocks = <&rcc 0 148>;
 139                         status = "disabled";
 140                 };
 141
 142                 usart7: serial@40007800 {
 143                         compatible = "st,stm32-usart", "st,stm32-uart";
 144                         reg = <0x40007800 0x400>;
 145                         interrupts = <82>;
 146                         clocks = <&rcc 0 158>;
 147                         status = "disabled";
 148                 };
 149
 150                 usart8: serial@40007c00 {
 151                         compatible = "st,stm32-usart", "st,stm32-uart";
 152                         reg = <0x40007c00 0x400>;
 153                         interrupts = <83>;
 154                         clocks = <&rcc 0 159>;
 155                         status = "disabled";
 156                 };
 157
 158                 usart1: serial@40011000 {
 159                         compatible = "st,stm32-usart", "st,stm32-uart";
 160                         reg = <0x40011000 0x400>;
 161                         interrupts = <37>;
 162                         clocks = <&rcc 0 164>;
 163                         status = "disabled";
 164                 };
 165
 166                 usart6: serial@40011400 {
 167                         compatible = "st,stm32-usart", "st,stm32-uart";
 168                         reg = <0x40011400 0x400>;
 169                         interrupts = <71>;
 170                         clocks = <&rcc 0 165>;
 171                         status = "disabled";
 172                 };
 173
 174                 pin-controller {
 175                         #address-cells = <1>;
 176                         #size-cells = <1>;
 177                         compatible = "st,stm32f429-pinctrl";
 178                         ranges = <0 0x40020000 0x3000>;
 179                         pins-are-numbered;
 180
 181                         gpioa: gpio@40020000 {
 182                                 gpio-controller;
 183                                 #gpio-cells = <2>;
 184                                 reg = <0x0 0x400>;
 185                                 clocks = <&rcc 0 256>;
 186                                 st,bank-name = "GPIOA";
 187                         };
 188
 189                         gpiob: gpio@40020400 {
 190                                 gpio-controller;
 191                                 #gpio-cells = <2>;
 192                                 reg = <0x400 0x400>;
 193                                 clocks = <&rcc 0 257>;
 194                                 st,bank-name = "GPIOB";
 195                         };
 196
 197                         gpioc: gpio@40020800 {
 198                                 gpio-controller;
 199                                 #gpio-cells = <2>;
 200                                 reg = <0x800 0x400>;
 201                                 clocks = <&rcc 0 258>;
 202                                 st,bank-name = "GPIOC";
 203                         };
 204
 205                         gpiod: gpio@40020c00 {
 206                                 gpio-controller;
 207                                 #gpio-cells = <2>;
 208                                 reg = <0xc00 0x400>;
 209                                 clocks = <&rcc 0 259>;
 210                                 st,bank-name = "GPIOD";
 211                         };
 212
 213                         gpioe: gpio@40021000 {
 214                                 gpio-controller;
 215                                 #gpio-cells = <2>;
 216                                 reg = <0x1000 0x400>;
 217                                 clocks = <&rcc 0 260>;
 218                                 st,bank-name = "GPIOE";
 219                         };
 220
 221                         gpiof: gpio@40021400 {
 222                                 gpio-controller;
 223                                 #gpio-cells = <2>;
 224                                 reg = <0x1400 0x400>;
 225                                 clocks = <&rcc 0 261>;
 226                                 st,bank-name = "GPIOF";
 227                         };
 228
 229                         gpiog: gpio@40021800 {
 230                                 gpio-controller;
 231                                 #gpio-cells = <2>;
 232                                 reg = <0x1800 0x400>;
 233                                 clocks = <&rcc 0 262>;
 234                                 st,bank-name = "GPIOG";
 235                         };
 236
 237                         gpioh: gpio@40021c00 {
 238                                 gpio-controller;
 239                                 #gpio-cells = <2>;
 240                                 reg = <0x1c00 0x400>;
 241                                 clocks = <&rcc 0 263>;
 242                                 st,bank-name = "GPIOH";
 243                         };
 244
 245                         gpioi: gpio@40022000 {
 246                                 gpio-controller;
 247                                 #gpio-cells = <2>;
 248                                 reg = <0x2000 0x400>;
 249                                 clocks = <&rcc 0 264>;
 250                                 st,bank-name = "GPIOI";
 251                         };
 252
 253                         gpioj: gpio@40022400 {
 254                                 gpio-controller;
 255                                 #gpio-cells = <2>;
 256                                 reg = <0x2400 0x400>;
 257                                 clocks = <&rcc 0 265>;
 258                                 st,bank-name = "GPIOJ";
 259                         };
 260
 261                         gpiok: gpio@40022800 {
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                                 reg = <0x2800 0x400>;
 265                                 clocks = <&rcc 0 266>;
 266                                 st,bank-name = "GPIOK";
 267                         };
 268
 269                         usart1_pins_a: usart1@0 {
 270                                 pins1 {
 271                                         pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
 272                                         bias-disable;
 273                                         drive-push-pull;
 274                                         slew-rate = <0>;
 275                                 };
 276                                 pins2 {
 277                                         pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
 278                                         bias-disable;
 279                                 };
 280                         };
 281                 };
 282
 283                 rcc: rcc@40023810 {
 284                         #clock-cells = <2>;
 285                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 286                         reg = <0x40023800 0x400>;
 287                         clocks = <&clk_hse>;
 288                 };
 289
 290                 dma1: dma-controller@40026000 {
 291                         compatible = "st,stm32-dma";
 292                         reg = <0x40026000 0x400>;
 293                         interrupts = <11>,
 294                                      <12>,
 295                                      <13>,
 296                                      <14>,
 297                                      <15>,
 298                                      <16>,
 299                                      <17>,
 300                                      <47>;
 301                         clocks = <&rcc 0 21>;
 302                         #dma-cells = <4>;
 303                 };
 304
 305                 dma2: dma-controller@40026400 {
 306                         compatible = "st,stm32-dma";
 307                         reg = <0x40026400 0x400>;
 308                         interrupts = <56>,
 309                                      <57>,
 310                                      <58>,
 311                                      <59>,
 312                                      <60>,
 313                                      <68>,
 314                                      <69>,
 315                                      <70>;
 316                         clocks = <&rcc 0 22>;
 317                         #dma-cells = <4>;
 318                         st,mem2mem;
 319                 };
 320
 321                 rng: rng@50060800 {
 322                         compatible = "st,stm32-rng";
 323                         reg = <0x50060800 0x400>;
 324                         interrupts = <80>;
 325                         clocks = <&rcc 0 38>;
 326                 };
 327         };
 328 };
 329
 330 &systick {
 331         clocks = <&rcc 1 0>;
 332         status = "okay";
 333 };