arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 #include <dt-bindings/dma/sun4i-a10.h>
  17 #include <dt-bindings/pinctrl/sun4i-a10.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         aliases {
  23                 ethernet0 = &emac;
  24         };
  25
  26         chosen {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges;
  30
  31                 framebuffer@0 {
  32                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  33                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  34                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  35                                  <&ahb_gates 44>;
  36                         status = "disabled";
  37                 };
  38
  39                 framebuffer@1 {
  40                         compatible = "allwinner,simple-framebuffer",
  41                                      "simple-framebuffer";
  42                         allwinner,pipeline = "de_be0-lcd0";
  43                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  44                         status = "disabled";
  45                 };
  46         };
  47
  48         cpus {
  49                 cpu@0 {
  50                         compatible = "arm,cortex-a8";
  51                 };
  52         };
  53
  54         memory {
  55                 reg = <0x40000000 0x20000000>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 /*
  64                  * This is a dummy clock, to be used as placeholder on
  65                  * other mux clocks when a specific parent clock is not
  66                  * yet implemented. It should be dropped when the driver
  67                  * is complete.
  68                  */
  69                 dummy: dummy {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc24M: clk@01c20050 {
  76                         #clock-cells = <0>;
  77                         compatible = "allwinner,sun4i-a10-osc-clk";
  78                         reg = <0x01c20050 0x4>;
  79                         clock-frequency = <24000000>;
  80                         clock-output-names = "osc24M";
  81                 };
  82
  83                 osc32k: clk@0 {
  84                         #clock-cells = <0>;
  85                         compatible = "fixed-clock";
  86                         clock-frequency = <32768>;
  87                         clock-output-names = "osc32k";
  88                 };
  89
  90                 pll1: clk@01c20000 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-a10-pll1-clk";
  93                         reg = <0x01c20000 0x4>;
  94                         clocks = <&osc24M>;
  95                         clock-output-names = "pll1";
  96                 };
  97
  98                 pll4: clk@01c20018 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun4i-a10-pll1-clk";
 101                         reg = <0x01c20018 0x4>;
 102                         clocks = <&osc24M>;
 103                         clock-output-names = "pll4";
 104                 };
 105
 106                 pll5: clk@01c20020 {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun4i-a10-pll5-clk";
 109                         reg = <0x01c20020 0x4>;
 110                         clocks = <&osc24M>;
 111                         clock-output-names = "pll5_ddr", "pll5_other";
 112                 };
 113
 114                 pll6: clk@01c20028 {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun4i-a10-pll6-clk";
 117                         reg = <0x01c20028 0x4>;
 118                         clocks = <&osc24M>;
 119                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 120                 };
 121
 122                 /* dummy is 200M */
 123                 cpu: cpu@01c20054 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun4i-a10-cpu-clk";
 126                         reg = <0x01c20054 0x4>;
 127                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 128                         clock-output-names = "cpu";
 129                 };
 130
 131                 axi: axi@01c20054 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun4i-a10-axi-clk";
 134                         reg = <0x01c20054 0x4>;
 135                         clocks = <&cpu>;
 136                         clock-output-names = "axi";
 137                 };
 138
 139                 axi_gates: clk@01c2005c {
 140                         #clock-cells = <1>;
 141                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 142                         reg = <0x01c2005c 0x4>;
 143                         clocks = <&axi>;
 144                         clock-output-names = "axi_dram";
 145                 };
 146
 147                 ahb: ahb@01c20054 {
 148                         #clock-cells = <0>;
 149                         compatible = "allwinner,sun4i-a10-ahb-clk";
 150                         reg = <0x01c20054 0x4>;
 151                         clocks = <&axi>;
 152                         clock-output-names = "ahb";
 153                 };
 154
 155                 ahb_gates: clk@01c20060 {
 156                         #clock-cells = <1>;
 157                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 158                         reg = <0x01c20060 0x8>;
 159                         clocks = <&ahb>;
 160                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 161                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 162                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 163                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 164                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 165                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 166                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 167                 };
 168
 169                 apb0: apb0@01c20054 {
 170                         #clock-cells = <0>;
 171                         compatible = "allwinner,sun4i-a10-apb0-clk";
 172                         reg = <0x01c20054 0x4>;
 173                         clocks = <&ahb>;
 174                         clock-output-names = "apb0";
 175                 };
 176
 177                 apb0_gates: clk@01c20068 {
 178                         #clock-cells = <1>;
 179                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 180                         reg = <0x01c20068 0x4>;
 181                         clocks = <&apb0>;
 182                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 183                                 "apb0_ir", "apb0_keypad";
 184                 };
 185
 186                 apb1: clk@01c20058 {
 187                         #clock-cells = <0>;
 188                         compatible = "allwinner,sun4i-a10-apb1-clk";
 189                         reg = <0x01c20058 0x4>;
 190                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 191                         clock-output-names = "apb1";
 192                 };
 193
 194                 apb1_gates: clk@01c2006c {
 195                         #clock-cells = <1>;
 196                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 197                         reg = <0x01c2006c 0x4>;
 198                         clocks = <&apb1>;
 199                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 200                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 201                                 "apb1_uart2", "apb1_uart3";
 202                 };
 203
 204                 nand_clk: clk@01c20080 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun4i-a10-mod0-clk";
 207                         reg = <0x01c20080 0x4>;
 208                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209                         clock-output-names = "nand";
 210                 };
 211
 212                 ms_clk: clk@01c20084 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-mod0-clk";
 215                         reg = <0x01c20084 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "ms";
 218                 };
 219
 220                 mmc0_clk: clk@01c20088 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-mod0-clk";
 223                         reg = <0x01c20088 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc0";
 226                 };
 227
 228                 mmc1_clk: clk@01c2008c {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-a10-mod0-clk";
 231                         reg = <0x01c2008c 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc1";
 234                 };
 235
 236                 mmc2_clk: clk@01c20090 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-a10-mod0-clk";
 239                         reg = <0x01c20090 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "mmc2";
 242                 };
 243
 244                 ts_clk: clk@01c20098 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-a10-mod0-clk";
 247                         reg = <0x01c20098 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "ts";
 250                 };
 251
 252                 ss_clk: clk@01c2009c {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-a10-mod0-clk";
 255                         reg = <0x01c2009c 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "ss";
 258                 };
 259
 260                 spi0_clk: clk@01c200a0 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-a10-mod0-clk";
 263                         reg = <0x01c200a0 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "spi0";
 266                 };
 267
 268                 spi1_clk: clk@01c200a4 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c200a4 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "spi1";
 274                 };
 275
 276                 spi2_clk: clk@01c200a8 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-a10-mod0-clk";
 279                         reg = <0x01c200a8 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "spi2";
 282                 };
 283
 284                 ir0_clk: clk@01c200b0 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c200b0 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "ir0";
 290                 };
 291
 292                 usb_clk: clk@01c200cc {
 293                         #clock-cells = <1>;
 294                         #reset-cells = <1>;
 295                         compatible = "allwinner,sun5i-a13-usb-clk";
 296                         reg = <0x01c200cc 0x4>;
 297                         clocks = <&pll6 1>;
 298                         clock-output-names = "usb_ohci0", "usb_phy";
 299                 };
 300
 301                 mbus_clk: clk@01c2015c {
 302                         #clock-cells = <0>;
 303                         compatible = "allwinner,sun5i-a13-mbus-clk";
 304                         reg = <0x01c2015c 0x4>;
 305                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 306                         clock-output-names = "mbus";
 307                 };
 308         };
 309
 310         soc@01c00000 {
 311                 compatible = "simple-bus";
 312                 #address-cells = <1>;
 313                 #size-cells = <1>;
 314                 ranges;
 315
 316                 dma: dma-controller@01c02000 {
 317                         compatible = "allwinner,sun4i-a10-dma";
 318                         reg = <0x01c02000 0x1000>;
 319                         interrupts = <27>;
 320                         clocks = <&ahb_gates 6>;
 321                         #dma-cells = <2>;
 322                 };
 323
 324                 spi0: spi@01c05000 {
 325                         compatible = "allwinner,sun4i-a10-spi";
 326                         reg = <0x01c05000 0x1000>;
 327                         interrupts = <10>;
 328                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 329                         clock-names = "ahb", "mod";
 330                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 331                                <&dma SUN4I_DMA_DEDICATED 26>;
 332                         dma-names = "rx", "tx";
 333                         status = "disabled";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                 };
 337
 338                 spi1: spi@01c06000 {
 339                         compatible = "allwinner,sun4i-a10-spi";
 340                         reg = <0x01c06000 0x1000>;
 341                         interrupts = <11>;
 342                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 343                         clock-names = "ahb", "mod";
 344                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 345                                <&dma SUN4I_DMA_DEDICATED 8>;
 346                         dma-names = "rx", "tx";
 347                         status = "disabled";
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                 };
 351
 352                 emac: ethernet@01c0b000 {
 353                         compatible = "allwinner,sun4i-a10-emac";
 354                         reg = <0x01c0b000 0x1000>;
 355                         interrupts = <55>;
 356                         clocks = <&ahb_gates 17>;
 357                         status = "disabled";
 358                 };
 359
 360                 mdio: mdio@01c0b080 {
 361                         compatible = "allwinner,sun4i-a10-mdio";
 362                         reg = <0x01c0b080 0x14>;
 363                         status = "disabled";
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                 };
 367
 368                 mmc0: mmc@01c0f000 {
 369                         compatible = "allwinner,sun5i-a13-mmc";
 370                         reg = <0x01c0f000 0x1000>;
 371                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 372                         clock-names = "ahb", "mmc";
 373                         interrupts = <32>;
 374                         status = "disabled";
 375                 };
 376
 377                 mmc1: mmc@01c10000 {
 378                         compatible = "allwinner,sun5i-a13-mmc";
 379                         reg = <0x01c10000 0x1000>;
 380                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 381                         clock-names = "ahb", "mmc";
 382                         interrupts = <33>;
 383                         status = "disabled";
 384                 };
 385
 386                 mmc2: mmc@01c11000 {
 387                         compatible = "allwinner,sun5i-a13-mmc";
 388                         reg = <0x01c11000 0x1000>;
 389                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 390                         clock-names = "ahb", "mmc";
 391                         interrupts = <34>;
 392                         status = "disabled";
 393                 };
 394
 395                 usbphy: phy@01c13400 {
 396                         #phy-cells = <1>;
 397                         compatible = "allwinner,sun5i-a13-usb-phy";
 398                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 399                         reg-names = "phy_ctrl", "pmu1";
 400                         clocks = <&usb_clk 8>;
 401                         clock-names = "usb_phy";
 402                         resets = <&usb_clk 0>, <&usb_clk 1>;
 403                         reset-names = "usb0_reset", "usb1_reset";
 404                         status = "disabled";
 405                 };
 406
 407                 ehci0: usb@01c14000 {
 408                         compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
 409                         reg = <0x01c14000 0x100>;
 410                         interrupts = <39>;
 411                         clocks = <&ahb_gates 1>;
 412                         phys = <&usbphy 1>;
 413                         phy-names = "usb";
 414                         status = "disabled";
 415                 };
 416
 417                 ohci0: usb@01c14400 {
 418                         compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
 419                         reg = <0x01c14400 0x100>;
 420                         interrupts = <40>;
 421                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 422                         phys = <&usbphy 1>;
 423                         phy-names = "usb";
 424                         status = "disabled";
 425                 };
 426
 427                 spi2: spi@01c17000 {
 428                         compatible = "allwinner,sun4i-a10-spi";
 429                         reg = <0x01c17000 0x1000>;
 430                         interrupts = <12>;
 431                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 432                         clock-names = "ahb", "mod";
 433                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 434                                <&dma SUN4I_DMA_DEDICATED 28>;
 435                         dma-names = "rx", "tx";
 436                         status = "disabled";
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                 };
 440
 441                 intc: interrupt-controller@01c20400 {
 442                         compatible = "allwinner,sun4i-a10-ic";
 443                         reg = <0x01c20400 0x400>;
 444                         interrupt-controller;
 445                         #interrupt-cells = <1>;
 446                 };
 447
 448                 pio: pinctrl@01c20800 {
 449                         compatible = "allwinner,sun5i-a10s-pinctrl";
 450                         reg = <0x01c20800 0x400>;
 451                         interrupts = <28>;
 452                         clocks = <&apb0_gates 5>;
 453                         gpio-controller;
 454                         interrupt-controller;
 455                         #interrupt-cells = <2>;
 456                         #size-cells = <0>;
 457                         #gpio-cells = <3>;
 458
 459                         uart0_pins_a: uart0@0 {
 460                                 allwinner,pins = "PB19", "PB20";
 461                                 allwinner,function = "uart0";
 462                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 463                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 464                         };
 465
 466                         uart2_pins_a: uart2@0 {
 467                                 allwinner,pins = "PC18", "PC19";
 468                                 allwinner,function = "uart2";
 469                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 470                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 471                         };
 472
 473                         uart3_pins_a: uart3@0 {
 474                                 allwinner,pins = "PG9", "PG10";
 475                                 allwinner,function = "uart3";
 476                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 477                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 478                         };
 479
 480                         emac_pins_a: emac0@0 {
 481                                 allwinner,pins = "PA0", "PA1", "PA2",
 482                                                 "PA3", "PA4", "PA5", "PA6",
 483                                                 "PA7", "PA8", "PA9", "PA10",
 484                                                 "PA11", "PA12", "PA13", "PA14",
 485                                                 "PA15", "PA16";
 486                                 allwinner,function = "emac";
 487                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 488                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 489                         };
 490
 491                         i2c0_pins_a: i2c0@0 {
 492                                 allwinner,pins = "PB0", "PB1";
 493                                 allwinner,function = "i2c0";
 494                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 495                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 496                         };
 497
 498                         i2c1_pins_a: i2c1@0 {
 499                                 allwinner,pins = "PB15", "PB16";
 500                                 allwinner,function = "i2c1";
 501                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 502                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 503                         };
 504
 505                         i2c2_pins_a: i2c2@0 {
 506                                 allwinner,pins = "PB17", "PB18";
 507                                 allwinner,function = "i2c2";
 508                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 509                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 510                         };
 511
 512                         mmc0_pins_a: mmc0@0 {
 513                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 514                                 allwinner,function = "mmc0";
 515                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 516                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 517                         };
 518
 519                         mmc1_pins_a: mmc1@0 {
 520                                 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
 521                                 allwinner,function = "mmc1";
 522                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 523                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 524                         };
 525                 };
 526
 527                 timer@01c20c00 {
 528                         compatible = "allwinner,sun4i-a10-timer";
 529                         reg = <0x01c20c00 0x90>;
 530                         interrupts = <22>;
 531                         clocks = <&osc24M>;
 532                 };
 533
 534                 wdt: watchdog@01c20c90 {
 535                         compatible = "allwinner,sun4i-a10-wdt";
 536                         reg = <0x01c20c90 0x10>;
 537                 };
 538
 539                 lradc: lradc@01c22800 {
 540                         compatible = "allwinner,sun4i-a10-lradc-keys";
 541                         reg = <0x01c22800 0x100>;
 542                         interrupts = <31>;
 543                         status = "disabled";
 544                 };
 545
 546                 sid: eeprom@01c23800 {
 547                         compatible = "allwinner,sun4i-a10-sid";
 548                         reg = <0x01c23800 0x10>;
 549                 };
 550
 551                 rtp: rtp@01c25000 {
 552                         compatible = "allwinner,sun4i-a10-ts";
 553                         reg = <0x01c25000 0x100>;
 554                         interrupts = <29>;
 555                         #thermal-sensor-cells = <0>;
 556                 };
 557
 558                 uart0: serial@01c28000 {
 559                         compatible = "snps,dw-apb-uart";
 560                         reg = <0x01c28000 0x400>;
 561                         interrupts = <1>;
 562                         reg-shift = <2>;
 563                         reg-io-width = <4>;
 564                         clocks = <&apb1_gates 16>;
 565                         status = "disabled";
 566                 };
 567
 568                 uart1: serial@01c28400 {
 569                         compatible = "snps,dw-apb-uart";
 570                         reg = <0x01c28400 0x400>;
 571                         interrupts = <2>;
 572                         reg-shift = <2>;
 573                         reg-io-width = <4>;
 574                         clocks = <&apb1_gates 17>;
 575                         status = "disabled";
 576                 };
 577
 578                 uart2: serial@01c28800 {
 579                         compatible = "snps,dw-apb-uart";
 580                         reg = <0x01c28800 0x400>;
 581                         interrupts = <3>;
 582                         reg-shift = <2>;
 583                         reg-io-width = <4>;
 584                         clocks = <&apb1_gates 18>;
 585                         status = "disabled";
 586                 };
 587
 588                 uart3: serial@01c28c00 {
 589                         compatible = "snps,dw-apb-uart";
 590                         reg = <0x01c28c00 0x400>;
 591                         interrupts = <4>;
 592                         reg-shift = <2>;
 593                         reg-io-width = <4>;
 594                         clocks = <&apb1_gates 19>;
 595                         status = "disabled";
 596                 };
 597
 598                 i2c0: i2c@01c2ac00 {
 599                         #address-cells = <1>;
 600                         #size-cells = <0>;
 601                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 602                         reg = <0x01c2ac00 0x400>;
 603                         interrupts = <7>;
 604                         clocks = <&apb1_gates 0>;
 605                         status = "disabled";
 606                 };
 607
 608                 i2c1: i2c@01c2b000 {
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 612                         reg = <0x01c2b000 0x400>;
 613                         interrupts = <8>;
 614                         clocks = <&apb1_gates 1>;
 615                         status = "disabled";
 616                 };
 617
 618                 i2c2: i2c@01c2b400 {
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 622                         reg = <0x01c2b400 0x400>;
 623                         interrupts = <9>;
 624                         clocks = <&apb1_gates 2>;
 625                         status = "disabled";
 626                 };
 627
 628                 timer@01c60000 {
 629                         compatible = "allwinner,sun5i-a13-hstimer";
 630                         reg = <0x01c60000 0x1000>;
 631                         interrupts = <82>, <83>;
 632                         clocks = <&ahb_gates 28>;
 633                 };
 634         };
 635 };