2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
34 compatible = "arm,cortex-a7";
40 compatible = "arm,cortex-a7";
46 compatible = "arm,cortex-a7";
52 compatible = "arm,cortex-a7";
59 reg = <0x40000000 0x80000000>;
63 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
64 interrupts = <0 120 4>,
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
85 clock-output-names = "osc32k";
90 compatible = "allwinner,sun6i-a31-pll1-clk";
91 reg = <0x01c20000 0x4>;
93 clock-output-names = "pll1";
98 compatible = "allwinner,sun6i-a31-pll6-clk";
99 reg = <0x01c20028 0x4>;
101 clock-output-names = "pll6";
106 compatible = "allwinner,sun4i-a10-cpu-clk";
107 reg = <0x01c20050 0x4>;
110 * PLL1 is listed twice here.
111 * While it looks suspicious, it's actually documented
112 * that way both in the datasheet and in the code from
115 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
116 clock-output-names = "cpu";
121 compatible = "allwinner,sun4i-a10-axi-clk";
122 reg = <0x01c20050 0x4>;
124 clock-output-names = "axi";
127 ahb1_mux: ahb1_mux@01c20054 {
129 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
130 reg = <0x01c20054 0x4>;
131 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
132 clock-output-names = "ahb1_mux";
135 ahb1: ahb1@01c20054 {
137 compatible = "allwinner,sun4i-a10-ahb-clk";
138 reg = <0x01c20054 0x4>;
139 clocks = <&ahb1_mux>;
140 clock-output-names = "ahb1";
143 ahb1_gates: clk@01c20060 {
145 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
146 reg = <0x01c20060 0x8>;
148 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
149 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
150 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
151 "ahb1_nand0", "ahb1_sdram",
152 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
153 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
154 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
155 "ahb1_ehci1", "ahb1_ohci0",
156 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
157 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
158 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
159 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
160 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
161 "ahb1_drc0", "ahb1_drc1";
164 apb1: apb1@01c20054 {
166 compatible = "allwinner,sun4i-a10-apb0-clk";
167 reg = <0x01c20054 0x4>;
169 clock-output-names = "apb1";
172 apb1_gates: clk@01c20068 {
174 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
175 reg = <0x01c20068 0x4>;
177 clock-output-names = "apb1_codec", "apb1_digital_mic",
178 "apb1_pio", "apb1_daudio0",
182 apb2_mux: apb2_mux@01c20058 {
184 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
185 reg = <0x01c20058 0x4>;
186 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
187 clock-output-names = "apb2_mux";
190 apb2: apb2@01c20058 {
192 compatible = "allwinner,sun6i-a31-apb2-div-clk";
193 reg = <0x01c20058 0x4>;
194 clocks = <&apb2_mux>;
195 clock-output-names = "apb2";
198 apb2_gates: clk@01c2006c {
200 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
201 reg = <0x01c2006c 0x4>;
203 clock-output-names = "apb2_i2c0", "apb2_i2c1",
204 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
205 "apb2_uart1", "apb2_uart2", "apb2_uart3",
206 "apb2_uart4", "apb2_uart5";
209 mmc0_clk: clk@01c20088 {
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c20088 0x4>;
213 clocks = <&osc24M>, <&pll6>;
214 clock-output-names = "mmc0";
217 mmc1_clk: clk@01c2008c {
219 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c2008c 0x4>;
221 clocks = <&osc24M>, <&pll6>;
222 clock-output-names = "mmc1";
225 mmc2_clk: clk@01c20090 {
227 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c20090 0x4>;
229 clocks = <&osc24M>, <&pll6>;
230 clock-output-names = "mmc2";
233 mmc3_clk: clk@01c20094 {
235 compatible = "allwinner,sun4i-a10-mod0-clk";
236 reg = <0x01c20094 0x4>;
237 clocks = <&osc24M>, <&pll6>;
238 clock-output-names = "mmc3";
241 spi0_clk: clk@01c200a0 {
243 compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c200a0 0x4>;
245 clocks = <&osc24M>, <&pll6>;
246 clock-output-names = "spi0";
249 spi1_clk: clk@01c200a4 {
251 compatible = "allwinner,sun4i-a10-mod0-clk";
252 reg = <0x01c200a4 0x4>;
253 clocks = <&osc24M>, <&pll6>;
254 clock-output-names = "spi1";
257 spi2_clk: clk@01c200a8 {
259 compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200a8 0x4>;
261 clocks = <&osc24M>, <&pll6>;
262 clock-output-names = "spi2";
265 spi3_clk: clk@01c200ac {
267 compatible = "allwinner,sun4i-a10-mod0-clk";
268 reg = <0x01c200ac 0x4>;
269 clocks = <&osc24M>, <&pll6>;
270 clock-output-names = "spi3";
273 usb_clk: clk@01c200cc {
276 compatible = "allwinner,sun6i-a31-usb-clk";
277 reg = <0x01c200cc 0x4>;
279 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
280 "usb_ohci0", "usb_ohci1",
286 compatible = "simple-bus";
287 #address-cells = <1>;
291 dma: dma-controller@01c02000 {
292 compatible = "allwinner,sun6i-a31-dma";
293 reg = <0x01c02000 0x1000>;
294 interrupts = <0 50 4>;
295 clocks = <&ahb1_gates 6>;
296 resets = <&ahb1_rst 6>;
301 compatible = "allwinner,sun5i-a13-mmc";
302 reg = <0x01c0f000 0x1000>;
303 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
304 clock-names = "ahb", "mmc";
305 resets = <&ahb1_rst 8>;
307 interrupts = <0 60 4>;
312 compatible = "allwinner,sun5i-a13-mmc";
313 reg = <0x01c10000 0x1000>;
314 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
315 clock-names = "ahb", "mmc";
316 resets = <&ahb1_rst 9>;
318 interrupts = <0 61 4>;
323 compatible = "allwinner,sun5i-a13-mmc";
324 reg = <0x01c11000 0x1000>;
325 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
326 clock-names = "ahb", "mmc";
327 resets = <&ahb1_rst 10>;
329 interrupts = <0 62 4>;
334 compatible = "allwinner,sun5i-a13-mmc";
335 reg = <0x01c12000 0x1000>;
336 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
337 clock-names = "ahb", "mmc";
338 resets = <&ahb1_rst 11>;
340 interrupts = <0 63 4>;
344 pio: pinctrl@01c20800 {
345 compatible = "allwinner,sun6i-a31-pinctrl";
346 reg = <0x01c20800 0x400>;
347 interrupts = <0 11 4>,
351 clocks = <&apb1_gates 5>;
353 interrupt-controller;
354 #address-cells = <1>;
358 uart0_pins_a: uart0@0 {
359 allwinner,pins = "PH20", "PH21";
360 allwinner,function = "uart0";
361 allwinner,drive = <0>;
362 allwinner,pull = <0>;
365 i2c0_pins_a: i2c0@0 {
366 allwinner,pins = "PH14", "PH15";
367 allwinner,function = "i2c0";
368 allwinner,drive = <0>;
369 allwinner,pull = <0>;
372 i2c1_pins_a: i2c1@0 {
373 allwinner,pins = "PH16", "PH17";
374 allwinner,function = "i2c1";
375 allwinner,drive = <0>;
376 allwinner,pull = <0>;
379 i2c2_pins_a: i2c2@0 {
380 allwinner,pins = "PH18", "PH19";
381 allwinner,function = "i2c2";
382 allwinner,drive = <0>;
383 allwinner,pull = <0>;
386 mmc0_pins_a: mmc0@0 {
387 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
388 allwinner,function = "mmc0";
389 allwinner,drive = <2>;
390 allwinner,pull = <0>;
394 ahb1_rst: reset@01c202c0 {
396 compatible = "allwinner,sun6i-a31-ahb1-reset";
397 reg = <0x01c202c0 0xc>;
400 apb1_rst: reset@01c202d0 {
402 compatible = "allwinner,sun6i-a31-clock-reset";
403 reg = <0x01c202d0 0x4>;
406 apb2_rst: reset@01c202d8 {
408 compatible = "allwinner,sun6i-a31-clock-reset";
409 reg = <0x01c202d8 0x4>;
413 compatible = "allwinner,sun4i-a10-timer";
414 reg = <0x01c20c00 0xa0>;
415 interrupts = <0 18 4>,
423 wdt1: watchdog@01c20ca0 {
424 compatible = "allwinner,sun6i-a31-wdt";
425 reg = <0x01c20ca0 0x20>;
428 uart0: serial@01c28000 {
429 compatible = "snps,dw-apb-uart";
430 reg = <0x01c28000 0x400>;
431 interrupts = <0 0 4>;
434 clocks = <&apb2_gates 16>;
435 resets = <&apb2_rst 16>;
436 dmas = <&dma 6>, <&dma 6>;
437 dma-names = "rx", "tx";
441 uart1: serial@01c28400 {
442 compatible = "snps,dw-apb-uart";
443 reg = <0x01c28400 0x400>;
444 interrupts = <0 1 4>;
447 clocks = <&apb2_gates 17>;
448 resets = <&apb2_rst 17>;
449 dmas = <&dma 7>, <&dma 7>;
450 dma-names = "rx", "tx";
454 uart2: serial@01c28800 {
455 compatible = "snps,dw-apb-uart";
456 reg = <0x01c28800 0x400>;
457 interrupts = <0 2 4>;
460 clocks = <&apb2_gates 18>;
461 resets = <&apb2_rst 18>;
462 dmas = <&dma 8>, <&dma 8>;
463 dma-names = "rx", "tx";
467 uart3: serial@01c28c00 {
468 compatible = "snps,dw-apb-uart";
469 reg = <0x01c28c00 0x400>;
470 interrupts = <0 3 4>;
473 clocks = <&apb2_gates 19>;
474 resets = <&apb2_rst 19>;
475 dmas = <&dma 9>, <&dma 9>;
476 dma-names = "rx", "tx";
480 uart4: serial@01c29000 {
481 compatible = "snps,dw-apb-uart";
482 reg = <0x01c29000 0x400>;
483 interrupts = <0 4 4>;
486 clocks = <&apb2_gates 20>;
487 resets = <&apb2_rst 20>;
488 dmas = <&dma 10>, <&dma 10>;
489 dma-names = "rx", "tx";
493 uart5: serial@01c29400 {
494 compatible = "snps,dw-apb-uart";
495 reg = <0x01c29400 0x400>;
496 interrupts = <0 5 4>;
499 clocks = <&apb2_gates 21>;
500 resets = <&apb2_rst 21>;
501 dmas = <&dma 22>, <&dma 22>;
502 dma-names = "rx", "tx";
507 compatible = "allwinner,sun6i-a31-i2c";
508 reg = <0x01c2ac00 0x400>;
509 interrupts = <0 6 4>;
510 clocks = <&apb2_gates 0>;
511 clock-frequency = <100000>;
512 resets = <&apb2_rst 0>;
517 compatible = "allwinner,sun6i-a31-i2c";
518 reg = <0x01c2b000 0x400>;
519 interrupts = <0 7 4>;
520 clocks = <&apb2_gates 1>;
521 clock-frequency = <100000>;
522 resets = <&apb2_rst 1>;
527 compatible = "allwinner,sun6i-a31-i2c";
528 reg = <0x01c2b400 0x400>;
529 interrupts = <0 8 4>;
530 clocks = <&apb2_gates 2>;
531 clock-frequency = <100000>;
532 resets = <&apb2_rst 2>;
537 compatible = "allwinner,sun6i-a31-i2c";
538 reg = <0x01c2b800 0x400>;
539 interrupts = <0 9 4>;
540 clocks = <&apb2_gates 3>;
541 clock-frequency = <100000>;
542 resets = <&apb2_rst 3>;
547 compatible = "allwinner,sun6i-a31-spi";
548 reg = <0x01c68000 0x1000>;
549 interrupts = <0 65 4>;
550 clocks = <&ahb1_gates 20>, <&spi0_clk>;
551 clock-names = "ahb", "mod";
552 dmas = <&dma 23>, <&dma 23>;
553 dma-names = "rx", "tx";
554 resets = <&ahb1_rst 20>;
559 compatible = "allwinner,sun6i-a31-spi";
560 reg = <0x01c69000 0x1000>;
561 interrupts = <0 66 4>;
562 clocks = <&ahb1_gates 21>, <&spi1_clk>;
563 clock-names = "ahb", "mod";
564 dmas = <&dma 24>, <&dma 24>;
565 dma-names = "rx", "tx";
566 resets = <&ahb1_rst 21>;
571 compatible = "allwinner,sun6i-a31-spi";
572 reg = <0x01c6a000 0x1000>;
573 interrupts = <0 67 4>;
574 clocks = <&ahb1_gates 22>, <&spi2_clk>;
575 clock-names = "ahb", "mod";
576 dmas = <&dma 25>, <&dma 25>;
577 dma-names = "rx", "tx";
578 resets = <&ahb1_rst 22>;
583 compatible = "allwinner,sun6i-a31-spi";
584 reg = <0x01c6b000 0x1000>;
585 interrupts = <0 68 4>;
586 clocks = <&ahb1_gates 23>, <&spi3_clk>;
587 clock-names = "ahb", "mod";
588 dmas = <&dma 26>, <&dma 26>;
589 dma-names = "rx", "tx";
590 resets = <&ahb1_rst 23>;
594 gic: interrupt-controller@01c81000 {
595 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
596 reg = <0x01c81000 0x1000>,
600 interrupt-controller;
601 #interrupt-cells = <3>;
602 interrupts = <1 9 0xf04>;
605 nmi_intc: interrupt-controller@01f00c0c {
606 compatible = "allwinner,sun6i-a31-sc-nmi";
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 reg = <0x01f00c0c 0x38>;
610 interrupts = <0 32 4>;
614 compatible = "allwinner,sun6i-a31-prcm";
615 reg = <0x01f01400 0x200>;
619 compatible = "allwinner,sun6i-a31-cpuconfig";
620 reg = <0x01f01c00 0x300>;