arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/pinctrl/sun4i-a10.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         compatible = "arm,cortex-a7";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                 };
  60
  61                 cpu@1 {
  62                         compatible = "arm,cortex-a7";
  63                         device_type = "cpu";
  64                         reg = <1>;
  65                 };
  66
  67                 cpu@2 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         reg = <2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                 };
  78         };
  79
  80         timer {
  81                 compatible = "arm,armv7-timer";
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  86         };
  87
  88         clocks {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92
  93                 osc24M: osc24M_clk {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <24000000>;
  97                         clock-output-names = "osc24M";
  98                 };
  99
 100                 osc32k: osc32k_clk {
 101                         #clock-cells = <0>;
 102                         compatible = "fixed-clock";
 103                         clock-frequency = <32768>;
 104                         clock-output-names = "osc32k";
 105                 };
 106
 107                 pll1: clk@01c20000 {
 108                         #clock-cells = <0>;
 109                         compatible = "allwinner,sun8i-a23-pll1-clk";
 110                         reg = <0x01c20000 0x4>;
 111                         clocks = <&osc24M>;
 112                         clock-output-names = "pll1";
 113                 };
 114
 115                 /* dummy clock until actually implemented */
 116                 pll5: pll5_clk {
 117                         #clock-cells = <0>;
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <0>;
 120                         clock-output-names = "pll5";
 121                 };
 122
 123                 pll6: clk@01c20028 {
 124                         #clock-cells = <1>;
 125                         compatible = "allwinner,sun6i-a31-pll6-clk";
 126                         reg = <0x01c20028 0x4>;
 127                         clocks = <&osc24M>;
 128                         clock-output-names = "pll6", "pll6x2";
 129                 };
 130
 131                 pll6d2: pll6d2_clk {
 132                         #clock-cells = <0>;
 133                         compatible = "fixed-factor-clock";
 134                         clock-div = <2>;
 135                         clock-mult = <1>;
 136                         clocks = <&pll6 0>;
 137                         clock-output-names = "pll6d2";
 138                 };
 139
 140                 /* dummy clock until pll6 can be reused */
 141                 pll8: pll8_clk {
 142                         #clock-cells = <0>;
 143                         compatible = "fixed-clock";
 144                         clock-frequency = <1>;
 145                         clock-output-names = "pll8";
 146                 };
 147
 148                 cpu: cpu_clk@01c20050 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-cpu-clk";
 151                         reg = <0x01c20050 0x4>;
 152                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 153                         clock-output-names = "cpu";
 154                 };
 155
 156                 axi: axi_clk@01c20050 {
 157                         #clock-cells = <0>;
 158                         compatible = "allwinner,sun4i-a10-axi-clk";
 159                         reg = <0x01c20050 0x4>;
 160                         clocks = <&cpu>;
 161                         clock-output-names = "axi";
 162                 };
 163
 164                 ahb1: ahb1_clk@01c20054 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 167                         reg = <0x01c20054 0x4>;
 168                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 169                         clock-output-names = "ahb1";
 170                 };
 171
 172                 ahb2: ahb2_clk@01c2005c {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun8i-h3-ahb2-clk";
 175                         reg = <0x01c2005c 0x4>;
 176                         clocks = <&ahb1>, <&pll6d2>;
 177                         clock-output-names = "ahb2";
 178                 };
 179
 180                 apb1: apb1_clk@01c20054 {
 181                         #clock-cells = <0>;
 182                         compatible = "allwinner,sun4i-a10-apb0-clk";
 183                         reg = <0x01c20054 0x4>;
 184                         clocks = <&ahb1>;
 185                         clock-output-names = "apb1";
 186                 };
 187
 188                 apb2: apb2_clk@01c20058 {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun4i-a10-apb1-clk";
 191                         reg = <0x01c20058 0x4>;
 192                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 193                         clock-output-names = "apb2";
 194                 };
 195
 196                 bus_gates: clk@01c20060 {
 197                         #clock-cells = <1>;
 198                         compatible = "allwinner,sun8i-h3-bus-gates-clk";
 199                         reg = <0x01c20060 0x14>;
 200                         clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
 201                         clock-names = "ahb1", "ahb2", "apb1", "apb2";
 202                         clock-indices = <5>, <6>, <8>,
 203                                         <9>, <10>, <13>,
 204                                         <14>, <17>, <18>,
 205                                         <19>, <20>,
 206                                         <21>, <23>,
 207                                         <24>, <25>,
 208                                         <26>, <27>,
 209                                         <28>, <29>,
 210                                         <30>, <31>, <32>,
 211                                         <35>, <36>, <37>,
 212                                         <40>, <41>, <43>,
 213                                         <44>, <52>, <53>,
 214                                         <54>, <64>,
 215                                         <65>, <69>, <72>,
 216                                         <76>, <77>, <78>,
 217                                         <96>, <97>, <98>,
 218                                         <112>, <113>,
 219                                         <114>, <115>,
 220                                         <116>, <128>, <135>;
 221                         clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
 222                                              "bus_mmc1", "bus_mmc2", "bus_nand",
 223                                              "bus_sdram", "bus_gmac", "bus_ts",
 224                                              "bus_hstimer", "bus_spi0",
 225                                              "bus_spi1", "bus_otg",
 226                                              "bus_otg_ehci0", "bus_ehci1",
 227                                              "bus_ehci2", "bus_ehci3",
 228                                              "bus_otg_ohci0", "bus_ohci1",
 229                                              "bus_ohci2", "bus_ohci3", "bus_ve",
 230                                              "bus_lcd0", "bus_lcd1", "bus_deint",
 231                                              "bus_csi", "bus_tve", "bus_hdmi",
 232                                              "bus_de", "bus_gpu", "bus_msgbox",
 233                                              "bus_spinlock", "bus_codec",
 234                                              "bus_spdif", "bus_pio", "bus_ths",
 235                                              "bus_i2s0", "bus_i2s1", "bus_i2s2",
 236                                              "bus_i2c0", "bus_i2c1", "bus_i2c2",
 237                                              "bus_uart0", "bus_uart1",
 238                                              "bus_uart2", "bus_uart3",
 239                                              "bus_scr", "bus_ephy", "bus_dbg";
 240                 };
 241
 242                 mmc0_clk: clk@01c20088 {
 243                         #clock-cells = <1>;
 244                         compatible = "allwinner,sun4i-a10-mmc-clk";
 245                         reg = <0x01c20088 0x4>;
 246                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 247                         clock-output-names = "mmc0",
 248                                              "mmc0_output",
 249                                              "mmc0_sample";
 250                 };
 251
 252                 mmc1_clk: clk@01c2008c {
 253                         #clock-cells = <1>;
 254                         compatible = "allwinner,sun4i-a10-mmc-clk";
 255                         reg = <0x01c2008c 0x4>;
 256                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 257                         clock-output-names = "mmc1",
 258                                              "mmc1_output",
 259                                              "mmc1_sample";
 260                 };
 261
 262                 mmc2_clk: clk@01c20090 {
 263                         #clock-cells = <1>;
 264                         compatible = "allwinner,sun4i-a10-mmc-clk";
 265                         reg = <0x01c20090 0x4>;
 266                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 267                         clock-output-names = "mmc2",
 268                                              "mmc2_output",
 269                                              "mmc2_sample";
 270                 };
 271
 272                 mbus_clk: clk@01c2015c {
 273                         #clock-cells = <0>;
 274                         compatible = "allwinner,sun8i-a23-mbus-clk";
 275                         reg = <0x01c2015c 0x4>;
 276                         clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 277                         clock-output-names = "mbus";
 278                 };
 279
 280                 apb0: apb0_clk {
 281                         compatible = "fixed-factor-clock";
 282                         #clock-cells = <0>;
 283                         clock-div = <1>;
 284                         clock-mult = <1>;
 285                         clocks = <&osc24M>;
 286                         clock-output-names = "apb0";
 287                 };
 288
 289                 apb0_gates: clk@01f01428 {
 290                         compatible = "allwinner,sun8i-h3-apb0-gates-clk",
 291                                      "allwinner,sun4i-a10-gates-clk";
 292                         reg = <0x01f01428 0x4>;
 293                         #clock-cells = <1>;
 294                         clocks = <&apb0>;
 295                         clock-indices = <0>, <1>;
 296                         clock-output-names = "apb0_pio", "apb0_ir";
 297                 };
 298
 299                 ir_clk: ir_clk@01f01454 {
 300                         compatible = "allwinner,sun4i-a10-mod0-clk";
 301                         reg = <0x01f01454 0x4>;
 302                         #clock-cells = <0>;
 303                         clocks = <&osc32k>, <&osc24M>;
 304                         clock-output-names = "ir";
 305                 };
 306         };
 307
 308         soc {
 309                 compatible = "simple-bus";
 310                 #address-cells = <1>;
 311                 #size-cells = <1>;
 312                 ranges;
 313
 314                 dma: dma-controller@01c02000 {
 315                         compatible = "allwinner,sun8i-h3-dma";
 316                         reg = <0x01c02000 0x1000>;
 317                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&bus_gates 6>;
 319                         resets = <&ahb_rst 6>;
 320                         #dma-cells = <1>;
 321                 };
 322
 323                 mmc0: mmc@01c0f000 {
 324                         compatible = "allwinner,sun5i-a13-mmc";
 325                         reg = <0x01c0f000 0x1000>;
 326                         clocks = <&bus_gates 8>,
 327                                  <&mmc0_clk 0>,
 328                                  <&mmc0_clk 1>,
 329                                  <&mmc0_clk 2>;
 330                         clock-names = "ahb",
 331                                       "mmc",
 332                                       "output",
 333                                       "sample";
 334                         resets = <&ahb_rst 8>;
 335                         reset-names = "ahb";
 336                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 337                         status = "disabled";
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                 };
 341
 342                 mmc1: mmc@01c10000 {
 343                         compatible = "allwinner,sun5i-a13-mmc";
 344                         reg = <0x01c10000 0x1000>;
 345                         clocks = <&bus_gates 9>,
 346                                  <&mmc1_clk 0>,
 347                                  <&mmc1_clk 1>,
 348                                  <&mmc1_clk 2>;
 349                         clock-names = "ahb",
 350                                       "mmc",
 351                                       "output",
 352                                       "sample";
 353                         resets = <&ahb_rst 9>;
 354                         reset-names = "ahb";
 355                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 356                         status = "disabled";
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                 };
 360
 361                 mmc2: mmc@01c11000 {
 362                         compatible = "allwinner,sun5i-a13-mmc";
 363                         reg = <0x01c11000 0x1000>;
 364                         clocks = <&bus_gates 10>,
 365                                  <&mmc2_clk 0>,
 366                                  <&mmc2_clk 1>,
 367                                  <&mmc2_clk 2>;
 368                         clock-names = "ahb",
 369                                       "mmc",
 370                                       "output",
 371                                       "sample";
 372                         resets = <&ahb_rst 10>;
 373                         reset-names = "ahb";
 374                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 375                         status = "disabled";
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                 };
 379
 380                 pio: pinctrl@01c20800 {
 381                         compatible = "allwinner,sun8i-h3-pinctrl";
 382                         reg = <0x01c20800 0x400>;
 383                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 384                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&bus_gates 69>;
 386                         gpio-controller;
 387                         #gpio-cells = <3>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <3>;
 390
 391                         uart0_pins_a: uart0@0 {
 392                                 allwinner,pins = "PA4", "PA5";
 393                                 allwinner,function = "uart0";
 394                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 395                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 396                         };
 397
 398                         mmc0_pins_a: mmc0@0 {
 399                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 400                                                  "PF4", "PF5";
 401                                 allwinner,function = "mmc0";
 402                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 403                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 404                         };
 405
 406                         mmc0_cd_pin: mmc0_cd_pin@0 {
 407                                 allwinner,pins = "PF6";
 408                                 allwinner,function = "gpio_in";
 409                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 410                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 411                         };
 412
 413                         mmc1_pins_a: mmc1@0 {
 414                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 415                                                  "PG4", "PG5";
 416                                 allwinner,function = "mmc1";
 417                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 418                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 419                         };
 420                 };
 421
 422                 ahb_rst: reset@01c202c0 {
 423                         #reset-cells = <1>;
 424                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 425                         reg = <0x01c202c0 0xc>;
 426                 };
 427
 428                 apb1_rst: reset@01c202d0 {
 429                         #reset-cells = <1>;
 430                         compatible = "allwinner,sun6i-a31-clock-reset";
 431                         reg = <0x01c202d0 0x4>;
 432                 };
 433
 434                 apb2_rst: reset@01c202d8 {
 435                         #reset-cells = <1>;
 436                         compatible = "allwinner,sun6i-a31-clock-reset";
 437                         reg = <0x01c202d8 0x4>;
 438                 };
 439
 440                 timer@01c20c00 {
 441                         compatible = "allwinner,sun4i-a10-timer";
 442                         reg = <0x01c20c00 0xa0>;
 443                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 444                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&osc24M>;
 446                 };
 447
 448                 wdt0: watchdog@01c20ca0 {
 449                         compatible = "allwinner,sun6i-a31-wdt";
 450                         reg = <0x01c20ca0 0x20>;
 451                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 452                 };
 453
 454                 uart0: serial@01c28000 {
 455                         compatible = "snps,dw-apb-uart";
 456                         reg = <0x01c28000 0x400>;
 457                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 458                         reg-shift = <2>;
 459                         reg-io-width = <4>;
 460                         clocks = <&bus_gates 112>;
 461                         resets = <&apb2_rst 16>;
 462                         dmas = <&dma 6>, <&dma 6>;
 463                         dma-names = "rx", "tx";
 464                         status = "disabled";
 465                 };
 466
 467                 uart1: serial@01c28400 {
 468                         compatible = "snps,dw-apb-uart";
 469                         reg = <0x01c28400 0x400>;
 470                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 471                         reg-shift = <2>;
 472                         reg-io-width = <4>;
 473                         clocks = <&bus_gates 113>;
 474                         resets = <&apb2_rst 17>;
 475                         dmas = <&dma 7>, <&dma 7>;
 476                         dma-names = "rx", "tx";
 477                         status = "disabled";
 478                 };
 479
 480                 uart2: serial@01c28800 {
 481                         compatible = "snps,dw-apb-uart";
 482                         reg = <0x01c28800 0x400>;
 483                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 484                         reg-shift = <2>;
 485                         reg-io-width = <4>;
 486                         clocks = <&bus_gates 114>;
 487                         resets = <&apb2_rst 18>;
 488                         dmas = <&dma 8>, <&dma 8>;
 489                         dma-names = "rx", "tx";
 490                         status = "disabled";
 491                 };
 492
 493                 uart3: serial@01c28c00 {
 494                         compatible = "snps,dw-apb-uart";
 495                         reg = <0x01c28c00 0x400>;
 496                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 497                         reg-shift = <2>;
 498                         reg-io-width = <4>;
 499                         clocks = <&bus_gates 115>;
 500                         resets = <&apb2_rst 19>;
 501                         dmas = <&dma 9>, <&dma 9>;
 502                         dma-names = "rx", "tx";
 503                         status = "disabled";
 504                 };
 505
 506                 gic: interrupt-controller@01c81000 {
 507                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 508                         reg = <0x01c81000 0x1000>,
 509                               <0x01c82000 0x1000>,
 510                               <0x01c84000 0x2000>,
 511                               <0x01c86000 0x2000>;
 512                         interrupt-controller;
 513                         #interrupt-cells = <3>;
 514                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 515                 };
 516
 517                 rtc: rtc@01f00000 {
 518                         compatible = "allwinner,sun6i-a31-rtc";
 519                         reg = <0x01f00000 0x54>;
 520                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 522                 };
 523
 524                 apb0_reset: reset@01f014b0 {
 525                         reg = <0x01f014b0 0x4>;
 526                         compatible = "allwinner,sun6i-a31-clock-reset";
 527                         #reset-cells = <1>;
 528                 };
 529
 530                 ir: ir@01f02000 {
 531                         compatible = "allwinner,sun5i-a13-ir";
 532                         clocks = <&apb0_gates 1>, <&ir_clk>;
 533                         clock-names = "apb", "ir";
 534                         resets = <&apb0_reset 1>;
 535                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 536                         reg = <0x01f02000 0x40>;
 537                         status = "disabled";
 538                 };
 539
 540                 r_pio: pinctrl@01f02c00 {
 541                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 542                         reg = <0x01f02c00 0x400>;
 543                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&apb0_gates 0>;
 545                         resets = <&apb0_reset 0>;
 546                         gpio-controller;
 547                         #gpio-cells = <3>;
 548                         interrupt-controller;
 549                         #interrupt-cells = <3>;
 550
 551                         ir_pins_a: ir@0 {
 552                                 allwinner,pins = "PL11";
 553                                 allwinner,function = "s_cir_rx";
 554                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 555                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 556                         };
 557                 };
 558         };
 559 };