arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton64.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a7";
  60                         device_type = "cpu";
  61                         reg = <0x0>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0x1>;
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "arm,cortex-a7";
  72                         device_type = "cpu";
  73                         reg = <0x2>;
  74                 };
  75
  76                 cpu3: cpu@3 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0x3>;
  80                 };
  81
  82                 cpu4: cpu@100 {
  83                         compatible = "arm,cortex-a15";
  84                         device_type = "cpu";
  85                         reg = <0x100>;
  86                 };
  87
  88                 cpu5: cpu@101 {
  89                         compatible = "arm,cortex-a15";
  90                         device_type = "cpu";
  91                         reg = <0x101>;
  92                 };
  93
  94                 cpu6: cpu@102 {
  95                         compatible = "arm,cortex-a15";
  96                         device_type = "cpu";
  97                         reg = <0x102>;
  98                 };
  99
 100                 cpu7: cpu@103 {
 101                         compatible = "arm,cortex-a15";
 102                         device_type = "cpu";
 103                         reg = <0x103>;
 104                 };
 105         };
 106
 107         memory {
 108                 /* 8GB max. with LPAE */
 109                 reg = <0 0x20000000 0x02 0>;
 110         };
 111
 112         timer {
 113                 compatible = "arm,armv7-timer";
 114                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 118                 clock-frequency = <24000000>;
 119                 arm,cpu-registers-not-fw-configured;
 120         };
 121
 122         clocks {
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 /*
 126                  * map 64 bit address range down to 32 bits,
 127                  * as the peripherals are all under 512MB.
 128                  */
 129                 ranges = <0 0 0 0x20000000>;
 130
 131                 osc24M: osc24M_clk {
 132                         #clock-cells = <0>;
 133                         compatible = "fixed-clock";
 134                         clock-frequency = <24000000>;
 135                         clock-output-names = "osc24M";
 136                 };
 137
 138                 osc32k: osc32k_clk {
 139                         #clock-cells = <0>;
 140                         compatible = "fixed-clock";
 141                         clock-frequency = <32768>;
 142                         clock-output-names = "osc32k";
 143                 };
 144
 145                 usb_mod_clk: clk@00a08000 {
 146                         #clock-cells = <1>;
 147                         #reset-cells = <1>;
 148                         compatible = "allwinner,sun9i-a80-usb-mod-clk";
 149                         reg = <0x00a08000 0x4>;
 150                         clocks = <&ahb1_gates 1>;
 151                         clock-output-names = "usb0_ahb", "usb_ohci0",
 152                                              "usb1_ahb", "usb_ohci1",
 153                                              "usb2_ahb", "usb_ohci2";
 154                 };
 155
 156                 usb_phy_clk: clk@00a08004 {
 157                         #clock-cells = <1>;
 158                         #reset-cells = <1>;
 159                         compatible = "allwinner,sun9i-a80-usb-phy-clk";
 160                         reg = <0x00a08004 0x4>;
 161                         clocks = <&ahb1_gates 1>;
 162                         clock-output-names = "usb_phy0", "usb_hsic1_480M",
 163                                              "usb_phy1", "usb_hsic2_480M",
 164                                              "usb_phy2", "usb_hsic_12M";
 165                 };
 166
 167                 pll3: clk@06000008 {
 168                         /* placeholder until implemented */
 169                         #clock-cells = <0>;
 170                         compatible = "fixed-clock";
 171                         clock-rate = <0>;
 172                         clock-output-names = "pll3";
 173                 };
 174
 175                 pll4: clk@0600000c {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun9i-a80-pll4-clk";
 178                         reg = <0x0600000c 0x4>;
 179                         clocks = <&osc24M>;
 180                         clock-output-names = "pll4";
 181                 };
 182
 183                 pll12: clk@0600002c {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun9i-a80-pll4-clk";
 186                         reg = <0x0600002c 0x4>;
 187                         clocks = <&osc24M>;
 188                         clock-output-names = "pll12";
 189                 };
 190
 191                 gt_clk: clk@0600005c {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun9i-a80-gt-clk";
 194                         reg = <0x0600005c 0x4>;
 195                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 196                         clock-output-names = "gt";
 197                 };
 198
 199                 ahb0: clk@06000060 {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun9i-a80-ahb-clk";
 202                         reg = <0x06000060 0x4>;
 203                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 204                         clock-output-names = "ahb0";
 205                 };
 206
 207                 ahb1: clk@06000064 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun9i-a80-ahb-clk";
 210                         reg = <0x06000064 0x4>;
 211                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 212                         clock-output-names = "ahb1";
 213                 };
 214
 215                 ahb2: clk@06000068 {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun9i-a80-ahb-clk";
 218                         reg = <0x06000068 0x4>;
 219                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 220                         clock-output-names = "ahb2";
 221                 };
 222
 223                 apb0: clk@06000070 {
 224                         #clock-cells = <0>;
 225                         compatible = "allwinner,sun9i-a80-apb0-clk";
 226                         reg = <0x06000070 0x4>;
 227                         clocks = <&osc24M>, <&pll4>;
 228                         clock-output-names = "apb0";
 229                 };
 230
 231                 apb1: clk@06000074 {
 232                         #clock-cells = <0>;
 233                         compatible = "allwinner,sun9i-a80-apb1-clk";
 234                         reg = <0x06000074 0x4>;
 235                         clocks = <&osc24M>, <&pll4>;
 236                         clock-output-names = "apb1";
 237                 };
 238
 239                 cci400_clk: clk@06000078 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun9i-a80-gt-clk";
 242                         reg = <0x06000078 0x4>;
 243                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 244                         clock-output-names = "cci400";
 245                 };
 246
 247                 mmc0_clk: clk@06000410 {
 248                         #clock-cells = <1>;
 249                         compatible = "allwinner,sun9i-a80-mmc-clk";
 250                         reg = <0x06000410 0x4>;
 251                         clocks = <&osc24M>, <&pll4>;
 252                         clock-output-names = "mmc0", "mmc0_output",
 253                                              "mmc0_sample";
 254                 };
 255
 256                 mmc1_clk: clk@06000414 {
 257                         #clock-cells = <1>;
 258                         compatible = "allwinner,sun9i-a80-mmc-clk";
 259                         reg = <0x06000414 0x4>;
 260                         clocks = <&osc24M>, <&pll4>;
 261                         clock-output-names = "mmc1", "mmc1_output",
 262                                              "mmc1_sample";
 263                 };
 264
 265                 mmc2_clk: clk@06000418 {
 266                         #clock-cells = <1>;
 267                         compatible = "allwinner,sun9i-a80-mmc-clk";
 268                         reg = <0x06000418 0x4>;
 269                         clocks = <&osc24M>, <&pll4>;
 270                         clock-output-names = "mmc2", "mmc2_output",
 271                                              "mmc2_sample";
 272                 };
 273
 274                 mmc3_clk: clk@0600041c {
 275                         #clock-cells = <1>;
 276                         compatible = "allwinner,sun9i-a80-mmc-clk";
 277                         reg = <0x0600041c 0x4>;
 278                         clocks = <&osc24M>, <&pll4>;
 279                         clock-output-names = "mmc3", "mmc3_output",
 280                                              "mmc3_sample";
 281                 };
 282
 283                 ahb0_gates: clk@06000580 {
 284                         #clock-cells = <1>;
 285                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 286                         reg = <0x06000580 0x4>;
 287                         clocks = <&ahb0>;
 288                         clock-indices = <0>, <1>, <3>,
 289                                         <5>, <8>, <12>,
 290                                         <13>, <14>,
 291                                         <15>, <16>, <18>,
 292                                         <20>, <21>, <22>,
 293                                         <23>;
 294                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 295                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 296                                         "ahb0_nand0", "ahb0_sdram",
 297                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 298                                         "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
 299                                         "ahb0_spi3";
 300                 };
 301
 302                 ahb1_gates: clk@06000584 {
 303                         #clock-cells = <1>;
 304                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 305                         reg = <0x06000584 0x4>;
 306                         clocks = <&ahb1>;
 307                         clock-indices = <0>, <1>,
 308                                         <17>, <21>,
 309                                         <22>, <23>,
 310                                         <24>;
 311                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 312                                         "ahb1_gmac", "ahb1_msgbox",
 313                                         "ahb1_spinlock", "ahb1_hstimer",
 314                                         "ahb1_dma";
 315                 };
 316
 317                 ahb2_gates: clk@06000588 {
 318                         #clock-cells = <1>;
 319                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 320                         reg = <0x06000588 0x4>;
 321                         clocks = <&ahb2>;
 322                         clock-indices = <0>, <1>,
 323                                         <2>, <4>, <5>,
 324                                         <7>, <8>, <11>;
 325                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 326                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 327                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 328                 };
 329
 330                 apb0_gates: clk@06000590 {
 331                         #clock-cells = <1>;
 332                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 333                         reg = <0x06000590 0x4>;
 334                         clocks = <&apb0>;
 335                         clock-indices = <1>, <5>,
 336                                         <11>, <12>, <13>,
 337                                         <15>, <17>, <18>,
 338                                         <19>;
 339                         clock-output-names = "apb0_spdif", "apb0_pio",
 340                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 341                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 342                                         "apb0_cirtx";
 343                 };
 344
 345                 apb1_gates: clk@06000594 {
 346                         #clock-cells = <1>;
 347                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 348                         reg = <0x06000594 0x4>;
 349                         clocks = <&apb1>;
 350                         clock-indices = <0>, <1>,
 351                                         <2>, <3>, <4>,
 352                                         <16>, <17>,
 353                                         <18>, <19>,
 354                                         <20>, <21>;
 355                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 356                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 357                                         "apb1_uart0", "apb1_uart1",
 358                                         "apb1_uart2", "apb1_uart3",
 359                                         "apb1_uart4", "apb1_uart5";
 360                 };
 361
 362                 cpus_clk: clk@08001410 {
 363                         compatible = "allwinner,sun9i-a80-cpus-clk";
 364                         reg = <0x08001410 0x4>;
 365                         #clock-cells = <0>;
 366                         clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
 367                         clock-output-names = "cpus";
 368                 };
 369
 370                 ahbs: ahbs_clk {
 371                         compatible = "fixed-factor-clock";
 372                         #clock-cells = <0>;
 373                         clock-div = <1>;
 374                         clock-mult = <1>;
 375                         clocks = <&cpus_clk>;
 376                         clock-output-names = "ahbs";
 377                 };
 378
 379                 apbs: clk@0800141c {
 380                         compatible = "allwinner,sun8i-a23-apb0-clk";
 381                         reg = <0x0800141c 0x4>;
 382                         #clock-cells = <0>;
 383                         clocks = <&ahbs>;
 384                         clock-output-names = "apbs";
 385                 };
 386
 387                 apbs_gates: clk@08001428 {
 388                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 389                         reg = <0x08001428 0x4>;
 390                         #clock-cells = <1>;
 391                         clocks = <&apbs>;
 392                         clock-indices = <0>, <1>,
 393                                         <2>, <3>,
 394                                         <4>, <5>,
 395                                         <6>, <7>,
 396                                         <12>, <13>,
 397                                         <16>, <17>,
 398                                         <18>, <20>;
 399                         clock-output-names = "apbs_pio", "apbs_ir",
 400                                         "apbs_timer", "apbs_rsb",
 401                                         "apbs_uart", "apbs_1wire",
 402                                         "apbs_i2c0", "apbs_i2c1",
 403                                         "apbs_ps2_0", "apbs_ps2_1",
 404                                         "apbs_dma", "apbs_i2s0",
 405                                         "apbs_i2s1", "apbs_twd";
 406                 };
 407
 408                 r_1wire_clk: clk@08001450 {
 409                         reg = <0x08001450 0x4>;
 410                         #clock-cells = <0>;
 411                         compatible = "allwinner,sun4i-a10-mod0-clk";
 412                         clocks = <&osc32k>, <&osc24M>;
 413                         clock-output-names = "r_1wire";
 414                 };
 415
 416                 r_ir_clk: clk@08001454 {
 417                         reg = <0x08001454 0x4>;
 418                         #clock-cells = <0>;
 419                         compatible = "allwinner,sun4i-a10-mod0-clk";
 420                         clocks = <&osc32k>, <&osc24M>;
 421                         clock-output-names = "r_ir";
 422                 };
 423         };
 424
 425         soc {
 426                 compatible = "simple-bus";
 427                 #address-cells = <1>;
 428                 #size-cells = <1>;
 429                 /*
 430                  * map 64 bit address range down to 32 bits,
 431                  * as the peripherals are all under 512MB.
 432                  */
 433                 ranges = <0 0 0 0x20000000>;
 434
 435                 ehci0: usb@00a00000 {
 436                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 437                         reg = <0x00a00000 0x100>;
 438                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&usb_mod_clk 1>;
 440                         resets = <&usb_mod_clk 17>;
 441                         phys = <&usbphy1>;
 442                         phy-names = "usb";
 443                         status = "disabled";
 444                 };
 445
 446                 ohci0: usb@00a00400 {
 447                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 448                         reg = <0x00a00400 0x100>;
 449                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 450                         clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
 451                         resets = <&usb_mod_clk 17>;
 452                         phys = <&usbphy1>;
 453                         phy-names = "usb";
 454                         status = "disabled";
 455                 };
 456
 457                 usbphy1: phy@00a00800 {
 458                         compatible = "allwinner,sun9i-a80-usb-phy";
 459                         reg = <0x00a00800 0x4>;
 460                         clocks = <&usb_phy_clk 1>;
 461                         clock-names = "phy";
 462                         resets = <&usb_phy_clk 17>;
 463                         reset-names = "phy";
 464                         status = "disabled";
 465                         #phy-cells = <0>;
 466                 };
 467
 468                 ehci1: usb@00a01000 {
 469                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 470                         reg = <0x00a01000 0x100>;
 471                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&usb_mod_clk 3>;
 473                         resets = <&usb_mod_clk 18>;
 474                         phys = <&usbphy2>;
 475                         phy-names = "usb";
 476                         status = "disabled";
 477                 };
 478
 479                 usbphy2: phy@00a01800 {
 480                         compatible = "allwinner,sun9i-a80-usb-phy";
 481                         reg = <0x00a01800 0x4>;
 482                         clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
 483                                  <&usb_phy_clk 3>;
 484                         clock-names = "hsic_480M", "hsic_12M", "phy";
 485                         resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
 486                         reset-names = "hsic", "phy";
 487                         status = "disabled";
 488                         #phy-cells = <0>;
 489                         /* usb1 is always used with HSIC */
 490                         phy_type = "hsic";
 491                 };
 492
 493                 ehci2: usb@00a02000 {
 494                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 495                         reg = <0x00a02000 0x100>;
 496                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&usb_mod_clk 5>;
 498                         resets = <&usb_mod_clk 19>;
 499                         phys = <&usbphy3>;
 500                         phy-names = "usb";
 501                         status = "disabled";
 502                 };
 503
 504                 ohci2: usb@00a02400 {
 505                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 506                         reg = <0x00a02400 0x100>;
 507                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
 509                         resets = <&usb_mod_clk 19>;
 510                         phys = <&usbphy3>;
 511                         phy-names = "usb";
 512                         status = "disabled";
 513                 };
 514
 515                 usbphy3: phy@00a02800 {
 516                         compatible = "allwinner,sun9i-a80-usb-phy";
 517                         reg = <0x00a02800 0x4>;
 518                         clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
 519                                  <&usb_phy_clk 5>;
 520                         clock-names = "hsic_480M", "hsic_12M", "phy";
 521                         resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
 522                         reset-names = "hsic", "phy";
 523                         status = "disabled";
 524                         #phy-cells = <0>;
 525                 };
 526
 527                 mmc0: mmc@01c0f000 {
 528                         compatible = "allwinner,sun5i-a13-mmc";
 529                         reg = <0x01c0f000 0x1000>;
 530                         clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 531                                  <&mmc0_clk 1>, <&mmc0_clk 2>;
 532                         clock-names = "ahb", "mmc", "output", "sample";
 533                         resets = <&mmc_config_clk 0>;
 534                         reset-names = "ahb";
 535                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 536                         status = "disabled";
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                 };
 540
 541                 mmc1: mmc@01c10000 {
 542                         compatible = "allwinner,sun5i-a13-mmc";
 543                         reg = <0x01c10000 0x1000>;
 544                         clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 545                                  <&mmc1_clk 1>, <&mmc1_clk 2>;
 546                         clock-names = "ahb", "mmc", "output", "sample";
 547                         resets = <&mmc_config_clk 1>;
 548                         reset-names = "ahb";
 549                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 550                         status = "disabled";
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                 };
 554
 555                 mmc2: mmc@01c11000 {
 556                         compatible = "allwinner,sun5i-a13-mmc";
 557                         reg = <0x01c11000 0x1000>;
 558                         clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 559                                  <&mmc2_clk 1>, <&mmc2_clk 2>;
 560                         clock-names = "ahb", "mmc", "output", "sample";
 561                         resets = <&mmc_config_clk 2>;
 562                         reset-names = "ahb";
 563                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 564                         status = "disabled";
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                 };
 568
 569                 mmc3: mmc@01c12000 {
 570                         compatible = "allwinner,sun5i-a13-mmc";
 571                         reg = <0x01c12000 0x1000>;
 572                         clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 573                                  <&mmc3_clk 1>, <&mmc3_clk 2>;
 574                         clock-names = "ahb", "mmc", "output", "sample";
 575                         resets = <&mmc_config_clk 3>;
 576                         reset-names = "ahb";
 577                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 578                         status = "disabled";
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                 };
 582
 583                 mmc_config_clk: clk@01c13000 {
 584                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 585                         reg = <0x01c13000 0x10>;
 586                         clocks = <&ahb0_gates 8>;
 587                         clock-names = "ahb";
 588                         resets = <&ahb0_resets 8>;
 589                         reset-names = "ahb";
 590                         #clock-cells = <1>;
 591                         #reset-cells = <1>;
 592                         clock-output-names = "mmc0_config", "mmc1_config",
 593                                              "mmc2_config", "mmc3_config";
 594                 };
 595
 596                 gic: interrupt-controller@01c41000 {
 597                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 598                         reg = <0x01c41000 0x1000>,
 599                               <0x01c42000 0x1000>,
 600                               <0x01c44000 0x2000>,
 601                               <0x01c46000 0x2000>;
 602                         interrupt-controller;
 603                         #interrupt-cells = <3>;
 604                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 605                 };
 606
 607                 ahb0_resets: reset@060005a0 {
 608                         #reset-cells = <1>;
 609                         compatible = "allwinner,sun6i-a31-clock-reset";
 610                         reg = <0x060005a0 0x4>;
 611                 };
 612
 613                 ahb1_resets: reset@060005a4 {
 614                         #reset-cells = <1>;
 615                         compatible = "allwinner,sun6i-a31-clock-reset";
 616                         reg = <0x060005a4 0x4>;
 617                 };
 618
 619                 ahb2_resets: reset@060005a8 {
 620                         #reset-cells = <1>;
 621                         compatible = "allwinner,sun6i-a31-clock-reset";
 622                         reg = <0x060005a8 0x4>;
 623                 };
 624
 625                 apb0_resets: reset@060005b0 {
 626                         #reset-cells = <1>;
 627                         compatible = "allwinner,sun6i-a31-clock-reset";
 628                         reg = <0x060005b0 0x4>;
 629                 };
 630
 631                 apb1_resets: reset@060005b4 {
 632                         #reset-cells = <1>;
 633                         compatible = "allwinner,sun6i-a31-clock-reset";
 634                         reg = <0x060005b4 0x4>;
 635                 };
 636
 637                 timer@06000c00 {
 638                         compatible = "allwinner,sun4i-a10-timer";
 639                         reg = <0x06000c00 0xa0>;
 640                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 646
 647                         clocks = <&osc24M>;
 648                 };
 649
 650                 wdt: watchdog@06000ca0 {
 651                         compatible = "allwinner,sun6i-a31-wdt";
 652                         reg = <0x06000ca0 0x20>;
 653                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 654                 };
 655
 656                 pio: pinctrl@06000800 {
 657                         compatible = "allwinner,sun9i-a80-pinctrl";
 658                         reg = <0x06000800 0x400>;
 659                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 664                         clocks = <&apb0_gates 5>;
 665                         gpio-controller;
 666                         interrupt-controller;
 667                         #interrupt-cells = <3>;
 668                         #size-cells = <0>;
 669                         #gpio-cells = <3>;
 670
 671                         i2c3_pins_a: i2c3@0 {
 672                                 allwinner,pins = "PG10", "PG11";
 673                                 allwinner,function = "i2c3";
 674                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 675                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 676                         };
 677
 678                         mmc0_pins: mmc0 {
 679                                 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
 680                                                  "PF4", "PF5";
 681                                 allwinner,function = "mmc0";
 682                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 683                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 684                         };
 685
 686                         mmc2_8bit_pins: mmc2_8bit {
 687                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 688                                                  "PC10", "PC11", "PC12",
 689                                                  "PC13", "PC14", "PC15";
 690                                 allwinner,function = "mmc2";
 691                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 692                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 693                         };
 694
 695                         uart0_pins_a: uart0@0 {
 696                                 allwinner,pins = "PH12", "PH13";
 697                                 allwinner,function = "uart0";
 698                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 699                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 700                         };
 701
 702                         uart4_pins_a: uart4@0 {
 703                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 704                                 allwinner,function = "uart4";
 705                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 706                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 707                         };
 708                 };
 709
 710                 uart0: serial@07000000 {
 711                         compatible = "snps,dw-apb-uart";
 712                         reg = <0x07000000 0x400>;
 713                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 714                         reg-shift = <2>;
 715                         reg-io-width = <4>;
 716                         clocks = <&apb1_gates 16>;
 717                         resets = <&apb1_resets 16>;
 718                         status = "disabled";
 719                 };
 720
 721                 uart1: serial@07000400 {
 722                         compatible = "snps,dw-apb-uart";
 723                         reg = <0x07000400 0x400>;
 724                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 725                         reg-shift = <2>;
 726                         reg-io-width = <4>;
 727                         clocks = <&apb1_gates 17>;
 728                         resets = <&apb1_resets 17>;
 729                         status = "disabled";
 730                 };
 731
 732                 uart2: serial@07000800 {
 733                         compatible = "snps,dw-apb-uart";
 734                         reg = <0x07000800 0x400>;
 735                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 736                         reg-shift = <2>;
 737                         reg-io-width = <4>;
 738                         clocks = <&apb1_gates 18>;
 739                         resets = <&apb1_resets 18>;
 740                         status = "disabled";
 741                 };
 742
 743                 uart3: serial@07000c00 {
 744                         compatible = "snps,dw-apb-uart";
 745                         reg = <0x07000c00 0x400>;
 746                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 747                         reg-shift = <2>;
 748                         reg-io-width = <4>;
 749                         clocks = <&apb1_gates 19>;
 750                         resets = <&apb1_resets 19>;
 751                         status = "disabled";
 752                 };
 753
 754                 uart4: serial@07001000 {
 755                         compatible = "snps,dw-apb-uart";
 756                         reg = <0x07001000 0x400>;
 757                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 758                         reg-shift = <2>;
 759                         reg-io-width = <4>;
 760                         clocks = <&apb1_gates 20>;
 761                         resets = <&apb1_resets 20>;
 762                         status = "disabled";
 763                 };
 764
 765                 uart5: serial@07001400 {
 766                         compatible = "snps,dw-apb-uart";
 767                         reg = <0x07001400 0x400>;
 768                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 769                         reg-shift = <2>;
 770                         reg-io-width = <4>;
 771                         clocks = <&apb1_gates 21>;
 772                         resets = <&apb1_resets 21>;
 773                         status = "disabled";
 774                 };
 775
 776                 i2c0: i2c@07002800 {
 777                         compatible = "allwinner,sun6i-a31-i2c";
 778                         reg = <0x07002800 0x400>;
 779                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 780                         clocks = <&apb1_gates 0>;
 781                         resets = <&apb1_resets 0>;
 782                         status = "disabled";
 783                         #address-cells = <1>;
 784                         #size-cells = <0>;
 785                 };
 786
 787                 i2c1: i2c@07002c00 {
 788                         compatible = "allwinner,sun6i-a31-i2c";
 789                         reg = <0x07002c00 0x400>;
 790                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 791                         clocks = <&apb1_gates 1>;
 792                         resets = <&apb1_resets 1>;
 793                         status = "disabled";
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796                 };
 797
 798                 i2c2: i2c@07003000 {
 799                         compatible = "allwinner,sun6i-a31-i2c";
 800                         reg = <0x07003000 0x400>;
 801                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 802                         clocks = <&apb1_gates 2>;
 803                         resets = <&apb1_resets 2>;
 804                         status = "disabled";
 805                         #address-cells = <1>;
 806                         #size-cells = <0>;
 807                 };
 808
 809                 i2c3: i2c@07003400 {
 810                         compatible = "allwinner,sun6i-a31-i2c";
 811                         reg = <0x07003400 0x400>;
 812                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 813                         clocks = <&apb1_gates 3>;
 814                         resets = <&apb1_resets 3>;
 815                         status = "disabled";
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                 };
 819
 820                 i2c4: i2c@07003800 {
 821                         compatible = "allwinner,sun6i-a31-i2c";
 822                         reg = <0x07003800 0x400>;
 823                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&apb1_gates 4>;
 825                         resets = <&apb1_resets 4>;
 826                         status = "disabled";
 827                         #address-cells = <1>;
 828                         #size-cells = <0>;
 829                 };
 830
 831                 r_wdt: watchdog@08001000 {
 832                         compatible = "allwinner,sun6i-a31-wdt";
 833                         reg = <0x08001000 0x20>;
 834                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 835                 };
 836
 837                 apbs_rst: reset@080014b0 {
 838                         reg = <0x080014b0 0x4>;
 839                         compatible = "allwinner,sun6i-a31-clock-reset";
 840                         #reset-cells = <1>;
 841                 };
 842
 843                 r_uart: serial@08002800 {
 844                         compatible = "snps,dw-apb-uart";
 845                         reg = <0x08002800 0x400>;
 846                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 847                         reg-shift = <2>;
 848                         reg-io-width = <4>;
 849                         clocks = <&apbs_gates 4>;
 850                         resets = <&apbs_rst 4>;
 851                         status = "disabled";
 852                 };
 853         };
 854 };