arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra124";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         host1x@0,50000000 {
  15                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  16                 reg = <0x0 0x50000000 0x0 0x00034000>;
  17                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  18                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  19                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  20                 resets = <&tegra_car 28>;
  21                 reset-names = "host1x";
  22
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25
  26                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  27
  28                 dc@0,54200000 {
  29                         compatible = "nvidia,tegra124-dc";
  30                         reg = <0x0 0x54200000 0x0 0x00040000>;
  31                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
  33                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  34                         clock-names = "dc", "parent";
  35                         resets = <&tegra_car 27>;
  36                         reset-names = "dc";
  37
  38                         nvidia,head = <0>;
  39                 };
  40
  41                 dc@0,54240000 {
  42                         compatible = "nvidia,tegra124-dc";
  43                         reg = <0x0 0x54240000 0x0 0x00040000>;
  44                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
  46                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  47                         clock-names = "dc", "parent";
  48                         resets = <&tegra_car 26>;
  49                         reset-names = "dc";
  50
  51                         nvidia,head = <1>;
  52                 };
  53
  54                 hdmi@0,54280000 {
  55                         compatible = "nvidia,tegra124-hdmi";
  56                         reg = <0x0 0x54280000 0x0 0x00040000>;
  57                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  58                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
  59                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
  60                         clock-names = "hdmi", "parent";
  61                         resets = <&tegra_car 51>;
  62                         reset-names = "hdmi";
  63                         status = "disabled";
  64                 };
  65
  66                 sor@0,54540000 {
  67                         compatible = "nvidia,tegra124-sor";
  68                         reg = <0x0 0x54540000 0x0 0x00040000>;
  69                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  70                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
  71                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
  72                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
  73                                  <&tegra_car TEGRA124_CLK_CLK_M>;
  74                         clock-names = "sor", "parent", "dp", "safe";
  75                         resets = <&tegra_car 182>;
  76                         reset-names = "sor";
  77                         status = "disabled";
  78                 };
  79
  80                 dpaux@0,545c0000 {
  81                         compatible = "nvidia,tegra124-dpaux";
  82                         reg = <0x0 0x545c0000 0x0 0x00040000>;
  83                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  84                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
  85                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
  86                         clock-names = "dpaux", "parent";
  87                         resets = <&tegra_car 181>;
  88                         reset-names = "dpaux";
  89                         status = "disabled";
  90                 };
  91         };
  92
  93         gic: interrupt-controller@0,50041000 {
  94                 compatible = "arm,cortex-a15-gic";
  95                 #interrupt-cells = <3>;
  96                 interrupt-controller;
  97                 reg = <0x0 0x50041000 0x0 0x1000>,
  98                       <0x0 0x50042000 0x0 0x1000>,
  99                       <0x0 0x50044000 0x0 0x2000>,
 100                       <0x0 0x50046000 0x0 0x2000>;
 101                 interrupts = <GIC_PPI 9
 102                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 103         };
 104
 105         timer@0,60005000 {
 106                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 107                 reg = <0x0 0x60005000 0x0 0x400>;
 108                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 109                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 110                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 112                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 114                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 115         };
 116
 117         tegra_car: clock@0,60006000 {
 118                 compatible = "nvidia,tegra124-car";
 119                 reg = <0x0 0x60006000 0x0 0x1000>;
 120                 #clock-cells = <1>;
 121                 #reset-cells = <1>;
 122         };
 123
 124         gpio: gpio@0,6000d000 {
 125                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 126                 reg = <0x0 0x6000d000 0x0 0x1000>;
 127                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 128                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 131                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         apbdma: dma@0,60020000 {
 142                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 143                 reg = <0x0 0x60020000 0x0 0x1400>;
 144                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 177                 resets = <&tegra_car 34>;
 178                 reset-names = "dma";
 179                 #dma-cells = <1>;
 180         };
 181
 182         apbmisc@0,70000800 {
 183                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 184                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 185                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 186         };
 187
 188         pinmux: pinmux@0,70000868 {
 189                 compatible = "nvidia,tegra124-pinmux";
 190                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 191                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 192         };
 193
 194         /*
 195          * There are two serial driver i.e. 8250 based simple serial
 196          * driver and APB DMA based serial driver for higher baudrate
 197          * and performace. To enable the 8250 based driver, the compatible
 198          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 199          * the APB DMA based serial driver, the comptible is
 200          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 201          */
 202         serial@0,70006000 {
 203                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 204                 reg = <0x0 0x70006000 0x0 0x40>;
 205                 reg-shift = <2>;
 206                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 208                 resets = <&tegra_car 6>;
 209                 reset-names = "serial";
 210                 dmas = <&apbdma 8>, <&apbdma 8>;
 211                 dma-names = "rx", "tx";
 212                 status = "disabled";
 213         };
 214
 215         serial@0,70006040 {
 216                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 217                 reg = <0x0 0x70006040 0x0 0x40>;
 218                 reg-shift = <2>;
 219                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 221                 resets = <&tegra_car 7>;
 222                 reset-names = "serial";
 223                 dmas = <&apbdma 9>, <&apbdma 9>;
 224                 dma-names = "rx", "tx";
 225                 status = "disabled";
 226         };
 227
 228         serial@0,70006200 {
 229                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 230                 reg = <0x0 0x70006200 0x0 0x40>;
 231                 reg-shift = <2>;
 232                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 234                 resets = <&tegra_car 55>;
 235                 reset-names = "serial";
 236                 dmas = <&apbdma 10>, <&apbdma 10>;
 237                 dma-names = "rx", "tx";
 238                 status = "disabled";
 239         };
 240
 241         serial@0,70006300 {
 242                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 243                 reg = <0x0 0x70006300 0x0 0x40>;
 244                 reg-shift = <2>;
 245                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 247                 resets = <&tegra_car 65>;
 248                 reset-names = "serial";
 249                 dmas = <&apbdma 19>, <&apbdma 19>;
 250                 dma-names = "rx", "tx";
 251                 status = "disabled";
 252         };
 253
 254         pwm@0,7000a000 {
 255                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 256                 reg = <0x0 0x7000a000 0x0 0x100>;
 257                 #pwm-cells = <2>;
 258                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 259                 resets = <&tegra_car 17>;
 260                 reset-names = "pwm";
 261                 status = "disabled";
 262         };
 263
 264         i2c@0,7000c000 {
 265                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 266                 reg = <0x0 0x7000c000 0x0 0x100>;
 267                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 271                 clock-names = "div-clk";
 272                 resets = <&tegra_car 12>;
 273                 reset-names = "i2c";
 274                 dmas = <&apbdma 21>, <&apbdma 21>;
 275                 dma-names = "rx", "tx";
 276                 status = "disabled";
 277         };
 278
 279         i2c@0,7000c400 {
 280                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 281                 reg = <0x0 0x7000c400 0x0 0x100>;
 282                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 286                 clock-names = "div-clk";
 287                 resets = <&tegra_car 54>;
 288                 reset-names = "i2c";
 289                 dmas = <&apbdma 22>, <&apbdma 22>;
 290                 dma-names = "rx", "tx";
 291                 status = "disabled";
 292         };
 293
 294         i2c@0,7000c500 {
 295                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 296                 reg = <0x0 0x7000c500 0x0 0x100>;
 297                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 301                 clock-names = "div-clk";
 302                 resets = <&tegra_car 67>;
 303                 reset-names = "i2c";
 304                 dmas = <&apbdma 23>, <&apbdma 23>;
 305                 dma-names = "rx", "tx";
 306                 status = "disabled";
 307         };
 308
 309         i2c@0,7000c700 {
 310                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 311                 reg = <0x0 0x7000c700 0x0 0x100>;
 312                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 316                 clock-names = "div-clk";
 317                 resets = <&tegra_car 103>;
 318                 reset-names = "i2c";
 319                 dmas = <&apbdma 26>, <&apbdma 26>;
 320                 dma-names = "rx", "tx";
 321                 status = "disabled";
 322         };
 323
 324         i2c@0,7000d000 {
 325                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 326                 reg = <0x0 0x7000d000 0x0 0x100>;
 327                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 331                 clock-names = "div-clk";
 332                 resets = <&tegra_car 47>;
 333                 reset-names = "i2c";
 334                 dmas = <&apbdma 24>, <&apbdma 24>;
 335                 dma-names = "rx", "tx";
 336                 status = "disabled";
 337         };
 338
 339         i2c@0,7000d100 {
 340                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 341                 reg = <0x0 0x7000d100 0x0 0x100>;
 342                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 346                 clock-names = "div-clk";
 347                 resets = <&tegra_car 166>;
 348                 reset-names = "i2c";
 349                 dmas = <&apbdma 30>, <&apbdma 30>;
 350                 dma-names = "rx", "tx";
 351                 status = "disabled";
 352         };
 353
 354         spi@0,7000d400 {
 355                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 356                 reg = <0x0 0x7000d400 0x0 0x200>;
 357                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 361                 clock-names = "spi";
 362                 resets = <&tegra_car 41>;
 363                 reset-names = "spi";
 364                 dmas = <&apbdma 15>, <&apbdma 15>;
 365                 dma-names = "rx", "tx";
 366                 status = "disabled";
 367         };
 368
 369         spi@0,7000d600 {
 370                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 371                 reg = <0x0 0x7000d600 0x0 0x200>;
 372                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 376                 clock-names = "spi";
 377                 resets = <&tegra_car 44>;
 378                 reset-names = "spi";
 379                 dmas = <&apbdma 16>, <&apbdma 16>;
 380                 dma-names = "rx", "tx";
 381                 status = "disabled";
 382         };
 383
 384         spi@0,7000d800 {
 385                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 386                 reg = <0x0 0x7000d800 0x0 0x200>;
 387                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 391                 clock-names = "spi";
 392                 resets = <&tegra_car 46>;
 393                 reset-names = "spi";
 394                 dmas = <&apbdma 17>, <&apbdma 17>;
 395                 dma-names = "rx", "tx";
 396                 status = "disabled";
 397         };
 398
 399         spi@0,7000da00 {
 400                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 401                 reg = <0x0 0x7000da00 0x0 0x200>;
 402                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 406                 clock-names = "spi";
 407                 resets = <&tegra_car 68>;
 408                 reset-names = "spi";
 409                 dmas = <&apbdma 18>, <&apbdma 18>;
 410                 dma-names = "rx", "tx";
 411                 status = "disabled";
 412         };
 413
 414         spi@0,7000dc00 {
 415                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 416                 reg = <0x0 0x7000dc00 0x0 0x200>;
 417                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 421                 clock-names = "spi";
 422                 resets = <&tegra_car 104>;
 423                 reset-names = "spi";
 424                 dmas = <&apbdma 27>, <&apbdma 27>;
 425                 dma-names = "rx", "tx";
 426                 status = "disabled";
 427         };
 428
 429         spi@0,7000de00 {
 430                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 431                 reg = <0x0 0x7000de00 0x0 0x200>;
 432                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 436                 clock-names = "spi";
 437                 resets = <&tegra_car 105>;
 438                 reset-names = "spi";
 439                 dmas = <&apbdma 28>, <&apbdma 28>;
 440                 dma-names = "rx", "tx";
 441                 status = "disabled";
 442         };
 443
 444         rtc@0,7000e000 {
 445                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 446                 reg = <0x0 0x7000e000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 449         };
 450
 451         pmc@0,7000e400 {
 452                 compatible = "nvidia,tegra124-pmc";
 453                 reg = <0x0 0x7000e400 0x0 0x400>;
 454                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 455                 clock-names = "pclk", "clk32k_in";
 456         };
 457
 458         fuse@0,7000f800 {
 459                 compatible = "nvidia,tegra124-efuse";
 460                 reg = <0x0 0x7000f800 0x0 0x400>;
 461                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 462                 clock-names = "fuse";
 463                 resets = <&tegra_car 39>;
 464                 reset-names = "fuse";
 465         };
 466
 467         hda@0,70030000 {
 468                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 469                 reg = <0x0 0x70030000 0x0 0x10000>;
 470                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 472                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 473                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 474                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 475                 resets = <&tegra_car 125>, /* hda */
 476                          <&tegra_car 128>, /* hda2hdmi */
 477                          <&tegra_car 111>; /* hda2codec_2x */
 478                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 479                 status = "disabled";
 480         };
 481
 482         sdhci@0,700b0000 {
 483                 compatible = "nvidia,tegra124-sdhci";
 484                 reg = <0x0 0x700b0000 0x0 0x200>;
 485                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 487                 resets = <&tegra_car 14>;
 488                 reset-names = "sdhci";
 489                 status = "disabled";
 490         };
 491
 492         sdhci@0,700b0200 {
 493                 compatible = "nvidia,tegra124-sdhci";
 494                 reg = <0x0 0x700b0200 0x0 0x200>;
 495                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 497                 resets = <&tegra_car 9>;
 498                 reset-names = "sdhci";
 499                 status = "disabled";
 500         };
 501
 502         sdhci@0,700b0400 {
 503                 compatible = "nvidia,tegra124-sdhci";
 504                 reg = <0x0 0x700b0400 0x0 0x200>;
 505                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 506                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 507                 resets = <&tegra_car 69>;
 508                 reset-names = "sdhci";
 509                 status = "disabled";
 510         };
 511
 512         sdhci@0,700b0600 {
 513                 compatible = "nvidia,tegra124-sdhci";
 514                 reg = <0x0 0x700b0600 0x0 0x200>;
 515                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 517                 resets = <&tegra_car 15>;
 518                 reset-names = "sdhci";
 519                 status = "disabled";
 520         };
 521
 522         ahub@0,70300000 {
 523                 compatible = "nvidia,tegra124-ahub";
 524                 reg = <0x0 0x70300000 0x0 0x200>,
 525                       <0x0 0x70300800 0x0 0x800>,
 526                       <0x0 0x70300200 0x0 0x600>;
 527                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 528                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 529                          <&tegra_car TEGRA124_CLK_APBIF>;
 530                 clock-names = "d_audio", "apbif";
 531                 resets = <&tegra_car 106>, /* d_audio */
 532                          <&tegra_car 107>, /* apbif */
 533                          <&tegra_car 30>,  /* i2s0 */
 534                          <&tegra_car 11>,  /* i2s1 */
 535                          <&tegra_car 18>,  /* i2s2 */
 536                          <&tegra_car 101>, /* i2s3 */
 537                          <&tegra_car 102>, /* i2s4 */
 538                          <&tegra_car 108>, /* dam0 */
 539                          <&tegra_car 109>, /* dam1 */
 540                          <&tegra_car 110>, /* dam2 */
 541                          <&tegra_car 10>,  /* spdif */
 542                          <&tegra_car 153>, /* amx */
 543                          <&tegra_car 185>, /* amx1 */
 544                          <&tegra_car 154>, /* adx */
 545                          <&tegra_car 180>, /* adx1 */
 546                          <&tegra_car 186>, /* afc0 */
 547                          <&tegra_car 187>, /* afc1 */
 548                          <&tegra_car 188>, /* afc2 */
 549                          <&tegra_car 189>, /* afc3 */
 550                          <&tegra_car 190>, /* afc4 */
 551                          <&tegra_car 191>; /* afc5 */
 552                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 553                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 554                               "spdif", "amx", "amx1", "adx", "adx1",
 555                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 556                 dmas = <&apbdma 1>, <&apbdma 1>,
 557                        <&apbdma 2>, <&apbdma 2>,
 558                        <&apbdma 3>, <&apbdma 3>,
 559                        <&apbdma 4>, <&apbdma 4>,
 560                        <&apbdma 6>, <&apbdma 6>,
 561                        <&apbdma 7>, <&apbdma 7>,
 562                        <&apbdma 12>, <&apbdma 12>,
 563                        <&apbdma 13>, <&apbdma 13>,
 564                        <&apbdma 14>, <&apbdma 14>,
 565                        <&apbdma 29>, <&apbdma 29>;
 566                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 567                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 568                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 569                             "rx9", "tx9";
 570                 ranges;
 571                 #address-cells = <2>;
 572                 #size-cells = <2>;
 573
 574                 tegra_i2s0: i2s@0,70301000 {
 575                         compatible = "nvidia,tegra124-i2s";
 576                         reg = <0x0 0x70301000 0x0 0x100>;
 577                         nvidia,ahub-cif-ids = <4 4>;
 578                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 579                         resets = <&tegra_car 30>;
 580                         reset-names = "i2s";
 581                         status = "disabled";
 582                 };
 583
 584                 tegra_i2s1: i2s@0,70301100 {
 585                         compatible = "nvidia,tegra124-i2s";
 586                         reg = <0x0 0x70301100 0x0 0x100>;
 587                         nvidia,ahub-cif-ids = <5 5>;
 588                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 589                         resets = <&tegra_car 11>;
 590                         reset-names = "i2s";
 591                         status = "disabled";
 592                 };
 593
 594                 tegra_i2s2: i2s@0,70301200 {
 595                         compatible = "nvidia,tegra124-i2s";
 596                         reg = <0x0 0x70301200 0x0 0x100>;
 597                         nvidia,ahub-cif-ids = <6 6>;
 598                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 599                         resets = <&tegra_car 18>;
 600                         reset-names = "i2s";
 601                         status = "disabled";
 602                 };
 603
 604                 tegra_i2s3: i2s@0,70301300 {
 605                         compatible = "nvidia,tegra124-i2s";
 606                         reg = <0x0 0x70301300 0x0 0x100>;
 607                         nvidia,ahub-cif-ids = <7 7>;
 608                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 609                         resets = <&tegra_car 101>;
 610                         reset-names = "i2s";
 611                         status = "disabled";
 612                 };
 613
 614                 tegra_i2s4: i2s@0,70301400 {
 615                         compatible = "nvidia,tegra124-i2s";
 616                         reg = <0x0 0x70301400 0x0 0x100>;
 617                         nvidia,ahub-cif-ids = <8 8>;
 618                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 619                         resets = <&tegra_car 102>;
 620                         reset-names = "i2s";
 621                         status = "disabled";
 622                 };
 623         };
 624
 625         usb@0,7d000000 {
 626                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 627                 reg = <0x0 0x7d000000 0x0 0x4000>;
 628                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 629                 phy_type = "utmi";
 630                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 631                 resets = <&tegra_car 22>;
 632                 reset-names = "usb";
 633                 nvidia,phy = <&phy1>;
 634                 status = "disabled";
 635         };
 636
 637         phy1: usb-phy@0,7d000000 {
 638                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 639                 reg = <0x0 0x7d000000 0x0 0x4000>,
 640                       <0x0 0x7d000000 0x0 0x4000>;
 641                 phy_type = "utmi";
 642                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 643                          <&tegra_car TEGRA124_CLK_PLL_U>,
 644                          <&tegra_car TEGRA124_CLK_USBD>;
 645                 clock-names = "reg", "pll_u", "utmi-pads";
 646                 nvidia,hssync-start-delay = <0>;
 647                 nvidia,idle-wait-delay = <17>;
 648                 nvidia,elastic-limit = <16>;
 649                 nvidia,term-range-adj = <6>;
 650                 nvidia,xcvr-setup = <9>;
 651                 nvidia,xcvr-lsfslew = <0>;
 652                 nvidia,xcvr-lsrslew = <3>;
 653                 nvidia,hssquelch-level = <2>;
 654                 nvidia,hsdiscon-level = <5>;
 655                 nvidia,xcvr-hsslew = <12>;
 656                 status = "disabled";
 657         };
 658
 659         usb@0,7d004000 {
 660                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 661                 reg = <0x0 0x7d004000 0x0 0x4000>;
 662                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 663                 phy_type = "utmi";
 664                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 665                 resets = <&tegra_car 58>;
 666                 reset-names = "usb";
 667                 nvidia,phy = <&phy2>;
 668                 status = "disabled";
 669         };
 670
 671         phy2: usb-phy@0,7d004000 {
 672                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 673                 reg = <0x0 0x7d004000 0x0 0x4000>,
 674                       <0x0 0x7d000000 0x0 0x4000>;
 675                 phy_type = "utmi";
 676                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 677                          <&tegra_car TEGRA124_CLK_PLL_U>,
 678                          <&tegra_car TEGRA124_CLK_USBD>;
 679                 clock-names = "reg", "pll_u", "utmi-pads";
 680                 nvidia,hssync-start-delay = <0>;
 681                 nvidia,idle-wait-delay = <17>;
 682                 nvidia,elastic-limit = <16>;
 683                 nvidia,term-range-adj = <6>;
 684                 nvidia,xcvr-setup = <9>;
 685                 nvidia,xcvr-lsfslew = <0>;
 686                 nvidia,xcvr-lsrslew = <3>;
 687                 nvidia,hssquelch-level = <2>;
 688                 nvidia,hsdiscon-level = <5>;
 689                 nvidia,xcvr-hsslew = <12>;
 690                 status = "disabled";
 691         };
 692
 693         usb@0,7d008000 {
 694                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 695                 reg = <0x0 0x7d008000 0x0 0x4000>;
 696                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 697                 phy_type = "utmi";
 698                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 699                 resets = <&tegra_car 59>;
 700                 reset-names = "usb";
 701                 nvidia,phy = <&phy3>;
 702                 status = "disabled";
 703         };
 704
 705         phy3: usb-phy@0,7d008000 {
 706                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 707                 reg = <0x0 0x7d008000 0x0 0x4000>,
 708                       <0x0 0x7d000000 0x0 0x4000>;
 709                 phy_type = "utmi";
 710                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 711                          <&tegra_car TEGRA124_CLK_PLL_U>,
 712                          <&tegra_car TEGRA124_CLK_USBD>;
 713                 clock-names = "reg", "pll_u", "utmi-pads";
 714                 nvidia,hssync-start-delay = <0>;
 715                 nvidia,idle-wait-delay = <17>;
 716                 nvidia,elastic-limit = <16>;
 717                 nvidia,term-range-adj = <6>;
 718                 nvidia,xcvr-setup = <9>;
 719                 nvidia,xcvr-lsfslew = <0>;
 720                 nvidia,xcvr-lsrslew = <3>;
 721                 nvidia,hssquelch-level = <2>;
 722                 nvidia,hsdiscon-level = <5>;
 723                 nvidia,xcvr-hsslew = <12>;
 724                 status = "disabled";
 725         };
 726
 727         cpus {
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730
 731                 cpu@0 {
 732                         device_type = "cpu";
 733                         compatible = "arm,cortex-a15";
 734                         reg = <0>;
 735                 };
 736
 737                 cpu@1 {
 738                         device_type = "cpu";
 739                         compatible = "arm,cortex-a15";
 740                         reg = <1>;
 741                 };
 742
 743                 cpu@2 {
 744                         device_type = "cpu";
 745                         compatible = "arm,cortex-a15";
 746                         reg = <2>;
 747                 };
 748
 749                 cpu@3 {
 750                         device_type = "cpu";
 751                         compatible = "arm,cortex-a15";
 752                         reg = <3>;
 753                 };
 754         };
 755
 756         timer {
 757                 compatible = "arm,armv7-timer";
 758                 interrupts = <GIC_PPI 13
 759                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 760                              <GIC_PPI 14
 761                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 762                              <GIC_PPI 11
 763                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 764                              <GIC_PPI 10
 765                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 766         };
 767 };