2 * Device Tree Source for UniPhier LD4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-ld4";
57 compatible = "arm,cortex-a9";
59 next-level-cache = <&l2>;
64 arm_timer_clk: arm_timer_clk {
66 compatible = "fixed-clock";
67 clock-frequency = <50000000>;
72 compatible = "fixed-clock";
73 clock-frequency = <36864000>;
76 iobus_clk: iobus_clk {
78 compatible = "fixed-clock";
79 clock-frequency = <100000000>;
85 l2: l2-cache@500c0000 {
86 compatible = "socionext,uniphier-system-cache";
87 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
88 interrupts = <0 174 4>, <0 175 4>;
90 cache-size = <(512 * 1024)>;
92 cache-line-size = <128>;
97 compatible = "socionext,uniphier-i2c";
99 reg = <0x58400000 0x40>;
100 #address-cells = <1>;
102 interrupts = <0 41 1>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_i2c0>;
105 clocks = <&iobus_clk>;
106 clock-frequency = <100000>;
110 compatible = "socionext,uniphier-i2c";
112 reg = <0x58480000 0x40>;
113 #address-cells = <1>;
115 interrupts = <0 42 1>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>;
118 clocks = <&iobus_clk>;
119 clock-frequency = <100000>;
122 /* chip-internal connection for DMD */
124 compatible = "socionext,uniphier-i2c";
125 reg = <0x58500000 0x40>;
126 #address-cells = <1>;
128 interrupts = <0 43 1>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c2>;
131 clocks = <&iobus_clk>;
132 clock-frequency = <400000>;
136 compatible = "socionext,uniphier-i2c";
138 reg = <0x58580000 0x40>;
139 #address-cells = <1>;
141 interrupts = <0 44 1>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_i2c3>;
144 clocks = <&iobus_clk>;
145 clock-frequency = <100000>;
149 compatible = "socionext,uniphier-ehci", "generic-ehci";
151 reg = <0x5a800100 0x100>;
152 interrupts = <0 80 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_usb0>;
158 compatible = "socionext,uniphier-ehci", "generic-ehci";
160 reg = <0x5a810100 0x100>;
161 interrupts = <0 81 4>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_usb1>;
167 compatible = "socionext,uniphier-ehci", "generic-ehci";
169 reg = <0x5a820100 0x100>;
170 interrupts = <0 82 4>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_usb2>;
178 clock-frequency = <24576000>;
182 interrupts = <0 29 4>;
186 compatible = "socionext,uniphier-ld4-pinctrl";