2 * Device Tree Source for UniPhier LD4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-ld4";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 arm_timer_clk: arm_timer_clk {
67 compatible = "fixed-clock";
68 clock-frequency = <50000000>;
73 compatible = "fixed-clock";
74 clock-frequency = <36864000>;
77 iobus_clk: iobus_clk {
79 compatible = "fixed-clock";
80 clock-frequency = <100000000>;
86 l2: l2-cache@500c0000 {
87 compatible = "socionext,uniphier-system-cache";
88 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
89 interrupts = <0 174 4>, <0 175 4>;
91 cache-size = <(512 * 1024)>;
93 cache-line-size = <128>;
98 compatible = "socionext,uniphier-i2c";
100 reg = <0x58400000 0x40>;
101 #address-cells = <1>;
103 interrupts = <0 41 1>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c0>;
106 clocks = <&iobus_clk>;
107 clock-frequency = <100000>;
111 compatible = "socionext,uniphier-i2c";
113 reg = <0x58480000 0x40>;
114 #address-cells = <1>;
116 interrupts = <0 42 1>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_i2c1>;
119 clocks = <&iobus_clk>;
120 clock-frequency = <100000>;
123 /* chip-internal connection for DMD */
125 compatible = "socionext,uniphier-i2c";
126 reg = <0x58500000 0x40>;
127 #address-cells = <1>;
129 interrupts = <0 43 1>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_i2c2>;
132 clocks = <&iobus_clk>;
133 clock-frequency = <400000>;
137 compatible = "socionext,uniphier-i2c";
139 reg = <0x58580000 0x40>;
140 #address-cells = <1>;
142 interrupts = <0 44 1>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_i2c3>;
145 clocks = <&iobus_clk>;
146 clock-frequency = <100000>;
150 compatible = "socionext,uniphier-ehci", "generic-ehci";
152 reg = <0x5a800100 0x100>;
153 interrupts = <0 80 4>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_usb0>;
159 compatible = "socionext,uniphier-ehci", "generic-ehci";
161 reg = <0x5a810100 0x100>;
162 interrupts = <0 81 4>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_usb1>;
168 compatible = "socionext,uniphier-ehci", "generic-ehci";
170 reg = <0x5a820100 0x100>;
171 interrupts = <0 82 4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_usb2>;
179 clock-frequency = <24576000>;
183 interrupts = <0 29 4>;
187 compatible = "socionext,uniphier-ld4-pinctrl";