arch/arm/boot/dts/uniphier-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD3 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /include/ "skeleton.dtsi"
  47
  48 / {
  49         compatible = "socionext,uniphier-sld3";
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "socionext,uniphier-smp";
  55
  56                 cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a9";
  59                         reg = <0>;
  60                         next-level-cache = <&l2>;
  61                 };
  62
  63                 cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a9";
  66                         reg = <1>;
  67                         next-level-cache = <&l2>;
  68                 };
  69         };
  70
  71         clocks {
  72                 refclk: ref {
  73                         #clock-cells = <0>;
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <24576000>;
  76                 };
  77
  78                 arm_timer_clk: arm_timer_clk {
  79                         #clock-cells = <0>;
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <50000000>;
  82                 };
  83
  84                 uart_clk: uart_clk {
  85                         #clock-cells = <0>;
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <36864000>;
  88                 };
  89
  90                 iobus_clk: iobus_clk {
  91                         #clock-cells = <0>;
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <100000000>;
  94                 };
  95         };
  96
  97         soc {
  98                 compatible = "simple-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102                 interrupt-parent = <&intc>;
 103
 104                 timer@20000200 {
 105                         compatible = "arm,cortex-a9-global-timer";
 106                         reg = <0x20000200 0x20>;
 107                         interrupts = <1 11 0x304>;
 108                         clocks = <&arm_timer_clk>;
 109                 };
 110
 111                 timer@20000600 {
 112                         compatible = "arm,cortex-a9-twd-timer";
 113                         reg = <0x20000600 0x20>;
 114                         interrupts = <1 13 0x304>;
 115                         clocks = <&arm_timer_clk>;
 116                 };
 117
 118                 intc: interrupt-controller@20001000 {
 119                         compatible = "arm,cortex-a9-gic";
 120                         #interrupt-cells = <3>;
 121                         interrupt-controller;
 122                         reg = <0x20001000 0x1000>,
 123                               <0x20000100 0x100>;
 124                 };
 125
 126                 l2: l2-cache@500c0000 {
 127                         compatible = "socionext,uniphier-system-cache";
 128                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
 129                               <0x506c0000 0x400>;
 130                         interrupts = <0 174 4>, <0 175 4>;
 131                         cache-unified;
 132                         cache-size = <(512 * 1024)>;
 133                         cache-sets = <256>;
 134                         cache-line-size = <128>;
 135                         cache-level = <2>;
 136                 };
 137
 138                 serial0: serial@54006800 {
 139                         compatible = "socionext,uniphier-uart";
 140                         status = "disabled";
 141                         reg = <0x54006800 0x40>;
 142                         interrupts = <0 33 4>;
 143                         clocks = <&uart_clk>;
 144                         fifo-size = <64>;
 145                 };
 146
 147                 serial1: serial@54006900 {
 148                         compatible = "socionext,uniphier-uart";
 149                         status = "disabled";
 150                         reg = <0x54006900 0x40>;
 151                         interrupts = <0 35 4>;
 152                         clocks = <&uart_clk>;
 153                         fifo-size = <64>;
 154                 };
 155
 156                 serial2: serial@54006a00 {
 157                         compatible = "socionext,uniphier-uart";
 158                         status = "disabled";
 159                         reg = <0x54006a00 0x40>;
 160                         interrupts = <0 37 4>;
 161                         clocks = <&uart_clk>;
 162                         fifo-size = <64>;
 163                 };
 164
 165                 i2c0: i2c@58400000 {
 166                         compatible = "socionext,uniphier-i2c";
 167                         status = "disabled";
 168                         reg = <0x58400000 0x40>;
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         interrupts = <0 41 1>;
 172                         clocks = <&iobus_clk>;
 173                         clock-frequency = <100000>;
 174                 };
 175
 176                 i2c1: i2c@58480000 {
 177                         compatible = "socionext,uniphier-i2c";
 178                         status = "disabled";
 179                         reg = <0x58480000 0x40>;
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         interrupts = <0 42 1>;
 183                         clocks = <&iobus_clk>;
 184                         clock-frequency = <100000>;
 185                 };
 186
 187                 i2c2: i2c@58500000 {
 188                         compatible = "socionext,uniphier-i2c";
 189                         status = "disabled";
 190                         reg = <0x58500000 0x40>;
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                         interrupts = <0 43 1>;
 194                         clocks = <&iobus_clk>;
 195                         clock-frequency = <100000>;
 196                 };
 197
 198                 i2c3: i2c@58580000 {
 199                         compatible = "socionext,uniphier-i2c";
 200                         status = "disabled";
 201                         reg = <0x58580000 0x40>;
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         interrupts = <0 44 1>;
 205                         clocks = <&iobus_clk>;
 206                         clock-frequency = <100000>;
 207                 };
 208
 209                 /* chip-internal connection for DMD */
 210                 i2c4: i2c@58600000 {
 211                         compatible = "socionext,uniphier-i2c";
 212                         reg = <0x58600000 0x40>;
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         interrupts = <0 45 1>;
 216                         clocks = <&iobus_clk>;
 217                         clock-frequency = <400000>;
 218                 };
 219
 220                 system_bus: system-bus@58c00000 {
 221                         compatible = "socionext,uniphier-system-bus";
 222                         status = "disabled";
 223                         reg = <0x58c00000 0x400>;
 224                         #address-cells = <2>;
 225                         #size-cells = <1>;
 226                 };
 227
 228                 smpctrl@59800000 {
 229                         compatible = "socionext,uniphier-smpctrl";
 230                         reg = <0x59801000 0x400>;
 231                 };
 232
 233                 usb0: usb@5a800100 {
 234                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 235                         status = "disabled";
 236                         reg = <0x5a800100 0x100>;
 237                         interrupts = <0 80 4>;
 238                 };
 239
 240                 usb1: usb@5a810100 {
 241                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 242                         status = "disabled";
 243                         reg = <0x5a810100 0x100>;
 244                         interrupts = <0 81 4>;
 245                 };
 246
 247                 usb2: usb@5a820100 {
 248                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 249                         status = "disabled";
 250                         reg = <0x5a820100 0x100>;
 251                         interrupts = <0 82 4>;
 252                 };
 253
 254                 usb3: usb@5a830100 {
 255                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 256                         status = "disabled";
 257                         reg = <0x5a830100 0x100>;
 258                         interrupts = <0 83 4>;
 259                 };
 260         };
 261 };