2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/utsname.h>
16 #include <linux/initrd.h>
17 #include <linux/console.h>
18 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/screen_info.h>
21 #include <linux/of_iommu.h>
22 #include <linux/of_platform.h>
23 #include <linux/init.h>
24 #include <linux/kexec.h>
25 #include <linux/of_fdt.h>
26 #include <linux/cpu.h>
27 #include <linux/interrupt.h>
28 #include <linux/smp.h>
29 #include <linux/proc_fs.h>
30 #include <linux/memblock.h>
31 #include <linux/bug.h>
32 #include <linux/compiler.h>
33 #include <linux/sort.h>
35 #include <asm/unified.h>
38 #include <asm/cputype.h>
40 #include <asm/procinfo.h>
42 #include <asm/sections.h>
43 #include <asm/setup.h>
44 #include <asm/smp_plat.h>
45 #include <asm/mach-types.h>
46 #include <asm/cacheflush.h>
47 #include <asm/cachetype.h>
48 #include <asm/tlbflush.h>
49 #include <asm/xen/hypervisor.h>
52 #include <asm/mach/arch.h>
53 #include <asm/mach/irq.h>
54 #include <asm/mach/time.h>
55 #include <asm/system_info.h>
56 #include <asm/system_misc.h>
57 #include <asm/traps.h>
58 #include <asm/unwind.h>
59 #include <asm/memblock.h>
65 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
68 static int __init fpe_setup(char *line)
70 memcpy(fpe_type, line, 8);
74 __setup("fpe=", fpe_setup);
77 extern void init_default_cache_policy(unsigned long);
78 extern void paging_init(const struct machine_desc *desc);
79 extern void early_paging_init(const struct machine_desc *);
80 extern void sanity_check_meminfo(void);
81 extern enum reboot_mode reboot_mode;
82 extern void setup_dma_zone(const struct machine_desc *desc);
84 unsigned int processor_id;
85 EXPORT_SYMBOL(processor_id);
86 unsigned int __machine_arch_type __read_mostly;
87 EXPORT_SYMBOL(__machine_arch_type);
88 unsigned int cacheid __read_mostly;
89 EXPORT_SYMBOL(cacheid);
91 unsigned int __atags_pointer __initdata;
93 unsigned int system_rev;
94 EXPORT_SYMBOL(system_rev);
96 const char *system_serial;
97 EXPORT_SYMBOL(system_serial);
99 unsigned int system_serial_low;
100 EXPORT_SYMBOL(system_serial_low);
102 unsigned int system_serial_high;
103 EXPORT_SYMBOL(system_serial_high);
105 unsigned int elf_hwcap __read_mostly;
106 EXPORT_SYMBOL(elf_hwcap);
108 unsigned int elf_hwcap2 __read_mostly;
109 EXPORT_SYMBOL(elf_hwcap2);
113 struct processor processor __read_mostly;
116 struct cpu_tlb_fns cpu_tlb __read_mostly;
119 struct cpu_user_fns cpu_user __read_mostly;
122 struct cpu_cache_fns cpu_cache __read_mostly;
124 #ifdef CONFIG_OUTER_CACHE
125 struct outer_cache_fns outer_cache __read_mostly;
126 EXPORT_SYMBOL(outer_cache);
130 * Cached cpu_architecture() result for use by assembler code.
131 * C code should use the cpu_architecture() function instead of accessing this
134 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
141 } ____cacheline_aligned;
143 #ifndef CONFIG_CPU_V7M
144 static struct stack stacks[NR_CPUS];
147 char elf_platform[ELF_PLATFORM_SIZE];
148 EXPORT_SYMBOL(elf_platform);
150 static const char *cpu_name;
151 static const char *machine_name;
152 static char __initdata cmd_line[COMMAND_LINE_SIZE];
153 const struct machine_desc *machine_desc __initdata;
155 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
156 #define ENDIANNESS ((char)endian_test.l)
158 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
161 * Standard memory resources
163 static struct resource mem_res[] = {
168 .flags = IORESOURCE_MEM
171 .name = "Kernel code",
174 .flags = IORESOURCE_MEM
177 .name = "Kernel data",
180 .flags = IORESOURCE_MEM
184 #define video_ram mem_res[0]
185 #define kernel_code mem_res[1]
186 #define kernel_data mem_res[2]
188 static struct resource io_res[] = {
193 .flags = IORESOURCE_IO | IORESOURCE_BUSY
199 .flags = IORESOURCE_IO | IORESOURCE_BUSY
205 .flags = IORESOURCE_IO | IORESOURCE_BUSY
209 #define lp0 io_res[0]
210 #define lp1 io_res[1]
211 #define lp2 io_res[2]
213 static const char *proc_arch[] = {
233 #ifdef CONFIG_CPU_V7M
234 static int __get_cpu_architecture(void)
236 return CPU_ARCH_ARMv7M;
239 static int __get_cpu_architecture(void)
243 if ((read_cpuid_id() & 0x0008f000) == 0) {
244 cpu_arch = CPU_ARCH_UNKNOWN;
245 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
246 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
247 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
248 cpu_arch = (read_cpuid_id() >> 16) & 7;
250 cpu_arch += CPU_ARCH_ARMv3;
251 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
252 /* Revised CPUID format. Read the Memory Model Feature
253 * Register 0 and check for VMSAv7 or PMSAv7 */
254 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
255 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
256 (mmfr0 & 0x000000f0) >= 0x00000030)
257 cpu_arch = CPU_ARCH_ARMv7;
258 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
259 (mmfr0 & 0x000000f0) == 0x00000020)
260 cpu_arch = CPU_ARCH_ARMv6;
262 cpu_arch = CPU_ARCH_UNKNOWN;
264 cpu_arch = CPU_ARCH_UNKNOWN;
270 int __pure cpu_architecture(void)
272 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
274 return __cpu_architecture;
277 static int cpu_has_aliasing_icache(unsigned int arch)
280 unsigned int id_reg, num_sets, line_size;
282 /* PIPT caches never alias. */
283 if (icache_is_pipt())
286 /* arch specifies the register format */
289 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
290 : /* No output operands */
293 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
295 line_size = 4 << ((id_reg & 0x7) + 2);
296 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
297 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
300 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
303 /* I-cache aliases will be handled by D-cache aliasing code */
307 return aliasing_icache;
310 static void __init cacheid_init(void)
312 unsigned int arch = cpu_architecture();
314 if (arch == CPU_ARCH_ARMv7M) {
316 } else if (arch >= CPU_ARCH_ARMv6) {
317 unsigned int cachetype = read_cpuid_cachetype();
318 if ((cachetype & (7 << 29)) == 4 << 29) {
319 /* ARMv7 register format */
320 arch = CPU_ARCH_ARMv7;
321 cacheid = CACHEID_VIPT_NONALIASING;
322 switch (cachetype & (3 << 14)) {
324 cacheid |= CACHEID_ASID_TAGGED;
327 cacheid |= CACHEID_PIPT;
331 arch = CPU_ARCH_ARMv6;
332 if (cachetype & (1 << 23))
333 cacheid = CACHEID_VIPT_ALIASING;
335 cacheid = CACHEID_VIPT_NONALIASING;
337 if (cpu_has_aliasing_icache(arch))
338 cacheid |= CACHEID_VIPT_I_ALIASING;
340 cacheid = CACHEID_VIVT;
343 pr_info("CPU: %s data cache, %s instruction cache\n",
344 cache_is_vivt() ? "VIVT" :
345 cache_is_vipt_aliasing() ? "VIPT aliasing" :
346 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
347 cache_is_vivt() ? "VIVT" :
348 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
349 icache_is_vipt_aliasing() ? "VIPT aliasing" :
350 icache_is_pipt() ? "PIPT" :
351 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
355 * These functions re-use the assembly code in head.S, which
356 * already provide the required functionality.
358 extern struct proc_info_list *lookup_processor_type(unsigned int);
360 void __init early_print(const char *str, ...)
362 extern void printascii(const char *);
367 vsnprintf(buf, sizeof(buf), str, ap);
370 #ifdef CONFIG_DEBUG_LL
376 static void __init cpuid_init_hwcaps(void)
381 if (cpu_architecture() < CPU_ARCH_ARMv7)
384 block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
386 elf_hwcap |= HWCAP_IDIVA;
388 elf_hwcap |= HWCAP_IDIVT;
390 /* LPAE implies atomic ldrd/strd instructions */
391 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
393 elf_hwcap |= HWCAP_LPAE;
395 /* check for supported v8 Crypto instructions */
396 isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
398 block = cpuid_feature_extract_field(isar5, 4);
400 elf_hwcap2 |= HWCAP2_PMULL;
402 elf_hwcap2 |= HWCAP2_AES;
404 block = cpuid_feature_extract_field(isar5, 8);
406 elf_hwcap2 |= HWCAP2_SHA1;
408 block = cpuid_feature_extract_field(isar5, 12);
410 elf_hwcap2 |= HWCAP2_SHA2;
412 block = cpuid_feature_extract_field(isar5, 16);
414 elf_hwcap2 |= HWCAP2_CRC32;
417 static void __init elf_hwcap_fixup(void)
419 unsigned id = read_cpuid_id();
422 * HWCAP_TLS is available only on 1136 r1p0 and later,
423 * see also kuser_get_tls_init.
425 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
426 ((id >> 20) & 3) == 0) {
427 elf_hwcap &= ~HWCAP_TLS;
431 /* Verify if CPUID scheme is implemented */
432 if ((id & 0x000f0000) != 0x000f0000)
436 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
437 * avoid advertising SWP; it may not be atomic with
438 * multiprocessing cores.
440 if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
441 (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
442 cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
443 elf_hwcap &= ~HWCAP_SWP;
447 * cpu_init - initialise one CPU.
449 * cpu_init sets up the per-CPU stacks.
451 void notrace cpu_init(void)
453 #ifndef CONFIG_CPU_V7M
454 unsigned int cpu = smp_processor_id();
455 struct stack *stk = &stacks[cpu];
457 if (cpu >= NR_CPUS) {
458 pr_crit("CPU%u: bad primary CPU number\n", cpu);
463 * This only works on resume and secondary cores. For booting on the
464 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
466 set_my_cpu_offset(per_cpu_offset(cpu));
471 * Define the placement constraint for the inline asm directive below.
472 * In Thumb-2, msr with an immediate value is not allowed.
474 #ifdef CONFIG_THUMB2_KERNEL
481 * setup stacks for re-entrant exception handlers
485 "add r14, %0, %2\n\t"
488 "add r14, %0, %4\n\t"
491 "add r14, %0, %6\n\t"
494 "add r14, %0, %8\n\t"
499 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
500 "I" (offsetof(struct stack, irq[0])),
501 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
502 "I" (offsetof(struct stack, abt[0])),
503 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
504 "I" (offsetof(struct stack, und[0])),
505 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
506 "I" (offsetof(struct stack, fiq[0])),
507 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
512 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
514 void __init smp_setup_processor_id(void)
517 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
518 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
520 cpu_logical_map(0) = cpu;
521 for (i = 1; i < nr_cpu_ids; ++i)
522 cpu_logical_map(i) = i == cpu ? 0 : i;
525 * clear __my_cpu_offset on boot CPU to avoid hang caused by
526 * using percpu variable early, for example, lockdep will
527 * access percpu variable inside lock_release
529 set_my_cpu_offset(0);
531 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
534 struct mpidr_hash mpidr_hash;
537 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
538 * level in order to build a linear index from an
539 * MPIDR value. Resulting algorithm is a collision
540 * free hash carried out through shifting and ORing
542 static void __init smp_build_mpidr_hash(void)
545 u32 fs[3], bits[3], ls, mask = 0;
547 * Pre-scan the list of MPIDRS and filter out bits that do
548 * not contribute to affinity levels, ie they never toggle.
550 for_each_possible_cpu(i)
551 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
552 pr_debug("mask of set bits 0x%x\n", mask);
554 * Find and stash the last and first bit set at all affinity levels to
555 * check how many bits are required to represent them.
557 for (i = 0; i < 3; i++) {
558 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
560 * Find the MSB bit and LSB bits position
561 * to determine how many bits are required
562 * to express the affinity level.
565 fs[i] = affinity ? ffs(affinity) - 1 : 0;
566 bits[i] = ls - fs[i];
569 * An index can be created from the MPIDR by isolating the
570 * significant bits at each affinity level and by shifting
571 * them in order to compress the 24 bits values space to a
572 * compressed set of values. This is equivalent to hashing
573 * the MPIDR through shifting and ORing. It is a collision free
574 * hash though not minimal since some levels might contain a number
575 * of CPUs that is not an exact power of 2 and their bit
576 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
578 mpidr_hash.shift_aff[0] = fs[0];
579 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
580 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
582 mpidr_hash.mask = mask;
583 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
584 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
585 mpidr_hash.shift_aff[0],
586 mpidr_hash.shift_aff[1],
587 mpidr_hash.shift_aff[2],
591 * 4x is an arbitrary value used to warn on a hash table much bigger
592 * than expected on most systems.
594 if (mpidr_hash_size() > 4 * num_possible_cpus())
595 pr_warn("Large number of MPIDR hash buckets detected\n");
596 sync_cache_w(&mpidr_hash);
600 static void __init setup_processor(void)
602 struct proc_info_list *list;
605 * locate processor in the list of supported processor
606 * types. The linker builds this table for us from the
607 * entries in arch/arm/mm/proc-*.S
609 list = lookup_processor_type(read_cpuid_id());
611 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
616 cpu_name = list->cpu_name;
617 __cpu_architecture = __get_cpu_architecture();
620 processor = *list->proc;
623 cpu_tlb = *list->tlb;
626 cpu_user = *list->user;
629 cpu_cache = *list->cache;
632 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
633 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
634 proc_arch[cpu_architecture()], get_cr());
636 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
637 list->arch_name, ENDIANNESS);
638 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
639 list->elf_name, ENDIANNESS);
640 elf_hwcap = list->elf_hwcap;
644 #ifndef CONFIG_ARM_THUMB
645 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
648 init_default_cache_policy(list->__cpu_mm_mmu_flags);
650 erratum_a15_798181_init();
658 void __init dump_machine_table(void)
660 const struct machine_desc *p;
662 early_print("Available machine support:\n\nID (hex)\tNAME\n");
663 for_each_machine_desc(p)
664 early_print("%08x\t%s\n", p->nr, p->name);
666 early_print("\nPlease check your kernel config and/or bootloader.\n");
669 /* can't use cpu_relax() here as it may require MMU setup */;
672 int __init arm_add_memory(u64 start, u64 size)
677 * Ensure that start/size are aligned to a page boundary.
678 * Size is rounded down, start is rounded up.
680 aligned_start = PAGE_ALIGN(start);
681 if (aligned_start > start + size)
684 size -= aligned_start - start;
686 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
687 if (aligned_start > ULONG_MAX) {
688 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
693 if (aligned_start + size > ULONG_MAX) {
694 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
697 * To ensure bank->start + bank->size is representable in
698 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
699 * This means we lose a page after masking.
701 size = ULONG_MAX - aligned_start;
705 if (aligned_start < PHYS_OFFSET) {
706 if (aligned_start + size <= PHYS_OFFSET) {
707 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
708 aligned_start, aligned_start + size);
712 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
713 aligned_start, (u64)PHYS_OFFSET);
715 size -= PHYS_OFFSET - aligned_start;
716 aligned_start = PHYS_OFFSET;
719 start = aligned_start;
720 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
723 * Check whether this memory region has non-zero size or
724 * invalid node number.
729 memblock_add(start, size);
734 * Pick out the memory size. We look for mem=size@start,
735 * where start and size are "size[KkMm]"
738 static int __init early_mem(char *p)
740 static int usermem __initdata = 0;
746 * If the user specifies memory size, we
747 * blow away any automatically generated
752 memblock_remove(memblock_start_of_DRAM(),
753 memblock_end_of_DRAM() - memblock_start_of_DRAM());
757 size = memparse(p, &endp);
759 start = memparse(endp + 1, NULL);
761 arm_add_memory(start, size);
765 early_param("mem", early_mem);
767 static void __init request_standard_resources(const struct machine_desc *mdesc)
769 struct memblock_region *region;
770 struct resource *res;
772 kernel_code.start = virt_to_phys(_text);
773 kernel_code.end = virt_to_phys(_etext - 1);
774 kernel_data.start = virt_to_phys(_sdata);
775 kernel_data.end = virt_to_phys(_end - 1);
777 for_each_memblock(memory, region) {
778 res = memblock_virt_alloc(sizeof(*res), 0);
779 res->name = "System RAM";
780 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
781 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
782 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
784 request_resource(&iomem_resource, res);
786 if (kernel_code.start >= res->start &&
787 kernel_code.end <= res->end)
788 request_resource(res, &kernel_code);
789 if (kernel_data.start >= res->start &&
790 kernel_data.end <= res->end)
791 request_resource(res, &kernel_data);
794 if (mdesc->video_start) {
795 video_ram.start = mdesc->video_start;
796 video_ram.end = mdesc->video_end;
797 request_resource(&iomem_resource, &video_ram);
801 * Some machines don't have the possibility of ever
802 * possessing lp0, lp1 or lp2
804 if (mdesc->reserve_lp0)
805 request_resource(&ioport_resource, &lp0);
806 if (mdesc->reserve_lp1)
807 request_resource(&ioport_resource, &lp1);
808 if (mdesc->reserve_lp2)
809 request_resource(&ioport_resource, &lp2);
812 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
813 struct screen_info screen_info = {
814 .orig_video_lines = 30,
815 .orig_video_cols = 80,
816 .orig_video_mode = 0,
817 .orig_video_ega_bx = 0,
818 .orig_video_isVGA = 1,
819 .orig_video_points = 8
823 static int __init customize_machine(void)
826 * customizes platform devices, or adds new ones
827 * On DT based machines, we fall back to populating the
828 * machine from the device tree, if no callback is provided,
829 * otherwise we would always need an init_machine callback.
832 if (machine_desc->init_machine)
833 machine_desc->init_machine();
836 of_platform_populate(NULL, of_default_bus_match_table,
841 arch_initcall(customize_machine);
843 static int __init init_machine_late(void)
845 struct device_node *root;
848 if (machine_desc->init_late)
849 machine_desc->init_late();
851 root = of_find_node_by_path("/");
853 ret = of_property_read_string(root, "serial-number",
856 system_serial = NULL;
860 system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
866 late_initcall(init_machine_late);
869 static inline unsigned long long get_total_mem(void)
873 total = max_low_pfn - min_low_pfn;
874 return total << PAGE_SHIFT;
878 * reserve_crashkernel() - reserves memory are for crash kernel
880 * This function reserves memory area given in "crashkernel=" kernel command
881 * line parameter. The memory reserved is used by a dump capture kernel when
882 * primary kernel is crashing.
884 static void __init reserve_crashkernel(void)
886 unsigned long long crash_size, crash_base;
887 unsigned long long total_mem;
890 total_mem = get_total_mem();
891 ret = parse_crashkernel(boot_command_line, total_mem,
892 &crash_size, &crash_base);
896 ret = memblock_reserve(crash_base, crash_size);
898 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
899 (unsigned long)crash_base);
903 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
904 (unsigned long)(crash_size >> 20),
905 (unsigned long)(crash_base >> 20),
906 (unsigned long)(total_mem >> 20));
908 crashk_res.start = crash_base;
909 crashk_res.end = crash_base + crash_size - 1;
910 insert_resource(&iomem_resource, &crashk_res);
913 static inline void reserve_crashkernel(void) {}
914 #endif /* CONFIG_KEXEC */
916 void __init hyp_mode_check(void)
918 #ifdef CONFIG_ARM_VIRT_EXT
921 if (is_hyp_mode_available()) {
922 pr_info("CPU: All CPU(s) started in HYP mode.\n");
923 pr_info("CPU: Virtualization extensions available.\n");
924 } else if (is_hyp_mode_mismatched()) {
925 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
926 __boot_cpu_mode & MODE_MASK);
927 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
929 pr_info("CPU: All CPU(s) started in SVC mode.\n");
933 void __init setup_arch(char **cmdline_p)
935 const struct machine_desc *mdesc;
938 mdesc = setup_machine_fdt(__atags_pointer);
940 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
941 machine_desc = mdesc;
942 machine_name = mdesc->name;
943 dump_stack_set_arch_desc("%s", mdesc->name);
945 if (mdesc->reboot_mode != REBOOT_HARD)
946 reboot_mode = mdesc->reboot_mode;
948 init_mm.start_code = (unsigned long) _text;
949 init_mm.end_code = (unsigned long) _etext;
950 init_mm.end_data = (unsigned long) _edata;
951 init_mm.brk = (unsigned long) _end;
953 /* populate cmd_line too for later use, preserving boot_command_line */
954 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
955 *cmdline_p = cmd_line;
960 early_paging_init(mdesc);
962 setup_dma_zone(mdesc);
963 sanity_check_meminfo();
964 arm_memblock_init(mdesc);
967 request_standard_resources(mdesc);
970 arm_pm_restart = mdesc->restart;
972 unflatten_device_tree();
974 arm_dt_init_cpu_maps();
979 if (!mdesc->smp_init || !mdesc->smp_init()) {
980 if (psci_smp_available())
981 smp_set_ops(&psci_smp_ops);
983 smp_set_ops(mdesc->smp);
986 smp_build_mpidr_hash();
993 reserve_crashkernel();
995 #ifdef CONFIG_MULTI_IRQ_HANDLER
996 handle_arch_irq = mdesc->handle_irq;
1000 #if defined(CONFIG_VGA_CONSOLE)
1001 conswitchp = &vga_con;
1002 #elif defined(CONFIG_DUMMY_CONSOLE)
1003 conswitchp = &dummy_con;
1007 if (mdesc->init_early)
1008 mdesc->init_early();
1012 static int __init topology_init(void)
1016 for_each_possible_cpu(cpu) {
1017 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
1018 cpuinfo->cpu.hotpluggable = 1;
1019 register_cpu(&cpuinfo->cpu, cpu);
1024 subsys_initcall(topology_init);
1026 #ifdef CONFIG_HAVE_PROC_CPU
1027 static int __init proc_cpu_init(void)
1029 struct proc_dir_entry *res;
1031 res = proc_mkdir("cpu", NULL);
1036 fs_initcall(proc_cpu_init);
1039 static const char *hwcap_str[] = {
1065 static const char *hwcap2_str[] = {
1074 static int c_show(struct seq_file *m, void *v)
1079 for_each_online_cpu(i) {
1081 * glibc reads /proc/cpuinfo to determine the number of
1082 * online processors, looking for lines beginning with
1083 * "processor". Give glibc what it expects.
1085 seq_printf(m, "processor\t: %d\n", i);
1086 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1087 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1088 cpu_name, cpuid & 15, elf_platform);
1090 #if defined(CONFIG_SMP)
1091 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1092 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1093 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1095 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1096 loops_per_jiffy / (500000/HZ),
1097 (loops_per_jiffy / (5000/HZ)) % 100);
1099 /* dump out the processor features */
1100 seq_puts(m, "Features\t: ");
1102 for (j = 0; hwcap_str[j]; j++)
1103 if (elf_hwcap & (1 << j))
1104 seq_printf(m, "%s ", hwcap_str[j]);
1106 for (j = 0; hwcap2_str[j]; j++)
1107 if (elf_hwcap2 & (1 << j))
1108 seq_printf(m, "%s ", hwcap2_str[j]);
1110 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1111 seq_printf(m, "CPU architecture: %s\n",
1112 proc_arch[cpu_architecture()]);
1114 if ((cpuid & 0x0008f000) == 0x00000000) {
1116 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1118 if ((cpuid & 0x0008f000) == 0x00007000) {
1120 seq_printf(m, "CPU variant\t: 0x%02x\n",
1121 (cpuid >> 16) & 127);
1124 seq_printf(m, "CPU variant\t: 0x%x\n",
1125 (cpuid >> 20) & 15);
1127 seq_printf(m, "CPU part\t: 0x%03x\n",
1128 (cpuid >> 4) & 0xfff);
1130 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1133 seq_printf(m, "Hardware\t: %s\n", machine_name);
1134 seq_printf(m, "Revision\t: %04x\n", system_rev);
1135 seq_printf(m, "Serial\t\t: %s\n", system_serial);
1140 static void *c_start(struct seq_file *m, loff_t *pos)
1142 return *pos < 1 ? (void *)1 : NULL;
1145 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1151 static void c_stop(struct seq_file *m, void *v)
1155 const struct seq_operations cpuinfo_op = {