arch/arm/mach-at91/board-yl-9200.c

   1 /*
   2  * linux/arch/arm/mach-at91/board-yl-9200.c
   3  *
   4  * Adapted from various board files in arch/arm/mach-at91
   5  *
   6  * Modifications for YL-9200 platform:
   7  *  Copyright (C) 2007 S. Birtles
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/types.h>
  25 #include <linux/gpio.h>
  26 #include <linux/init.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spi/spi.h>
  32 #include <linux/spi/ads7846.h>
  33 #include <linux/mtd/physmap.h>
  34 #include <linux/gpio_keys.h>
  35 #include <linux/input.h>
  36
  37 #include <asm/setup.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/irq.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/irq.h>
  44
  45 #include <mach/hardware.h>
  46 #include <mach/board.h>
  47 #include <mach/at91_aic.h>
  48 #include <mach/at91rm9200_mc.h>
  49 #include <mach/at91_ramc.h>
  50 #include <mach/cpu.h>
  51
  52 #include "generic.h"
  53
  54
  55 static void __init yl9200_init_early(void)
  56 {
  57         /* Set cpu type: PQFP */
  58         at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
  59
  60         /* Initialize processor: 18.432 MHz crystal */
  61         at91_initialize(18432000);
  62 }
  63
  64 /*
  65  * LEDs
  66  */
  67 static struct gpio_led yl9200_leds[] = {
  68         {       /* D2 */
  69                 .name                   = "led2",
  70                 .gpio                   = AT91_PIN_PB17,
  71                 .active_low             = 1,
  72                 .default_trigger        = "timer",
  73         },
  74         {       /* D3 */
  75                 .name                   = "led3",
  76                 .gpio                   = AT91_PIN_PB16,
  77                 .active_low             = 1,
  78                 .default_trigger        = "heartbeat",
  79         },
  80         {       /* D4 */
  81                 .name                   = "led4",
  82                 .gpio                   = AT91_PIN_PB15,
  83                 .active_low             = 1,
  84         },
  85         {       /* D5 */
  86                 .name                   = "led5",
  87                 .gpio                   = AT91_PIN_PB8,
  88                 .active_low             = 1,
  89         }
  90 };
  91
  92 /*
  93  * Ethernet
  94  */
  95 static struct macb_platform_data __initdata yl9200_eth_data = {
  96         .phy_irq_pin            = AT91_PIN_PB28,
  97         .is_rmii                = 1,
  98 };
  99
 100 /*
 101  * USB Host
 102  */
 103 static struct at91_usbh_data __initdata yl9200_usbh_data = {
 104         .ports                  = 1,    /* PQFP version of AT91RM9200 */
 105         .vbus_pin               = {-EINVAL, -EINVAL},
 106         .overcurrent_pin= {-EINVAL, -EINVAL},
 107 };
 108
 109 /*
 110  * USB Device
 111  */
 112 static struct at91_udc_data __initdata yl9200_udc_data = {
 113         .pullup_pin             = AT91_PIN_PC4,
 114         .vbus_pin               = AT91_PIN_PC5,
 115         .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
 116
 117 };
 118
 119 /*
 120  * MMC
 121  */
 122 static struct at91_mmc_data __initdata yl9200_mmc_data = {
 123         .det_pin        = AT91_PIN_PB9,
 124         .wire4          = 1,
 125         .wp_pin         = -EINVAL,
 126         .vcc_pin        = -EINVAL,
 127 };
 128
 129 /*
 130  * NAND Flash
 131  */
 132 static struct mtd_partition __initdata yl9200_nand_partition[] = {
 133         {
 134                 .name   = "AT91 NAND partition 1, boot",
 135                 .offset = 0,
 136                 .size   = SZ_256K
 137         },
 138         {
 139                 .name   = "AT91 NAND partition 2, kernel",
 140                 .offset = MTDPART_OFS_NXTBLK,
 141                 .size   = (2 * SZ_1M) - SZ_256K
 142         },
 143         {
 144                 .name   = "AT91 NAND partition 3, filesystem",
 145                 .offset = MTDPART_OFS_NXTBLK,
 146                 .size   = 14 * SZ_1M
 147         },
 148         {
 149                 .name   = "AT91 NAND partition 4, storage",
 150                 .offset = MTDPART_OFS_NXTBLK,
 151                 .size   = SZ_16M
 152         },
 153         {
 154                 .name   = "AT91 NAND partition 5, ext-fs",
 155                 .offset = MTDPART_OFS_NXTBLK,
 156                 .size   = SZ_32M
 157         }
 158 };
 159
 160 static struct atmel_nand_data __initdata yl9200_nand_data = {
 161         .ale            = 6,
 162         .cle            = 7,
 163         .det_pin        = -EINVAL,
 164         .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
 165         .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
 166         .ecc_mode       = NAND_ECC_SOFT,
 167         .parts          = yl9200_nand_partition,
 168         .num_parts      = ARRAY_SIZE(yl9200_nand_partition),
 169 };
 170
 171 /*
 172  * NOR Flash
 173  */
 174 #define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
 175 #define YL9200_FLASH_SIZE       SZ_16M
 176
 177 static struct mtd_partition yl9200_flash_partitions[] = {
 178         {
 179                 .name           = "Bootloader",
 180                 .offset         = 0,
 181                 .size           = SZ_256K,
 182                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 183         },
 184         {
 185                 .name           = "Kernel",
 186                 .offset         = MTDPART_OFS_NXTBLK,
 187                 .size           = (2 * SZ_1M) - SZ_256K
 188         },
 189         {
 190                 .name           = "Filesystem",
 191                 .offset         = MTDPART_OFS_NXTBLK,
 192                 .size           = MTDPART_SIZ_FULL
 193         }
 194 };
 195
 196 static struct physmap_flash_data yl9200_flash_data = {
 197         .width          = 2,
 198         .parts          = yl9200_flash_partitions,
 199         .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
 200 };
 201
 202 static struct resource yl9200_flash_resources[] = {
 203         {
 204                 .start  = YL9200_FLASH_BASE,
 205                 .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
 206                 .flags  = IORESOURCE_MEM,
 207         }
 208 };
 209
 210 static struct platform_device yl9200_flash = {
 211         .name           = "physmap-flash",
 212         .id             = 0,
 213         .dev            = {
 214                                 .platform_data  = &yl9200_flash_data,
 215                         },
 216         .resource       = yl9200_flash_resources,
 217         .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
 218 };
 219
 220 /*
 221  * I2C (TWI)
 222  */
 223 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
 224         {       /* EEPROM */
 225                 I2C_BOARD_INFO("24c128", 0x50),
 226         }
 227 };
 228
 229 /*
 230  * GPIO Buttons
 231 */
 232 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 233 static struct gpio_keys_button yl9200_buttons[] = {
 234         {
 235                 .gpio           = AT91_PIN_PA24,
 236                 .code           = BTN_2,
 237                 .desc           = "SW2",
 238                 .active_low     = 1,
 239                 .wakeup         = 1,
 240         },
 241         {
 242                 .gpio           = AT91_PIN_PB1,
 243                 .code           = BTN_3,
 244                 .desc           = "SW3",
 245                 .active_low     = 1,
 246                 .wakeup         = 1,
 247         },
 248         {
 249                 .gpio           = AT91_PIN_PB2,
 250                 .code           = BTN_4,
 251                 .desc           = "SW4",
 252                 .active_low     = 1,
 253                 .wakeup         = 1,
 254         },
 255         {
 256                 .gpio           = AT91_PIN_PB6,
 257                 .code           = BTN_5,
 258                 .desc           = "SW5",
 259                 .active_low     = 1,
 260                 .wakeup         = 1,
 261         }
 262 };
 263
 264 static struct gpio_keys_platform_data yl9200_button_data = {
 265         .buttons        = yl9200_buttons,
 266         .nbuttons       = ARRAY_SIZE(yl9200_buttons),
 267 };
 268
 269 static struct platform_device yl9200_button_device = {
 270         .name           = "gpio-keys",
 271         .id             = -1,
 272         .num_resources  = 0,
 273         .dev            = {
 274                 .platform_data  = &yl9200_button_data,
 275         }
 276 };
 277
 278 static void __init yl9200_add_device_buttons(void)
 279 {
 280         at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
 281         at91_set_deglitch(AT91_PIN_PA24, 1);
 282         at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
 283         at91_set_deglitch(AT91_PIN_PB1, 1);
 284         at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
 285         at91_set_deglitch(AT91_PIN_PB2, 1);
 286         at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
 287         at91_set_deglitch(AT91_PIN_PB6, 1);
 288
 289         /* Enable buttons (Sheet 5) */
 290         at91_set_gpio_output(AT91_PIN_PB7, 1);
 291
 292         platform_device_register(&yl9200_button_device);
 293 }
 294 #else
 295 static void __init yl9200_add_device_buttons(void) {}
 296 #endif
 297
 298 /*
 299  * Touchscreen
 300  */
 301 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 302 static int ads7843_pendown_state(void)
 303 {
 304         return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
 305 }
 306
 307 static struct ads7846_platform_data ads_info = {
 308         .model                  = 7843,
 309         .x_min                  = 150,
 310         .x_max                  = 3830,
 311         .y_min                  = 190,
 312         .y_max                  = 3830,
 313         .vref_delay_usecs       = 100,
 314
 315         /* For a 8" touch-screen */
 316         // .x_plate_ohms                = 603,
 317         // .y_plate_ohms                = 332,
 318
 319         /* For a 10.4" touch-screen */
 320         // .x_plate_ohms                = 611,
 321         // .y_plate_ohms                = 325,
 322
 323         .x_plate_ohms           = 576,
 324         .y_plate_ohms           = 366,
 325
 326         .pressure_max           = 15000, /* generally nonsense on the 7843 */
 327         .debounce_max           = 1,
 328         .debounce_rep           = 0,
 329         .debounce_tol           = (~0),
 330         .get_pendown_state      = ads7843_pendown_state,
 331 };
 332
 333 static void __init yl9200_add_device_ts(void)
 334 {
 335         at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
 336         at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
 337 }
 338 #else
 339 static void __init yl9200_add_device_ts(void) {}
 340 #endif
 341
 342 /*
 343  * SPI devices
 344  */
 345 static struct spi_board_info yl9200_spi_devices[] = {
 346 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 347         {       /* Touchscreen */
 348                 .modalias       = "ads7846",
 349                 .chip_select    = 0,
 350                 .max_speed_hz   = 5000 * 26,
 351                 .platform_data  = &ads_info,
 352                 .irq            = AT91_PIN_PB11,
 353         },
 354 #endif
 355         {       /* CAN */
 356                 .modalias       = "mcp2510",
 357                 .chip_select    = 1,
 358                 .max_speed_hz   = 25000 * 26,
 359                 .irq            = AT91_PIN_PC0,
 360         }
 361 };
 362
 363 /*
 364  * LCD / VGA
 365  *
 366  * EPSON S1D13806 FB (discontinued chip)
 367  * EPSON S1D13506 FB
 368  */
 369 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 370 #include <video/s1d13xxxfb.h>
 371
 372
 373 static void yl9200_init_video(void)
 374 {
 375         /* NWAIT Signal */
 376         at91_set_A_periph(AT91_PIN_PC6, 0);
 377
 378         /* Initialization of the Static Memory Controller for Chip Select 2 */
 379         at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
 380                         | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
 381                         | AT91_SMC_TDF_(0x100)                  /* float time */
 382         );
 383 }
 384
 385 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
 386 {
 387         {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
 388         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 389         {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
 390         {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
 391         {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
 392         {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
 393         {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
 394         {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
 395         {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
 396         {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
 397         {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
 398         {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
 399         {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
 400         {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
 401         {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
 402         {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
 403         {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
 404         {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
 405         {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
 406         {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
 407         {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
 408         {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
 409         {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
 410         {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
 411         {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
 412         {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
 413         {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
 414         {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
 415         {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
 416         {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
 417         {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
 418         {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
 419         {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
 420         {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
 421         {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
 422         {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
 423         {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
 424         {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
 425         {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
 426         {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
 427         {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
 428         {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
 429         {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
 430         {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
 431         {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
 432         {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
 433         {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
 434         {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
 435         {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
 436         {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
 437         {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
 438         {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
 439         {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
 440         {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
 441         {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
 442         {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
 443         {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
 444         {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
 445         {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
 446         {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
 447         {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
 448         {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
 449         {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
 450         {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
 451         {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
 452         {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
 453         {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
 454         {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
 455         {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
 456         {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
 457         {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
 458         {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
 459         {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
 460         {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
 461         {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
 462         {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
 463         {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
 464         {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
 465         {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
 466         {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
 467         {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
 468         {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
 469         {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
 470         {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
 471         {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
 472         {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
 473         {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
 474         {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
 475         {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
 476         {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
 477         {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
 478         {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
 479         {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
 480         {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
 481         {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
 482         {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
 483         {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
 484         {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
 485         {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
 486         {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
 487         {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
 488         {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
 489         {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
 490         {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
 491         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 492 };
 493
 494 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
 495         .initregs               = yl9200_s1dfb_initregs,
 496         .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
 497         .platform_init_video    = yl9200_init_video,
 498 };
 499
 500 #define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
 501 #define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
 502 #define YL9200_FB_VMEM_SIZE     SZ_2M
 503
 504 static struct resource yl9200_s1dfb_resource[] = {
 505         [0] = { /* video mem */
 506                 .name   = "s1d13xxxfb memory",
 507                 .start  = YL9200_FB_VMEM_BASE,
 508                 .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
 509                 .flags  = IORESOURCE_MEM,
 510         },
 511         [1] = { /* video registers */
 512                 .name   = "s1d13xxxfb registers",
 513                 .start  = YL9200_FB_REG_BASE,
 514                 .end    = YL9200_FB_REG_BASE + SZ_512 -1,
 515                 .flags  = IORESOURCE_MEM,
 516         },
 517 };
 518
 519 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
 520
 521 static struct platform_device yl9200_s1dfb_device = {
 522         .name           = "s1d13806fb",
 523         .id             = -1,
 524         .dev    = {
 525                 .dma_mask               = &s1dfb_dmamask,
 526                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 527                 .platform_data          = &yl9200_s1dfb_pdata,
 528         },
 529         .resource       = yl9200_s1dfb_resource,
 530         .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
 531 };
 532
 533 void __init yl9200_add_device_video(void)
 534 {
 535         platform_device_register(&yl9200_s1dfb_device);
 536 }
 537 #else
 538 void __init yl9200_add_device_video(void) {}
 539 #endif
 540
 541
 542 static void __init yl9200_board_init(void)
 543 {
 544         /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
 545         at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
 546
 547         /* Serial */
 548         /* DBGU on ttyS0. (Rx & Tx only) */
 549         at91_register_uart(0, 0, 0);
 550
 551         /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
 552         at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
 553                         | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
 554                         | ATMEL_UART_RI);
 555
 556         /* USART0 on ttyS2. (Rx & Tx only to JP3) */
 557         at91_register_uart(AT91RM9200_ID_US0, 2, 0);
 558
 559         /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
 560         at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
 561         at91_add_device_serial();
 562         /* Ethernet */
 563         at91_add_device_eth(&yl9200_eth_data);
 564         /* USB Host */
 565         at91_add_device_usbh(&yl9200_usbh_data);
 566         /* USB Device */
 567         at91_add_device_udc(&yl9200_udc_data);
 568         /* I2C */
 569         at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
 570         /* MMC */
 571         at91_add_device_mmc(0, &yl9200_mmc_data);
 572         /* NAND */
 573         at91_add_device_nand(&yl9200_nand_data);
 574         /* NOR Flash */
 575         platform_device_register(&yl9200_flash);
 576 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 577         /* SPI */
 578         at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
 579         /* Touchscreen */
 580         yl9200_add_device_ts();
 581 #endif
 582         /* LEDs. */
 583         at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
 584         /* Push Buttons */
 585         yl9200_add_device_buttons();
 586         /* VGA */
 587         yl9200_add_device_video();
 588 }
 589
 590 MACHINE_START(YL9200, "uCdragon YL-9200")
 591         /* Maintainer: S.Birtles */
 592         .timer          = &at91rm9200_timer,
 593         .map_io         = at91_map_io,
 594         .handle_irq     = at91_aic_handle_irq,
 595         .init_early     = yl9200_init_early,
 596         .init_irq       = at91_init_irq_default,
 597         .init_machine   = yl9200_board_init,
 598 MACHINE_END