arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13
  14 #include <asm/mach/map.h>
  15
  16 #include <mach/hardware.h>
  17 #include <mach/cpu.h>
  18 #include <mach/at91_dbgu.h>
  19 #include <mach/at91_pmc.h>
  20 #include <mach/at91_shdwc.h>
  21
  22 #include "soc.h"
  23 #include "generic.h"
  24
  25 struct at91_init_soc __initdata at91_boot_soc;
  26
  27 struct at91_socinfo at91_soc_initdata;
  28 EXPORT_SYMBOL(at91_soc_initdata);
  29
  30 void __init at91rm9200_set_type(int type)
  31 {
  32         if (type == ARCH_REVISON_9200_PQFP)
  33                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  34         else
  35                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  36
  37         pr_info("AT91: filled in soc subtype: %s\n",
  38                 at91_get_soc_subtype(&at91_soc_initdata));
  39 }
  40
  41 void __init at91_init_irq_default(void)
  42 {
  43         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  44 }
  45
  46 void __init at91_init_interrupts(unsigned int *priority)
  47 {
  48         /* Initialize the AIC interrupt controller */
  49         at91_aic_init(priority);
  50
  51         /* Enable GPIO interrupts */
  52         at91_gpio_irq_setup();
  53 }
  54
  55 void __iomem *at91_ramc_base[2];
  56
  57 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  58 {
  59         if (id < 0 || id > 1) {
  60                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  61                 BUG();
  62         }
  63         at91_ramc_base[id] = ioremap(addr, size);
  64         if (!at91_ramc_base[id])
  65                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  66 }
  67
  68 static struct map_desc sram_desc[2] __initdata;
  69
  70 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  71 {
  72         struct map_desc *desc = &sram_desc[bank];
  73
  74         desc->virtual = AT91_IO_VIRT_BASE - length;
  75         if (bank > 0)
  76                 desc->virtual -= sram_desc[bank - 1].length;
  77
  78         desc->pfn = __phys_to_pfn(base);
  79         desc->length = length;
  80         desc->type = MT_DEVICE;
  81
  82         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  83                 base, length, desc->virtual);
  84
  85         iotable_init(desc, 1);
  86 }
  87
  88 static struct map_desc at91_io_desc __initdata = {
  89         .virtual        = AT91_VA_BASE_SYS,
  90         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  91         .length         = SZ_16K,
  92         .type           = MT_DEVICE,
  93 };
  94
  95 static void __init soc_detect(u32 dbgu_base)
  96 {
  97         u32 cidr, socid;
  98
  99         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 100         socid = cidr & ~AT91_CIDR_VERSION;
 101
 102         switch (socid) {
 103         case ARCH_ID_AT91RM9200:
 104                 at91_soc_initdata.type = AT91_SOC_RM9200;
 105                 at91_boot_soc = at91rm9200_soc;
 106                 break;
 107
 108         case ARCH_ID_AT91SAM9260:
 109                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 110                 at91_boot_soc = at91sam9260_soc;
 111                 break;
 112
 113         case ARCH_ID_AT91SAM9261:
 114                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 115                 at91_boot_soc = at91sam9261_soc;
 116                 break;
 117
 118         case ARCH_ID_AT91SAM9263:
 119                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 120                 at91_boot_soc = at91sam9263_soc;
 121                 break;
 122
 123         case ARCH_ID_AT91SAM9G20:
 124                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 125                 at91_boot_soc = at91sam9260_soc;
 126                 break;
 127
 128         case ARCH_ID_AT91SAM9G45:
 129                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 130                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 131                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 132                 at91_boot_soc = at91sam9g45_soc;
 133                 break;
 134
 135         case ARCH_ID_AT91SAM9RL64:
 136                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 137                 at91_boot_soc = at91sam9rl_soc;
 138                 break;
 139
 140         case ARCH_ID_AT91SAM9X5:
 141                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 142                 at91_boot_soc = at91sam9x5_soc;
 143                 break;
 144         }
 145
 146         /* at91sam9g10 */
 147         if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 148                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 149                 at91_boot_soc = at91sam9261_soc;
 150         }
 151         /* at91sam9xe */
 152         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 153                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 154                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 155                 at91_boot_soc = at91sam9260_soc;
 156         }
 157
 158         if (!at91_soc_is_detected())
 159                 return;
 160
 161         at91_soc_initdata.cidr = cidr;
 162
 163         /* sub version of soc */
 164         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 165
 166         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 167                 switch (at91_soc_initdata.exid) {
 168                 case ARCH_EXID_AT91SAM9M10:
 169                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 170                         break;
 171                 case ARCH_EXID_AT91SAM9G46:
 172                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 173                         break;
 174                 case ARCH_EXID_AT91SAM9M11:
 175                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 176                         break;
 177                 }
 178         }
 179
 180         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 181                 switch (at91_soc_initdata.exid) {
 182                 case ARCH_EXID_AT91SAM9G15:
 183                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 184                         break;
 185                 case ARCH_EXID_AT91SAM9G35:
 186                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 187                         break;
 188                 case ARCH_EXID_AT91SAM9X35:
 189                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 190                         break;
 191                 case ARCH_EXID_AT91SAM9G25:
 192                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 193                         break;
 194                 case ARCH_EXID_AT91SAM9X25:
 195                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 196                         break;
 197                 }
 198         }
 199 }
 200
 201 static const char *soc_name[] = {
 202         [AT91_SOC_RM9200]       = "at91rm9200",
 203         [AT91_SOC_SAM9260]      = "at91sam9260",
 204         [AT91_SOC_SAM9261]      = "at91sam9261",
 205         [AT91_SOC_SAM9263]      = "at91sam9263",
 206         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 207         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 208         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 209         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 210         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 211         [AT91_SOC_NONE]         = "Unknown"
 212 };
 213
 214 const char *at91_get_soc_type(struct at91_socinfo *c)
 215 {
 216         return soc_name[c->type];
 217 }
 218 EXPORT_SYMBOL(at91_get_soc_type);
 219
 220 static const char *soc_subtype_name[] = {
 221         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 222         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 223         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 224         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 225         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 226         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 227         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 228         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 229         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 230         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 231         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 232         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 233         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 234 };
 235
 236 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 237 {
 238         return soc_subtype_name[c->subtype];
 239 }
 240 EXPORT_SYMBOL(at91_get_soc_subtype);
 241
 242 void __init at91_map_io(void)
 243 {
 244         /* Map peripherals */
 245         iotable_init(&at91_io_desc, 1);
 246
 247         at91_soc_initdata.type = AT91_SOC_NONE;
 248         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 249
 250         soc_detect(AT91_BASE_DBGU0);
 251         if (!at91_soc_is_detected())
 252                 soc_detect(AT91_BASE_DBGU1);
 253
 254         if (!at91_soc_is_detected())
 255                 panic("AT91: Impossible to detect the SOC type");
 256
 257         pr_info("AT91: Detected soc type: %s\n",
 258                 at91_get_soc_type(&at91_soc_initdata));
 259         pr_info("AT91: Detected soc subtype: %s\n",
 260                 at91_get_soc_subtype(&at91_soc_initdata));
 261
 262         if (!at91_soc_is_enabled())
 263                 panic("AT91: Soc not enabled");
 264
 265         if (at91_boot_soc.map_io)
 266                 at91_boot_soc.map_io();
 267 }
 268
 269 void __iomem *at91_shdwc_base = NULL;
 270
 271 static void at91sam9_poweroff(void)
 272 {
 273         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 274 }
 275
 276 void __init at91_ioremap_shdwc(u32 base_addr)
 277 {
 278         at91_shdwc_base = ioremap(base_addr, 16);
 279         if (!at91_shdwc_base)
 280                 panic("Impossible to ioremap at91_shdwc_base\n");
 281         pm_power_off = at91sam9_poweroff;
 282 }
 283
 284 void __iomem *at91_rstc_base;
 285
 286 void __init at91_ioremap_rstc(u32 base_addr)
 287 {
 288         at91_rstc_base = ioremap(base_addr, 16);
 289         if (!at91_rstc_base)
 290                 panic("Impossible to ioremap at91_rstc_base\n");
 291 }
 292
 293 void __iomem *at91_matrix_base;
 294
 295 void __init at91_ioremap_matrix(u32 base_addr)
 296 {
 297         at91_matrix_base = ioremap(base_addr, 512);
 298         if (!at91_matrix_base)
 299                 panic("Impossible to ioremap at91_matrix_base\n");
 300 }
 301
 302 #if defined(CONFIG_OF)
 303 static struct of_device_id rstc_ids[] = {
 304         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 305         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 306         { /*sentinel*/ }
 307 };
 308
 309 static void at91_dt_rstc(void)
 310 {
 311         struct device_node *np;
 312         const struct of_device_id *of_id;
 313
 314         np = of_find_matching_node(NULL, rstc_ids);
 315         if (!np)
 316                 panic("unable to find compatible rstc node in dtb\n");
 317
 318         at91_rstc_base = of_iomap(np, 0);
 319         if (!at91_rstc_base)
 320                 panic("unable to map rstc cpu registers\n");
 321
 322         of_id = of_match_node(rstc_ids, np);
 323         if (!of_id)
 324                 panic("AT91: rtsc no restart function availlable\n");
 325
 326         arm_pm_restart = of_id->data;
 327
 328         of_node_put(np);
 329 }
 330
 331 static struct of_device_id ramc_ids[] = {
 332         { .compatible = "atmel,at91sam9260-sdramc" },
 333         { .compatible = "atmel,at91sam9g45-ddramc" },
 334         { /*sentinel*/ }
 335 };
 336
 337 static void at91_dt_ramc(void)
 338 {
 339         struct device_node *np;
 340
 341         np = of_find_matching_node(NULL, ramc_ids);
 342         if (!np)
 343                 panic("unable to find compatible ram conroller node in dtb\n");
 344
 345         at91_ramc_base[0] = of_iomap(np, 0);
 346         if (!at91_ramc_base[0])
 347                 panic("unable to map ramc[0] cpu registers\n");
 348         /* the controller may have 2 banks */
 349         at91_ramc_base[1] = of_iomap(np, 1);
 350
 351         of_node_put(np);
 352 }
 353
 354 static struct of_device_id shdwc_ids[] = {
 355         { .compatible = "atmel,at91sam9260-shdwc", },
 356         { .compatible = "atmel,at91sam9rl-shdwc", },
 357         { .compatible = "atmel,at91sam9x5-shdwc", },
 358         { /*sentinel*/ }
 359 };
 360
 361 static const char *shdwc_wakeup_modes[] = {
 362         [AT91_SHDW_WKMODE0_NONE]        = "none",
 363         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 364         [AT91_SHDW_WKMODE0_LOW]         = "low",
 365         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 366 };
 367
 368 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 369 {
 370         const char *pm;
 371         int err, i;
 372
 373         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 374         if (err < 0)
 375                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 376
 377         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 378                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 379                         return i;
 380
 381         return -ENODEV;
 382 }
 383
 384 static void at91_dt_shdwc(void)
 385 {
 386         struct device_node *np;
 387         int wakeup_mode;
 388         u32 reg;
 389         u32 mode = 0;
 390
 391         np = of_find_matching_node(NULL, shdwc_ids);
 392         if (!np) {
 393                 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
 394                 return;
 395         }
 396
 397         at91_shdwc_base = of_iomap(np, 0);
 398         if (!at91_shdwc_base)
 399                 panic("AT91: unable to map shdwc cpu registers\n");
 400
 401         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 402         if (wakeup_mode < 0) {
 403                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 404                 goto end;
 405         }
 406
 407         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 408                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 409                         pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
 410                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 411                         reg = AT91_SHDW_CPTWK0_MAX;
 412                 }
 413                 mode |= AT91_SHDW_CPTWK0_(reg);
 414         }
 415
 416         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 417                         mode |= AT91_SHDW_RTCWKEN;
 418
 419         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 420                         mode |= AT91_SHDW_RTTWKEN;
 421
 422         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 423
 424 end:
 425         pm_power_off = at91sam9_poweroff;
 426
 427         of_node_put(np);
 428 }
 429
 430 void __init at91_dt_initialize(void)
 431 {
 432         at91_dt_rstc();
 433         at91_dt_ramc();
 434         at91_dt_shdwc();
 435
 436         /* Init clock subsystem */
 437         at91_dt_clock_init();
 438
 439         /* Register the processor-specific clocks */
 440         at91_boot_soc.register_clocks();
 441
 442         at91_boot_soc.init();
 443 }
 444 #endif
 445
 446 void __init at91_initialize(unsigned long main_clock)
 447 {
 448         at91_boot_soc.ioremap_registers();
 449
 450         /* Init clock subsystem */
 451         at91_clock_init(main_clock);
 452
 453         /* Register the processor-specific clocks */
 454         at91_boot_soc.register_clocks();
 455
 456         at91_boot_soc.init();
 457 }