arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqchip.h>
  16 #include <linux/io.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/sched.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/of.h>
  22 #include <linux/of_fdt.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/export.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/of_address.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clk-provider.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/irqchip/chained_irq.h>
  31
  32 #include <asm/proc-fns.h>
  33 #include <asm/exception.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/cacheflush.h>
  38
  39 #include <mach/regs-irq.h>
  40 #include <mach/regs-pmu.h>
  41 #include <mach/regs-gpio.h>
  42 #include <mach/irqs.h>
  43
  44 #include <plat/cpu.h>
  45 #include <plat/devs.h>
  46 #include <plat/pm.h>
  47 #include <plat/sdhci.h>
  48 #include <plat/gpio-cfg.h>
  49 #include <plat/adc-core.h>
  50 #include <plat/fb-core.h>
  51 #include <plat/fimc-core.h>
  52 #include <plat/iic-core.h>
  53 #include <plat/tv-core.h>
  54 #include <plat/spi-core.h>
  55 #include <plat/regs-serial.h>
  56
  57 #include "common.h"
  58 #define L2_AUX_VAL 0x7C470001
  59 #define L2_AUX_MASK 0xC200ffff
  60
  61 static const char name_exynos4210[] = "EXYNOS4210";
  62 static const char name_exynos4212[] = "EXYNOS4212";
  63 static const char name_exynos4412[] = "EXYNOS4412";
  64 static const char name_exynos5250[] = "EXYNOS5250";
  65 static const char name_exynos5440[] = "EXYNOS5440";
  66
  67 static void exynos4_map_io(void);
  68 static void exynos5_map_io(void);
  69 static void exynos5440_map_io(void);
  70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  71 static int exynos_init(void);
  72
  73 unsigned long xxti_f = 0, xusbxti_f = 0;
  74
  75 static struct cpu_table cpu_ids[] __initdata = {
  76         {
  77                 .idcode         = EXYNOS4210_CPU_ID,
  78                 .idmask         = EXYNOS4_CPU_MASK,
  79                 .map_io         = exynos4_map_io,
  80                 .init_uarts     = exynos4_init_uarts,
  81                 .init           = exynos_init,
  82                 .name           = name_exynos4210,
  83         }, {
  84                 .idcode         = EXYNOS4212_CPU_ID,
  85                 .idmask         = EXYNOS4_CPU_MASK,
  86                 .map_io         = exynos4_map_io,
  87                 .init_uarts     = exynos4_init_uarts,
  88                 .init           = exynos_init,
  89                 .name           = name_exynos4212,
  90         }, {
  91                 .idcode         = EXYNOS4412_CPU_ID,
  92                 .idmask         = EXYNOS4_CPU_MASK,
  93                 .map_io         = exynos4_map_io,
  94                 .init_uarts     = exynos4_init_uarts,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos4412,
  97         }, {
  98                 .idcode         = EXYNOS5250_SOC_ID,
  99                 .idmask         = EXYNOS5_SOC_MASK,
 100                 .map_io         = exynos5_map_io,
 101                 .init           = exynos_init,
 102                 .name           = name_exynos5250,
 103         }, {
 104                 .idcode         = EXYNOS5440_SOC_ID,
 105                 .idmask         = EXYNOS5_SOC_MASK,
 106                 .map_io         = exynos5440_map_io,
 107                 .init           = exynos_init,
 108                 .name           = name_exynos5440,
 109         },
 110 };
 111
 112 /* Initial IO mappings */
 113
 114 static struct map_desc exynos_iodesc[] __initdata = {
 115         {
 116                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 117                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 #ifdef CONFIG_ARCH_EXYNOS5
 124 static struct map_desc exynos5440_iodesc[] __initdata = {
 125         {
 126                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 127                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         },
 131 };
 132 #endif
 133
 134 static struct map_desc exynos4_iodesc[] __initdata = {
 135         {
 136                 .virtual        = (unsigned long)S3C_VA_SYS,
 137                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 138                 .length         = SZ_64K,
 139                 .type           = MT_DEVICE,
 140         }, {
 141                 .virtual        = (unsigned long)S3C_VA_TIMER,
 142                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 143                 .length         = SZ_16K,
 144                 .type           = MT_DEVICE,
 145         }, {
 146                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 147                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE,
 150         }, {
 151                 .virtual        = (unsigned long)S5P_VA_SROMC,
 152                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE,
 155         }, {
 156                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 157                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE,
 160         }, {
 161                 .virtual        = (unsigned long)S5P_VA_PMU,
 162                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 163                 .length         = SZ_64K,
 164                 .type           = MT_DEVICE,
 165         }, {
 166                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 167                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 168                 .length         = SZ_4K,
 169                 .type           = MT_DEVICE,
 170         }, {
 171                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 172                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 173                 .length         = SZ_64K,
 174                 .type           = MT_DEVICE,
 175         }, {
 176                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 177                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 178                 .length         = SZ_64K,
 179                 .type           = MT_DEVICE,
 180         }, {
 181                 .virtual        = (unsigned long)S3C_VA_UART,
 182                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 183                 .length         = SZ_512K,
 184                 .type           = MT_DEVICE,
 185         }, {
 186                 .virtual        = (unsigned long)S5P_VA_CMU,
 187                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 188                 .length         = SZ_128K,
 189                 .type           = MT_DEVICE,
 190         }, {
 191                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 192                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 193                 .length         = SZ_8K,
 194                 .type           = MT_DEVICE,
 195         }, {
 196                 .virtual        = (unsigned long)S5P_VA_L2CC,
 197                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 198                 .length         = SZ_4K,
 199                 .type           = MT_DEVICE,
 200         }, {
 201                 .virtual        = (unsigned long)S5P_VA_DMC0,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 203                 .length         = SZ_64K,
 204                 .type           = MT_DEVICE,
 205         }, {
 206                 .virtual        = (unsigned long)S5P_VA_DMC1,
 207                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 208                 .length         = SZ_64K,
 209                 .type           = MT_DEVICE,
 210         }, {
 211                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 212                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 213                 .length         = SZ_4K,
 214                 .type           = MT_DEVICE,
 215         },
 216 };
 217
 218 static struct map_desc exynos4_iodesc0[] __initdata = {
 219         {
 220                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 221                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 222                 .length         = SZ_4K,
 223                 .type           = MT_DEVICE,
 224         },
 225 };
 226
 227 static struct map_desc exynos4_iodesc1[] __initdata = {
 228         {
 229                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 230                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         },
 234 };
 235
 236 static struct map_desc exynos4210_iodesc[] __initdata = {
 237         {
 238                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 239                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 240                 .length         = SZ_4K,
 241                 .type           = MT_DEVICE,
 242         },
 243 };
 244
 245 static struct map_desc exynos4x12_iodesc[] __initdata = {
 246         {
 247                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 248                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 249                 .length         = SZ_4K,
 250                 .type           = MT_DEVICE,
 251         },
 252 };
 253
 254 static struct map_desc exynos5250_iodesc[] __initdata = {
 255         {
 256                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 257                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 258                 .length         = SZ_4K,
 259                 .type           = MT_DEVICE,
 260         },
 261 };
 262
 263 static struct map_desc exynos5_iodesc[] __initdata = {
 264         {
 265                 .virtual        = (unsigned long)S3C_VA_SYS,
 266                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 267                 .length         = SZ_64K,
 268                 .type           = MT_DEVICE,
 269         }, {
 270                 .virtual        = (unsigned long)S3C_VA_TIMER,
 271                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 272                 .length         = SZ_16K,
 273                 .type           = MT_DEVICE,
 274         }, {
 275                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 276                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 277                 .length         = SZ_4K,
 278                 .type           = MT_DEVICE,
 279         }, {
 280                 .virtual        = (unsigned long)S5P_VA_SROMC,
 281                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 282                 .length         = SZ_4K,
 283                 .type           = MT_DEVICE,
 284         }, {
 285                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 286                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 287                 .length         = SZ_4K,
 288                 .type           = MT_DEVICE,
 289         }, {
 290                 .virtual        = (unsigned long)S5P_VA_CMU,
 291                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 292                 .length         = 144 * SZ_1K,
 293                 .type           = MT_DEVICE,
 294         }, {
 295                 .virtual        = (unsigned long)S5P_VA_PMU,
 296                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 297                 .length         = SZ_64K,
 298                 .type           = MT_DEVICE,
 299         }, {
 300                 .virtual        = (unsigned long)S3C_VA_UART,
 301                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 302                 .length         = SZ_512K,
 303                 .type           = MT_DEVICE,
 304         },
 305 };
 306
 307 static struct map_desc exynos5440_iodesc0[] __initdata = {
 308         {
 309                 .virtual        = (unsigned long)S3C_VA_UART,
 310                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 311                 .length         = SZ_512K,
 312                 .type           = MT_DEVICE,
 313         },
 314 };
 315
 316 void exynos4_restart(char mode, const char *cmd)
 317 {
 318         __raw_writel(0x1, S5P_SWRESET);
 319 }
 320
 321 void exynos5_restart(char mode, const char *cmd)
 322 {
 323         struct device_node *np;
 324         u32 val;
 325         void __iomem *addr;
 326
 327         if (of_machine_is_compatible("samsung,exynos5250")) {
 328                 val = 0x1;
 329                 addr = EXYNOS_SWRESET;
 330         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 331                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 332                 addr = of_iomap(np, 0) + 0xcc;
 333                 val = (0xfff << 20) | (0x1 << 16);
 334         } else {
 335                 pr_err("%s: cannot support non-DT\n", __func__);
 336                 return;
 337         }
 338
 339         __raw_writel(val, addr);
 340 }
 341
 342 void __init exynos_init_late(void)
 343 {
 344         if (of_machine_is_compatible("samsung,exynos5440"))
 345                 /* to be supported later */
 346                 return;
 347
 348         exynos_pm_late_initcall();
 349 }
 350
 351 /*
 352  * exynos_map_io
 353  *
 354  * register the standard cpu IO areas
 355  */
 356
 357 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 358 {
 359         struct map_desc *iodesc = exynos_iodesc;
 360         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 361 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 362         unsigned long root = of_get_flat_dt_root();
 363
 364         /* initialize the io descriptors we need for initialization */
 365         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 366                 iodesc = exynos5440_iodesc;
 367                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 368         }
 369 #endif
 370
 371         iotable_init(iodesc, iodesc_sz);
 372
 373         if (mach_desc)
 374                 iotable_init(mach_desc, size);
 375
 376         /* detect cpu id and rev. */
 377         s5p_init_cpu(S5P_VA_CHIPID);
 378
 379         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 380 }
 381
 382 static void __init exynos4_map_io(void)
 383 {
 384         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 385
 386         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 387                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 388         else
 389                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 390
 391         if (soc_is_exynos4210())
 392                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 393         if (soc_is_exynos4212() || soc_is_exynos4412())
 394                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 395
 396         /* initialize device information early */
 397         exynos4_default_sdhci0();
 398         exynos4_default_sdhci1();
 399         exynos4_default_sdhci2();
 400         exynos4_default_sdhci3();
 401
 402         s3c_adc_setname("samsung-adc-v3");
 403
 404         s3c_fimc_setname(0, "exynos4-fimc");
 405         s3c_fimc_setname(1, "exynos4-fimc");
 406         s3c_fimc_setname(2, "exynos4-fimc");
 407         s3c_fimc_setname(3, "exynos4-fimc");
 408
 409         s3c_sdhci_setname(0, "exynos4-sdhci");
 410         s3c_sdhci_setname(1, "exynos4-sdhci");
 411         s3c_sdhci_setname(2, "exynos4-sdhci");
 412         s3c_sdhci_setname(3, "exynos4-sdhci");
 413
 414         /* The I2C bus controllers are directly compatible with s3c2440 */
 415         s3c_i2c0_setname("s3c2440-i2c");
 416         s3c_i2c1_setname("s3c2440-i2c");
 417         s3c_i2c2_setname("s3c2440-i2c");
 418
 419         s5p_fb_setname(0, "exynos4-fb");
 420         s5p_hdmi_setname("exynos4-hdmi");
 421
 422         s3c64xx_spi_setname("exynos4210-spi");
 423 }
 424
 425 static void __init exynos5_map_io(void)
 426 {
 427         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 428
 429         if (soc_is_exynos5250())
 430                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 431 }
 432
 433 static void __init exynos5440_map_io(void)
 434 {
 435         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 436 }
 437
 438 void __init exynos_init_time(void)
 439 {
 440         if (of_have_populated_dt()) {
 441 #ifdef CONFIG_OF
 442                 of_clk_init(NULL);
 443                 clocksource_of_init();
 444 #endif
 445         } else {
 446                 /* todo: remove after migrating legacy E4 platforms to dt */
 447 #ifdef CONFIG_ARCH_EXYNOS4
 448                 exynos4_clk_init(NULL);
 449                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 450 #endif
 451                 mct_init();
 452         }
 453 }
 454
 455 void __init exynos4_init_irq(void)
 456 {
 457         unsigned int gic_bank_offset;
 458
 459         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 460
 461         if (!of_have_populated_dt())
 462                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 463 #ifdef CONFIG_OF
 464         else
 465                 irqchip_init();
 466 #endif
 467
 468         if (!of_have_populated_dt())
 469                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 470
 471         /*
 472          * The parameters of s5p_init_irq() are for VIC init.
 473          * Theses parameters should be NULL and 0 because EXYNOS4
 474          * uses GIC instead of VIC.
 475          */
 476         s5p_init_irq(NULL, 0);
 477
 478         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 479 }
 480
 481 void __init exynos5_init_irq(void)
 482 {
 483 #ifdef CONFIG_OF
 484         irqchip_init();
 485 #endif
 486         /*
 487          * The parameters of s5p_init_irq() are for VIC init.
 488          * Theses parameters should be NULL and 0 because EXYNOS4
 489          * uses GIC instead of VIC.
 490          */
 491         if (!of_machine_is_compatible("samsung,exynos5440"))
 492                 s5p_init_irq(NULL, 0);
 493
 494         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 495 }
 496
 497 struct bus_type exynos_subsys = {
 498         .name           = "exynos-core",
 499         .dev_name       = "exynos-core",
 500 };
 501
 502 static struct device exynos4_dev = {
 503         .bus    = &exynos_subsys,
 504 };
 505
 506 static int __init exynos_core_init(void)
 507 {
 508         return subsys_system_register(&exynos_subsys, NULL);
 509 }
 510 core_initcall(exynos_core_init);
 511
 512 #ifdef CONFIG_CACHE_L2X0
 513 static int __init exynos4_l2x0_cache_init(void)
 514 {
 515         int ret;
 516
 517         if (soc_is_exynos5250() || soc_is_exynos5440())
 518                 return 0;
 519
 520         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 521         if (!ret) {
 522                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 523                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 524                 return 0;
 525         }
 526
 527         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 528                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 529                 /* TAG, Data Latency Control: 2 cycles */
 530                 l2x0_saved_regs.tag_latency = 0x110;
 531
 532                 if (soc_is_exynos4212() || soc_is_exynos4412())
 533                         l2x0_saved_regs.data_latency = 0x120;
 534                 else
 535                         l2x0_saved_regs.data_latency = 0x110;
 536
 537                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 538                 l2x0_saved_regs.pwr_ctrl =
 539                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 540
 541                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 542
 543                 __raw_writel(l2x0_saved_regs.tag_latency,
 544                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 545                 __raw_writel(l2x0_saved_regs.data_latency,
 546                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 547
 548                 /* L2X0 Prefetch Control */
 549                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 550                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 551
 552                 /* L2X0 Power Control */
 553                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 554                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 555
 556                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 557                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 558         }
 559
 560         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 561         return 0;
 562 }
 563 early_initcall(exynos4_l2x0_cache_init);
 564 #endif
 565
 566 static int __init exynos_init(void)
 567 {
 568         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 569
 570         return device_register(&exynos4_dev);
 571 }
 572
 573 /* uart registration process */
 574
 575 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 576 {
 577         struct s3c2410_uartcfg *tcfg = cfg;
 578         u32 ucnt;
 579
 580         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 581                 tcfg->has_fracval = 1;
 582
 583         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 584 }
 585
 586 static void __iomem *exynos_eint_base;
 587
 588 static DEFINE_SPINLOCK(eint_lock);
 589
 590 static unsigned int eint0_15_data[16];
 591
 592 static inline int exynos4_irq_to_gpio(unsigned int irq)
 593 {
 594         if (irq < IRQ_EINT(0))
 595                 return -EINVAL;
 596
 597         irq -= IRQ_EINT(0);
 598         if (irq < 8)
 599                 return EXYNOS4_GPX0(irq);
 600
 601         irq -= 8;
 602         if (irq < 8)
 603                 return EXYNOS4_GPX1(irq);
 604
 605         irq -= 8;
 606         if (irq < 8)
 607                 return EXYNOS4_GPX2(irq);
 608
 609         irq -= 8;
 610         if (irq < 8)
 611                 return EXYNOS4_GPX3(irq);
 612
 613         return -EINVAL;
 614 }
 615
 616 static inline int exynos5_irq_to_gpio(unsigned int irq)
 617 {
 618         if (irq < IRQ_EINT(0))
 619                 return -EINVAL;
 620
 621         irq -= IRQ_EINT(0);
 622         if (irq < 8)
 623                 return EXYNOS5_GPX0(irq);
 624
 625         irq -= 8;
 626         if (irq < 8)
 627                 return EXYNOS5_GPX1(irq);
 628
 629         irq -= 8;
 630         if (irq < 8)
 631                 return EXYNOS5_GPX2(irq);
 632
 633         irq -= 8;
 634         if (irq < 8)
 635                 return EXYNOS5_GPX3(irq);
 636
 637         return -EINVAL;
 638 }
 639
 640 static unsigned int exynos4_eint0_15_src_int[16] = {
 641         EXYNOS4_IRQ_EINT0,
 642         EXYNOS4_IRQ_EINT1,
 643         EXYNOS4_IRQ_EINT2,
 644         EXYNOS4_IRQ_EINT3,
 645         EXYNOS4_IRQ_EINT4,
 646         EXYNOS4_IRQ_EINT5,
 647         EXYNOS4_IRQ_EINT6,
 648         EXYNOS4_IRQ_EINT7,
 649         EXYNOS4_IRQ_EINT8,
 650         EXYNOS4_IRQ_EINT9,
 651         EXYNOS4_IRQ_EINT10,
 652         EXYNOS4_IRQ_EINT11,
 653         EXYNOS4_IRQ_EINT12,
 654         EXYNOS4_IRQ_EINT13,
 655         EXYNOS4_IRQ_EINT14,
 656         EXYNOS4_IRQ_EINT15,
 657 };
 658
 659 static unsigned int exynos5_eint0_15_src_int[16] = {
 660         EXYNOS5_IRQ_EINT0,
 661         EXYNOS5_IRQ_EINT1,
 662         EXYNOS5_IRQ_EINT2,
 663         EXYNOS5_IRQ_EINT3,
 664         EXYNOS5_IRQ_EINT4,
 665         EXYNOS5_IRQ_EINT5,
 666         EXYNOS5_IRQ_EINT6,
 667         EXYNOS5_IRQ_EINT7,
 668         EXYNOS5_IRQ_EINT8,
 669         EXYNOS5_IRQ_EINT9,
 670         EXYNOS5_IRQ_EINT10,
 671         EXYNOS5_IRQ_EINT11,
 672         EXYNOS5_IRQ_EINT12,
 673         EXYNOS5_IRQ_EINT13,
 674         EXYNOS5_IRQ_EINT14,
 675         EXYNOS5_IRQ_EINT15,
 676 };
 677 static inline void exynos_irq_eint_mask(struct irq_data *data)
 678 {
 679         u32 mask;
 680
 681         spin_lock(&eint_lock);
 682         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 683         mask |= EINT_OFFSET_BIT(data->irq);
 684         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 685         spin_unlock(&eint_lock);
 686 }
 687
 688 static void exynos_irq_eint_unmask(struct irq_data *data)
 689 {
 690         u32 mask;
 691
 692         spin_lock(&eint_lock);
 693         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 694         mask &= ~(EINT_OFFSET_BIT(data->irq));
 695         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 696         spin_unlock(&eint_lock);
 697 }
 698
 699 static inline void exynos_irq_eint_ack(struct irq_data *data)
 700 {
 701         __raw_writel(EINT_OFFSET_BIT(data->irq),
 702                      EINT_PEND(exynos_eint_base, data->irq));
 703 }
 704
 705 static void exynos_irq_eint_maskack(struct irq_data *data)
 706 {
 707         exynos_irq_eint_mask(data);
 708         exynos_irq_eint_ack(data);
 709 }
 710
 711 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 712 {
 713         int offs = EINT_OFFSET(data->irq);
 714         int shift;
 715         u32 ctrl, mask;
 716         u32 newvalue = 0;
 717
 718         switch (type) {
 719         case IRQ_TYPE_EDGE_RISING:
 720                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 721                 break;
 722
 723         case IRQ_TYPE_EDGE_FALLING:
 724                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 725                 break;
 726
 727         case IRQ_TYPE_EDGE_BOTH:
 728                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 729                 break;
 730
 731         case IRQ_TYPE_LEVEL_LOW:
 732                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 733                 break;
 734
 735         case IRQ_TYPE_LEVEL_HIGH:
 736                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 737                 break;
 738
 739         default:
 740                 printk(KERN_ERR "No such irq type %d", type);
 741                 return -EINVAL;
 742         }
 743
 744         shift = (offs & 0x7) * 4;
 745         mask = 0x7 << shift;
 746
 747         spin_lock(&eint_lock);
 748         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 749         ctrl &= ~mask;
 750         ctrl |= newvalue << shift;
 751         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 752         spin_unlock(&eint_lock);
 753
 754         if (soc_is_exynos5250())
 755                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 756         else
 757                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 758
 759         return 0;
 760 }
 761
 762 static struct irq_chip exynos_irq_eint = {
 763         .name           = "exynos-eint",
 764         .irq_mask       = exynos_irq_eint_mask,
 765         .irq_unmask     = exynos_irq_eint_unmask,
 766         .irq_mask_ack   = exynos_irq_eint_maskack,
 767         .irq_ack        = exynos_irq_eint_ack,
 768         .irq_set_type   = exynos_irq_eint_set_type,
 769 #ifdef CONFIG_PM
 770         .irq_set_wake   = s3c_irqext_wake,
 771 #endif
 772 };
 773
 774 /*
 775  * exynos4_irq_demux_eint
 776  *
 777  * This function demuxes the IRQ from from EINTs 16 to 31.
 778  * It is designed to be inlined into the specific handler
 779  * s5p_irq_demux_eintX_Y.
 780  *
 781  * Each EINT pend/mask registers handle eight of them.
 782  */
 783 static inline void exynos_irq_demux_eint(unsigned int start)
 784 {
 785         unsigned int irq;
 786
 787         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 788         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 789
 790         status &= ~mask;
 791         status &= 0xff;
 792
 793         while (status) {
 794                 irq = fls(status) - 1;
 795                 generic_handle_irq(irq + start);
 796                 status &= ~(1 << irq);
 797         }
 798 }
 799
 800 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 801 {
 802         struct irq_chip *chip = irq_get_chip(irq);
 803         chained_irq_enter(chip, desc);
 804         exynos_irq_demux_eint(IRQ_EINT(16));
 805         exynos_irq_demux_eint(IRQ_EINT(24));
 806         chained_irq_exit(chip, desc);
 807 }
 808
 809 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 810 {
 811         u32 *irq_data = irq_get_handler_data(irq);
 812         struct irq_chip *chip = irq_get_chip(irq);
 813
 814         chained_irq_enter(chip, desc);
 815         generic_handle_irq(*irq_data);
 816         chained_irq_exit(chip, desc);
 817 }
 818
 819 static int __init exynos_init_irq_eint(void)
 820 {
 821         int irq;
 822
 823 #ifdef CONFIG_PINCTRL_SAMSUNG
 824         /*
 825          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 826          * functionality along with support for external gpio and wakeup
 827          * interrupts. If the samsung pinctrl driver is enabled and includes
 828          * the wakeup interrupt support, then the setting up external wakeup
 829          * interrupts here can be skipped. This check here is temporary to
 830          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 831          * co-exist with platforms that do. When all of the Samsung Exynos4
 832          * platforms switch over to using the pinctrl driver, the wakeup
 833          * interrupt support code here can be completely removed.
 834          */
 835         static const struct of_device_id exynos_pinctrl_ids[] = {
 836                 { .compatible = "samsung,exynos4210-pinctrl", },
 837                 { .compatible = "samsung,exynos4x12-pinctrl", },
 838                 { .compatible = "samsung,exynos5250-pinctrl", },
 839         };
 840         struct device_node *pctrl_np, *wkup_np;
 841         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 842
 843         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 844                 if (of_device_is_available(pctrl_np)) {
 845                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 846                                                         wkup_compat);
 847                         if (wkup_np)
 848                                 return -ENODEV;
 849                 }
 850         }
 851 #endif
 852         if (soc_is_exynos5440())
 853                 return 0;
 854
 855         if (soc_is_exynos5250())
 856                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 857         else
 858                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 859
 860         if (exynos_eint_base == NULL) {
 861                 pr_err("unable to ioremap for EINT base address\n");
 862                 return -ENOMEM;
 863         }
 864
 865         for (irq = 0 ; irq <= 31 ; irq++) {
 866                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 867                                          handle_level_irq);
 868                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 869         }
 870
 871         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 872
 873         for (irq = 0 ; irq <= 15 ; irq++) {
 874                 eint0_15_data[irq] = IRQ_EINT(irq);
 875
 876                 if (soc_is_exynos5250()) {
 877                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 878                                              &eint0_15_data[irq]);
 879                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 880                                                 exynos_irq_eint0_15);
 881                 } else {
 882                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 883                                              &eint0_15_data[irq]);
 884                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 885                                                 exynos_irq_eint0_15);
 886                 }
 887         }
 888
 889         return 0;
 890 }
 891 arch_initcall(exynos_init_irq_eint);
 892
 893 static struct resource exynos4_pmu_resource[] = {
 894         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
 895         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
 896 #if defined(CONFIG_SOC_EXYNOS4412)
 897         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
 898         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
 899 #endif
 900 };
 901
 902 static struct platform_device exynos4_device_pmu = {
 903         .name           = "arm-pmu",
 904         .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
 905         .resource       = exynos4_pmu_resource,
 906 };
 907
 908 static int __init exynos_armpmu_init(void)
 909 {
 910         if (!of_have_populated_dt()) {
 911                 if (soc_is_exynos4210() || soc_is_exynos4212())
 912                         exynos4_device_pmu.num_resources = 2;
 913                 platform_device_register(&exynos4_device_pmu);
 914         }
 915
 916         return 0;
 917 }
 918 arch_initcall(exynos_armpmu_init);