arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/platform_data/dwc3-exynos.h>
  16 #include <linux/regulator/fixed.h>
  17 #include <linux/regulator/machine.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/smsc911x.h>
  20 #include <linux/delay.h>
  21 #include <linux/i2c.h>
  22 #include <linux/pwm_backlight.h>
  23 #include <linux/mfd/wm8994/pdata.h>
  24 #include <linux/regulator/machine.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/memblock.h>
  27 #include <linux/of_fdt.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/hardware/gic.h>
  31 #include <mach/map.h>
  32 #include <mach/ohci.h>
  33 #include <mach/regs-pmu.h>
  34 #include <mach/sysmmu.h>
  35 #include <mach/ohci.h>
  36 #include <mach/regs-audss.h>
  37 #include <mach/regs-pmu.h>
  38
  39 #include <plat/audio.h>
  40 #include <plat/cpu.h>
  41 #include <plat/dsim.h>
  42 #include <plat/fb.h>
  43 #include <plat/mipi_dsi.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/regs-fb.h>
  46 #include <plat/regs-serial.h>
  47 #include <plat/regs-srom.h>
  48 #include <plat/backlight.h>
  49 #include <plat/devs.h>
  50 #include <plat/usb-phy.h>
  51 #include <plat/ehci.h>
  52 #include <plat/dp.h>
  53 #include <plat/s3c64xx-spi.h>
  54
  55 #include <video/platform_lcd.h>
  56
  57 #include "drm/exynos_drm.h"
  58 #include "common.h"
  59
  60 static void __init smsc911x_init(int ncs)
  61 {
  62         u32 data;
  63
  64         /* configure nCS1 width to 16 bits */
  65         data = __raw_readl(S5P_SROM_BW) &
  66                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  67         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  68                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  69                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  70         __raw_writel(data, S5P_SROM_BW);
  71
  72         /* set timing for nCS1 suitable for ethernet chip */
  73         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  74                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  75                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  76                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  77                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  78                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  79                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  80                 S5P_SROM_BC0 + (ncs * 4));
  81 }
  82
  83 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  84         .win_mode = {
  85                 .left_margin    = 4,
  86                 .right_margin   = 4,
  87                 .upper_margin   = 4,
  88                 .lower_margin   = 4,
  89                 .hsync_len      = 4,
  90                 .vsync_len      = 4,
  91                 .xres           = 1280,
  92                 .yres           = 800,
  93         },
  94         .virtual_x              = 1280,
  95         .virtual_y              = 800 * 2,
  96         .width                  = 223,
  97         .height                 = 125,
  98         .max_bpp                = 32,
  99         .default_bpp            = 24,
 100 };
 101
 102 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
 103         .win_mode = {
 104                 .left_margin    = 4,
 105                 .right_margin   = 4,
 106                 .upper_margin   = 4,
 107                 .lower_margin   = 4,
 108                 .hsync_len      = 4,
 109                 .vsync_len      = 4,
 110                 .xres           = 1280,
 111                 .yres           = 800,
 112         },
 113         .virtual_x              = 1280,
 114         .virtual_y              = 800 * 2,
 115         .width                  = 223,
 116         .height                 = 125,
 117         .max_bpp                = 32,
 118         .default_bpp            = 24,
 119 };
 120
 121 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 122         .win_mode = {
 123                 .left_margin    = 0x4,
 124                 .right_margin   = 0x4,
 125                 .upper_margin   = 4,
 126                 .lower_margin   = 4,
 127                 .hsync_len      = 4,
 128                 .vsync_len      = 4,
 129                 .xres           = 1280,
 130                 .yres           = 800,
 131         },
 132         .virtual_x              = 1280,
 133         .virtual_y              = 800 * 2,
 134         .width                  = 223,
 135         .height                 = 125,
 136         .max_bpp                = 32,
 137         .default_bpp            = 24,
 138 };
 139
 140 static struct fb_videomode snow_fb_window[] = {
 141         [0] = { /* Only LCD Connected */
 142                 .left_margin    = 40,
 143                 .right_margin   = 40,
 144                 .upper_margin   = 10,
 145                 .lower_margin   = 10,
 146                 .hsync_len      = 32,
 147                 .vsync_len      = 5,
 148                 .xres           = 1366,
 149                 .yres           = 768,
 150         },
 151         [1] = { /* TV & LCD Connected */
 152                 .left_margin    = 83,
 153                 .right_margin   = 83,
 154                 .upper_margin   = 34,
 155                 .lower_margin   = 34,
 156                 .hsync_len      = 32,
 157                 .vsync_len      = 5,
 158                 .xres           = 1280,
 159                 .yres           = 720,
 160         },
 161         [2] = {
 162                 .xres           = -1,
 163                 .yres           = -1,
 164         },
 165 };
 166
 167 static void exynos_fimd_gpio_setup_24bpp(void)
 168 {
 169         unsigned int reg = 0;
 170
 171         /*
 172          * Set DISP1BLK_CFG register for Display path selection
 173          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 174          * ---------------------
 175          * 0 | MIE/MDNIE
 176          * 1 | FIMD : selected
 177          */
 178         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 179         reg &= ~(1 << 15);      /* To save other reset values */
 180         reg |= (1 << 15);
 181         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 182 }
 183
 184 static void exynos_dp_gpio_setup_24bpp(void)
 185 {
 186         exynos_fimd_gpio_setup_24bpp();
 187
 188         /* Set Hotplug detect for DP */
 189         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 190         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 191 }
 192
 193 #ifdef CONFIG_DRM_EXYNOS_HDMI
 194 static struct platform_device exynos_drm_hdmi_device = {
 195         .name           = "exynos-drm-hdmi",
 196 };
 197
 198 static struct exynos_drm_hdmi_pdata drm_mixer_pdata = {
 199         .timing = {
 200                 .xres    = 1920,
 201                 .yres    = 1080,
 202                 .refresh = 60,
 203         },
 204         .default_win    = 0,
 205         .bpp            = 32,
 206         .is_v13         = 0,
 207         .is_soc_exynos5 = 1,
 208 };
 209
 210 static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = {
 211         .timing = {
 212                 .xres    = 1920,
 213                 .yres    = 1080,
 214                 .refresh    = 60,
 215         },
 216         .default_win    = 0,
 217         .bpp            = 32,
 218         .is_v13         = 0,
 219         .is_soc_exynos5 = 1,
 220 };
 221 #endif
 222
 223 #ifdef CONFIG_DRM_EXYNOS_FIMD
 224 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 225         .panel[0].timing   = {
 226                 .xres           = 1280,
 227                 .yres           = 800,
 228                 .hsync_len      = 4,
 229                 .left_margin    = 0x4,
 230                 .right_margin   = 0x4,
 231                 .vsync_len      = 4,
 232                 .upper_margin   = 4,
 233                 .lower_margin   = 4,
 234                 .refresh        = 60,
 235         },
 236         .panel[1].timing   = {
 237                 .xres           = 1280,
 238                 .yres           = 720,
 239                 .hsync_len      = 4,
 240                 .left_margin    = 0x4,
 241                 .right_margin   = 0x4,
 242                 .vsync_len      = 4,
 243                 .upper_margin   = 4,
 244                 .lower_margin   = 4,
 245                 .refresh        = 60,
 246         },
 247         .panel[2].timing   = {
 248                 .xres           = -1,
 249                 .yres           = -1,
 250         },
 251         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 252         .vidcon1        = VIDCON1_INV_VCLK,
 253         .default_win    = 0,
 254         .bpp            = 32,
 255         .clock_rate     = 800 * 1000 * 1000,
 256 };
 257 #else
 258 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 259         .win[0]         = &smdk5250_fb_win0,
 260         .win[1]         = &smdk5250_fb_win1,
 261         .win[2]         = &smdk5250_fb_win2,
 262         .default_win    = 0,
 263         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 264         .vidcon1        = VIDCON1_INV_VCLK,
 265         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 266         .clock_rate     = 800 * 1000 * 1000,
 267 };
 268 #endif
 269
 270 static struct mipi_dsim_config dsim_info = {
 271         .e_interface            = DSIM_VIDEO,
 272         .e_pixel_format         = DSIM_24BPP_888,
 273         /* main frame fifo auto flush at VSYNC pulse */
 274         .auto_flush             = false,
 275         .eot_disable            = false,
 276         .auto_vertical_cnt      = false,
 277         .hse                    = false,
 278         .hfp                    = false,
 279         .hbp                    = false,
 280         .hsa                    = false,
 281
 282         .e_no_data_lane         = DSIM_DATA_LANE_4,
 283         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 284         .e_burst_mode           = DSIM_BURST,
 285
 286         .p                      = 3,
 287         .m                      = 115,
 288         .s                      = 1,
 289
 290         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 291         .pll_stable_time        = 500,
 292
 293         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 294
 295         /* stop state holding counter after bta change count 0 ~ 0xfff */
 296         .stop_holding_cnt       = 0x0f,
 297         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 298         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 299
 300         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 301 };
 302
 303 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 304         .rgb_timing.left_margin         = 0x4,
 305         .rgb_timing.right_margin        = 0x4,
 306         .rgb_timing.upper_margin        = 0x4,
 307         .rgb_timing.lower_margin        =  0x4,
 308         .rgb_timing.hsync_len           = 0x4,
 309         .rgb_timing.vsync_len           = 0x4,
 310         .cpu_timing.cs_setup            = 0,
 311         .cpu_timing.wr_setup            = 1,
 312         .cpu_timing.wr_act              = 0,
 313         .cpu_timing.wr_hold             = 0,
 314         .lcd_size.width                 = 1280,
 315         .lcd_size.height                = 800,
 316 };
 317
 318 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 319         .clk_name               = "dsim0",
 320         .dsim_config            = &dsim_info,
 321         .dsim_lcd_config        = &dsim_lcd_info,
 322
 323         .part_reset             = s5p_dsim_part_reset,
 324         .init_d_phy             = s5p_dsim_init_d_phy,
 325         .get_fb_frame_done      = NULL,
 326         .trigger                = NULL,
 327
 328         /*
 329          * the stable time of needing to write data on SFR
 330          * when the mipi mode becomes LP mode.
 331          */
 332         .delay_for_stabilization = 600,
 333 };
 334
 335 static struct platform_device exynos_drm_device = {
 336         .name           = "exynos-drm",
 337         .dev = {
 338                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 339                 .coherent_dma_mask = 0xffffffffUL,
 340         }
 341 };
 342
 343 static void lcd_set_power(struct plat_lcd_data *pd,
 344                         unsigned int power)
 345 {
 346         if (of_machine_is_compatible("google,daisy") ||
 347                         of_machine_is_compatible("google,snow")) {
 348                 struct regulator *lcd_fet;
 349
 350                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 351                 if (!IS_ERR(lcd_fet)) {
 352                         if (power)
 353                                 regulator_enable(lcd_fet);
 354                         else
 355                                 regulator_disable(lcd_fet);
 356
 357                         regulator_put(lcd_fet);
 358                 }
 359         }
 360
 361         if (!of_machine_is_compatible("google,snow")) {
 362                 /* reset */
 363                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 364                 mdelay(20);
 365                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 366                 mdelay(20);
 367                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 368                 mdelay(20);
 369                 gpio_free(EXYNOS5_GPX1(5));
 370                 mdelay(20);
 371         }
 372
 373
 374         /* Turn on regulator for backlight */
 375         if (of_machine_is_compatible("google,daisy") ||
 376                         of_machine_is_compatible("google,snow")) {
 377                 struct regulator *backlight_fet;
 378
 379                 backlight_fet = regulator_get(NULL, "vcd_led");
 380                 if (!IS_ERR(backlight_fet)) {
 381                         if (power)
 382                                 regulator_enable(backlight_fet);
 383                         else
 384                                 regulator_disable(backlight_fet);
 385
 386                         regulator_put(backlight_fet);
 387                 }
 388                 /* Wait 10 ms between regulator on and PWM start per spec */
 389                 mdelay(10);
 390         }
 391 }
 392
 393 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 394 {
 395         /* Don't call .set_power callback while unblanking */
 396         return 0;
 397 }
 398
 399 static struct plat_lcd_data smdk5250_lcd_data = {
 400         .set_power      = lcd_set_power,
 401         .match_fb       = smdk5250_match_fb,
 402 };
 403
 404 static struct platform_device smdk5250_lcd = {
 405         .name                   = "platform-lcd",
 406         .dev.platform_data      = &smdk5250_lcd_data,
 407 };
 408
 409 static int smdk5250_bl_notify(struct device *unused, int brightness)
 410 {
 411         /* manage lcd_bl_en signal */
 412         if (brightness)
 413                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 414         else
 415                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 416
 417         return brightness;
 418 }
 419
 420 /* LCD Backlight data */
 421 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 422         .no     = EXYNOS5_GPB2(0),
 423         .func   = S3C_GPIO_SFN(2),
 424 };
 425
 426 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 427         .pwm_period_ns  = 1000000,
 428         .notify         = smdk5250_bl_notify,
 429 };
 430
 431 struct platform_device exynos_device_md0 = {
 432         .name = "exynos-mdev",
 433         .id = 0,
 434 };
 435
 436 struct platform_device exynos_device_md1 = {
 437         .name = "exynos-mdev",
 438         .id = 1,
 439 };
 440
 441 struct platform_device exynos_device_md2 = {
 442         .name = "exynos-mdev",
 443         .id = 2,
 444 };
 445
 446 static struct regulator_consumer_supply wm8994_avdd1_supply =
 447         REGULATOR_SUPPLY("AVDD1", "1-001a");
 448
 449 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 450         REGULATOR_SUPPLY("DCVDD", "1-001a");
 451
 452 static struct regulator_init_data wm8994_ldo1_data = {
 453         .constraints    = {
 454                 .name           = "AVDD1",
 455         },
 456         .num_consumer_supplies  = 1,
 457         .consumer_supplies      = &wm8994_avdd1_supply,
 458 };
 459
 460 static struct regulator_init_data wm8994_ldo2_data = {
 461         .constraints    = {
 462         .name                   = "DCVDD",
 463                 },
 464         .num_consumer_supplies  = 1,
 465         .consumer_supplies      = &wm8994_dcvdd_supply,
 466 };
 467
 468 static struct wm8994_pdata wm8994_platform_data = {
 469         /* configure gpio1 function: 0x0001(Logic level input/output) */
 470         .gpio_defaults[0] = 0x0001,
 471         /* If the i2s0 and i2s2 is enabled simultaneously */
 472         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 473         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 474         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 475         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 476         .ldo[0] = { 0, &wm8994_ldo1_data },
 477         .ldo[1] = { 0, &wm8994_ldo2_data },
 478 };
 479
 480 static struct i2c_board_info i2c_devs1[] __initdata = {
 481         {
 482                 I2C_BOARD_INFO("wm8994", 0x1a),
 483                 .platform_data  = &wm8994_platform_data,
 484         },
 485 };
 486
 487 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 488         [0] = {
 489                 .line           = EXYNOS5_GPA2(5),
 490                 .fb_delay       = 0x2,
 491         },
 492 };
 493
 494 static struct spi_board_info spi1_board_info[] __initdata = {
 495         {
 496                 .modalias               = "spidev",
 497                 .platform_data          = NULL,
 498                 .max_speed_hz           = 10*1000*1000,
 499                 .bus_num                = 1,
 500                 .chip_select            = 0,
 501                 .mode                   = SPI_MODE_0,
 502                 .controller_data        = spi1_csi,
 503         }
 504 };
 505
 506 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 507         .dbgname = "mfc_l",
 508         .clockname = "sysmmu",
 509 };
 510
 511 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 512         .dbgname = "mfc_r",
 513         .clockname = "sysmmu",
 514 };
 515
 516 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 517         .dbgname = "gsc",
 518         .clockname = "sysmmu",
 519 };
 520
 521 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 522         .dbgname = "g2d",
 523         .clockname = "sysmmu",
 524 };
 525
 526 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 527         .dbgname = "fimd",
 528         .clockname = "sysmmu",
 529 };
 530
 531 struct sysmmu_platform_data platdata_sysmmu_tv = {
 532         .dbgname = "tv",
 533         .clockname = "sysmmu",
 534 };
 535
 536 #ifdef CONFIG_VIDEO_FIMG2D4X
 537 static struct fimg2d_platdata fimg2d_data __initdata = {
 538         .hw_ver         = 0x42,
 539         .gate_clkname   = "fimg2d",
 540 };
 541 #endif
 542
 543 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 544         .phy_init = s5p_usb_phy_init,
 545         .phy_exit = s5p_usb_phy_exit,
 546 };
 547
 548 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 549         .phy_init = s5p_usb_phy_init,
 550         .phy_exit = s5p_usb_phy_exit,
 551 };
 552
 553 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 554         .phy_type = S5P_USB_PHY_DRD,
 555         .phy_init = s5p_usb_phy_init,
 556         .phy_exit = s5p_usb_phy_exit,
 557 };
 558
 559 struct exynos_gpio_cfg {
 560         unsigned int    addr;
 561         unsigned int    num;
 562         unsigned int    bit;
 563 };
 564
 565 static const char *rclksrc[] = {
 566         [0] = "busclk",
 567         [1] = "i2sclk",
 568 };
 569
 570 static struct video_info smdk5250_dp_config = {
 571         .name                   = "eDP-LVDS NXP PTN3460",
 572
 573         .h_sync_polarity        = 0,
 574         .v_sync_polarity        = 0,
 575         .interlaced             = 0,
 576
 577         .color_space            = COLOR_RGB,
 578         .dynamic_range          = VESA,
 579         .ycbcr_coeff            = COLOR_YCBCR601,
 580         .color_depth            = COLOR_8,
 581
 582         .link_rate              = LINK_RATE_2_70GBPS,
 583         .lane_count             = LANE_COUNT2,
 584 };
 585
 586 static struct exynos_dp_platdata smdk5250_dp_data = {
 587         .video_info     = &smdk5250_dp_config,
 588         .training_type  = SW_LINK_TRAINING,
 589         .phy_init       = s5p_dp_phy_init,
 590         .phy_exit       = s5p_dp_phy_exit,
 591 };
 592
 593 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 594 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 595 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 596 /* Mask bit[12:8] for xxti clock selection */
 597 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 598
 599 static void __init enable_xclkout(void)
 600 {
 601        unsigned int tmp;
 602
 603        tmp = readl(S5P_PMU_DEBUG);
 604        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 605        tmp |= PMU_DEBUG_XXTI;
 606        writel(tmp, S5P_PMU_DEBUG);
 607 }
 608
 609 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 610 {
 611         int id;
 612         /* configure GPIO for i2s port */
 613         struct exynos_gpio_cfg exynos5_cfg[3] = {
 614                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 615                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 616                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 617         };
 618
 619         if (pdev->dev.of_node) {
 620                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 621                 if (id < 0)
 622                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 623         } else {
 624                 id = pdev->id;
 625         }
 626
 627         if (id < 0 || id > 2) {
 628                 printk(KERN_ERR "Invalid Device %d\n", id);
 629                 return -EINVAL;
 630         }
 631
 632         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 633                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 634
 635         return 0;
 636 }
 637
 638 static struct s3c_audio_pdata i2sv5_pdata = {
 639         .cfg_gpio = exynos_cfg_i2s_gpio,
 640         .type = {
 641                 .i2s = {
 642                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 643                                          | QUIRK_NEED_RSTCLR,
 644                         .src_clk = rclksrc,
 645                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 646                 },
 647         },
 648 };
 649
 650 /*
 651  * The following lookup table is used to override device names when devices
 652  * are registered from device tree. This is temporarily added to enable
 653  * device tree support addition for the EXYNOS5 architecture.
 654  *
 655  * For drivers that require platform data to be provided from the machine
 656  * file, a platform data pointer can also be supplied along with the
 657  * devices names. Usually, the platform data elements that cannot be parsed
 658  * from the device tree by the drivers (example: function pointers) are
 659  * supplied. But it should be noted that this is a temporary mechanism and
 660  * at some point, the drivers should be capable of parsing all the platform
 661  * data from the device tree.
 662  */
 663 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 664         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 665                                 "exynos4210-uart.0", NULL),
 666         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 667                                 "exynos4210-uart.1", NULL),
 668         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 669                                 "exynos4210-uart.2", NULL),
 670         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 671                                 "exynos4210-uart.3", NULL),
 672         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 673                                 "s3c2440-i2c.0", NULL),
 674         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 675                                 "s3c2440-i2c.1", NULL),
 676         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 677                                 "s3c2440-i2c.2", NULL),
 678         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 679                                 "s3c2440-i2c.3", NULL),
 680         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 681                                 "s3c2440-i2c.4", NULL),
 682         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 683                                 "s3c2440-i2c.5", NULL),
 684         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 685                                 "s3c2440-i2c.6", NULL),
 686         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 687                                 "s3c2440-i2c.7", NULL),
 688         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 689                                 "s3c2440-hdmiphy-i2c", NULL),
 690         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 691                                 "exynos4210-spi.0", NULL),
 692         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 693                                 "exynos4210-spi.1", NULL),
 694         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 695                                 "exynos4210-spi.2", NULL),
 696         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 697                                 "dw_mmc.0", NULL),
 698         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 699                                 "dw_mmc.1", NULL),
 700         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 701                                 "dw_mmc.2", NULL),
 702         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 703                                 "dw_mmc.3", NULL),
 704         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 705         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 706         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 707         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 708                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 709         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 710                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 711         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 712                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 713         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 714                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 715         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 716                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 717         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 718                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 719         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 720                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 721         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 722                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 723         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 724                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 725         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 726                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 727         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 728                                 "s5p-mipi-dsim", &dsim_platform_data),
 729         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 730                                 "s5p-dp", &smdk5250_dp_data),
 731         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 732         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 733                                 "exynos-gsc.0", NULL),
 734         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 735                                 "exynos-gsc.1", NULL),
 736         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 737                                 "exynos-gsc.2", NULL),
 738         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 739                                 "exynos-gsc.3", NULL),
 740 #ifdef CONFIG_VIDEO_FIMG2D4X
 741         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 742                                 "s5p-g2d", &fimg2d_data),
 743 #endif
 744         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 745                                 "exynos-ohci", &smdk5250_ohci_pdata),
 746         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 747                                 "s5p-ehci", &smdk5250_ehci_pdata),
 748         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 749                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 750         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 751                                 "samsung-i2s.0", &i2sv5_pdata),
 752 #ifdef CONFIG_DRM_EXYNOS_HDMI
 753         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 754                                 "exynos5-hdmi", &drm_hdmi_pdata),
 755         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 756                                 "s5p-mixer", &drm_mixer_pdata),
 757 #else
 758         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 759                                 "exynos5-hdmi", NULL),
 760         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 761                                 "s5p-mixer", NULL),
 762 #endif
 763         {},
 764 };
 765
 766 static struct platform_device *smdk5250_devices[] __initdata = {
 767         &smdk5250_lcd, /* for platform_lcd device */
 768         &exynos_device_md0, /* for media device framework */
 769         &exynos_device_md1, /* for media device framework */
 770         &exynos_device_md2, /* for media device framework */
 771         &samsung_asoc_dma,  /* for audio dma interface device */
 772         &exynos_drm_device,
 773 #ifdef CONFIG_DRM_EXYNOS_HDMI
 774         &exynos_drm_hdmi_device,
 775 #endif
 776 };
 777
 778 static struct regulator_consumer_supply dummy_supplies[] = {
 779         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 780         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 781 };
 782
 783 static void __init exynos5250_dt_map_io(void)
 784 {
 785         exynos_init_io(NULL, 0);
 786         s3c24xx_init_clocks(24000000);
 787 }
 788
 789 static unsigned long ramoops_dt_start, ramoops_dt_size;
 790 static int __init init_dt_scan_ramoops(unsigned long node, const char *uname,
 791                                         int depth, void *data)
 792 {
 793         __be32 *reg, *endp;
 794         unsigned long l;
 795
 796         if (!of_flat_dt_is_compatible(node, "ramoops"))
 797                 return 0;
 798
 799         reg = of_get_flat_dt_prop(node, "reg", &l);
 800         if (!reg)
 801                 return 0;
 802         endp = reg + (l / sizeof(__be32));
 803
 804         /* This architecture uses single cells for address and size.
 805          * Other architectures may differ. */
 806         ramoops_dt_start = be32_to_cpu(reg[0]);
 807         ramoops_dt_size = be32_to_cpu(reg[1]);
 808         return 0;
 809 }
 810
 811 static void __init exynos5_ramoops_reserve(void)
 812 {
 813         unsigned long start, size;
 814
 815         of_scan_flat_dt(init_dt_scan_ramoops, NULL);
 816
 817         /* If necessary, lower start and raise size to align to 1M. */
 818         start = round_down(ramoops_dt_start, SZ_1M);
 819         size = ramoops_dt_size + ramoops_dt_start - start;
 820         size = round_up(size, SZ_1M);
 821
 822         if (memblock_remove(start, size)) {
 823                 pr_err("Failed to remove ramoops %08lx@%08lx from memory\n",
 824                         size, start);
 825         } else {
 826                 pr_info("Ramoops: %08lx - %08lx\n", start, start + size - 1);
 827         }
 828 }
 829
 830 static void __init exynos5_reserve(void)
 831 {
 832         /* required to have enough address range to remap the IOMMU
 833          * allocated buffers */
 834         init_consistent_dma_size(SZ_64M);
 835
 836         exynos5_ramoops_reserve();
 837 }
 838
 839 static void s5p_tv_setup(void)
 840 {
 841         /* direct HPD to HDMI chip */
 842         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 843
 844         gpio_direction_input(EXYNOS5_GPX3(7));
 845         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 846         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 847 }
 848
 849 static void exynos5_i2c_setup(void)
 850 {
 851         /* Setup the low-speed i2c controller interrupts */
 852         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 853 }
 854
 855 static void __init exynos5250_dt_machine_init(void)
 856 {
 857         struct device_node *srom_np, *np;
 858         int i;
 859
 860         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 861
 862         /* Setup pins for any SMSC 911x controller on the SROMC bus */
 863         srom_np = of_find_node_by_path("/sromc-bus");
 864         if (!srom_np) {
 865                 printk(KERN_ERR "No /sromc-bus property.\n");
 866                 goto out;
 867         }
 868         for_each_child_of_node(srom_np, np) {
 869                 if (of_device_is_compatible(np, "smsc,lan9115")) {
 870                         u32 reg;
 871                         of_property_read_u32(np, "reg", &reg);
 872                         smsc911x_init(reg);
 873                 }
 874         }
 875
 876         /*
 877          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 878          * TODO: Fix this so we are not at risk of requesting the GPIO
 879          * multiple times, this should be done with device tree, and
 880          * likely integrated into the plat-samsung/dev-backlight.c init.
 881          */
 882         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_HIGH, "lcd_bl_en");
 883
 884         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 885
 886         /*
 887          * HACK ALERT! TODO: FIXME!
 888          *
 889          * We're going to hack in Daisy LCD info here for bringup purposes.
 890          * Lots of things wrong with what we're doing here, but it works for
 891          * bringup purposes.
 892          */
 893
 894         if (of_machine_is_compatible("google,daisy")) {
 895 #ifdef CONFIG_DRM_EXYNOS_FIMD
 896                 smdk5250_lcd1_pdata.panel[0].timing.xres = 1366;
 897                 smdk5250_lcd1_pdata.panel[0].timing.yres = 768;
 898                 smdk5250_lcd1_pdata.panel[1].timing.xres = 1280;
 899                 smdk5250_lcd1_pdata.panel[1].timing.yres = 720;
 900                 smdk5250_lcd1_pdata.panel[2].timing.xres = -1;
 901                 smdk5250_lcd1_pdata.panel[2].timing.yres = -1;
 902                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
 903 #else
 904                 smdk5250_fb_win0.win_mode.xres = 1366;
 905                 smdk5250_fb_win0.win_mode.yres = 768;
 906                 smdk5250_fb_win0.virtual_x = 1366;
 907                 smdk5250_fb_win0.virtual_y = 768 * 2;
 908
 909                 smdk5250_fb_win1.win_mode.xres = 1366;
 910                 smdk5250_fb_win1.win_mode.yres = 768;
 911                 smdk5250_fb_win1.virtual_x = 1366;
 912                 smdk5250_fb_win1.virtual_y = 768 * 2;
 913
 914                 smdk5250_fb_win2.win_mode.xres = 1366;
 915                 smdk5250_fb_win2.win_mode.yres = 768;
 916                 smdk5250_fb_win2.virtual_x = 1366;
 917                 smdk5250_fb_win2.virtual_y = 768 * 2;
 918 #endif
 919                 dsim_lcd_info.lcd_size.width = 1366;
 920                 dsim_lcd_info.lcd_size.height = 768;
 921         } else if (of_machine_is_compatible("google,snow")) {
 922 #ifdef CONFIG_DRM_EXYNOS_FIMD
 923                 for (i = 0;i < ARRAY_SIZE(snow_fb_window);i++)
 924                         smdk5250_lcd1_pdata.panel[i].timing = snow_fb_window[i];
 925
 926                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
 927                 smdk5250_lcd1_pdata.clock_rate = 70250000;
 928                 smdk5250_lcd1_pdata.vidcon1 = 0;
 929 #endif
 930         }
 931
 932         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 933                 "HOST_VBUS_CONTROL")) {
 934                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 935         } else {
 936                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 937                 gpio_free(EXYNOS5_GPX2(6));
 938         }
 939
 940         exynos5_i2c_setup();
 941
 942         /*
 943          * MAX77686 PMIC interrupt setup code
 944          * TODO: Convert the device tree wakeup_int domain to support
 945          * pull-up flags
 946          */
 947         s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_NONE);
 948
 949         /*
 950          * BIG HACK: The wm8994 is not device tree enabled apparently, so
 951          * needs to be added manually.  ...but it's only on SMDK5250.
 952          */
 953         if (of_machine_is_compatible("samsung,smdk5250")) {
 954                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 955         }
 956
 957         /* XCLKOUT needs to be moved over to the clock interface, but enable it
 958          * here for now.
 959          */
 960         enable_xclkout();
 961
 962         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
 963                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
 964         } else {
 965                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
 966                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
 967                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
 968                 spi_register_board_info(spi1_board_info,
 969                                         ARRAY_SIZE(spi1_board_info));
 970         }
 971
 972         of_platform_populate(NULL, of_default_bus_match_table,
 973                                 exynos5250_auxdata_lookup, NULL);
 974
 975 #ifdef CONFIG_DRM_EXYNOS_FIMD
 976         if (of_machine_is_compatible("google,snow"))
 977                 exynos_dp_gpio_setup_24bpp();
 978         else
 979                 exynos_fimd_gpio_setup_24bpp();
 980 #endif
 981         s5p_tv_setup();
 982
 983         /* Enable power to ADC */
 984         __raw_writel(0x1, S5P_ADC_PHY_CONTROL);
 985
 986         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 987 out:
 988         of_node_put(srom_np);
 989         return;
 990 }
 991
 992 static char const *exynos5250_dt_compat[] __initdata = {
 993         "samsung,exynos5250",
 994         NULL
 995 };
 996
 997 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 998         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 999         .init_irq       = exynos5_init_irq,
1000         .reserve        = exynos5_reserve,
1001         .map_io         = exynos5250_dt_map_io,
1002         .handle_irq     = gic_handle_irq,
1003         .init_machine   = exynos5250_dt_machine_init,
1004         .timer          = &exynos4_timer,
1005         .dt_compat      = exynos5250_dt_compat,
1006         .restart        = exynos5_restart,
1007 MACHINE_END