arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dwc3-exynos.h>
  15 #include <linux/regulator/fixed.h>
  16 #include <linux/regulator/machine.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/smsc911x.h>
  19 #include <linux/delay.h>
  20 #include <linux/i2c.h>
  21 #include <linux/pwm_backlight.h>
  22 #include <linux/mfd/wm8994/pdata.h>
  23 #include <linux/regulator/machine.h>
  24
  25 #include <asm/mach/arch.h>
  26 #include <asm/hardware/gic.h>
  27 #include <mach/map.h>
  28 #include <mach/ohci.h>
  29 #include <mach/regs-pmu.h>
  30 #include <mach/sysmmu.h>
  31 #include <mach/ohci.h>
  32 #include <mach/regs-audss.h>
  33
  34 #include <plat/audio.h>
  35 #include <plat/cpu.h>
  36 #include <plat/dsim.h>
  37 #include <plat/fb.h>
  38 #include <plat/mipi_dsi.h>
  39 #include <plat/gpio-cfg.h>
  40 #include <plat/regs-fb.h>
  41 #include <plat/regs-serial.h>
  42 #include <plat/regs-srom.h>
  43 #include <plat/backlight.h>
  44 #include <plat/devs.h>
  45 #include <plat/usb-phy.h>
  46 #include <plat/ehci.h>
  47 #include <plat/dp.h>
  48
  49 #include <video/platform_lcd.h>
  50
  51 #include "drm/exynos_drm.h"
  52 #include "common.h"
  53
  54 static void __init smsc911x_init(int ncs)
  55 {
  56         u32 data;
  57
  58         /* configure nCS1 width to 16 bits */
  59         data = __raw_readl(S5P_SROM_BW) &
  60                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  61         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  62                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  63                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  64         __raw_writel(data, S5P_SROM_BW);
  65
  66         /* set timing for nCS1 suitable for ethernet chip */
  67         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  68                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  69                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  70                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  71                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  72                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  73                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  74                 S5P_SROM_BC0 + (ncs * 4));
  75 }
  76
  77 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  78         .win_mode = {
  79                 .left_margin    = 4,
  80                 .right_margin   = 4,
  81                 .upper_margin   = 4,
  82                 .lower_margin   = 4,
  83                 .hsync_len      = 4,
  84                 .vsync_len      = 4,
  85                 .xres           = 1280,
  86                 .yres           = 800,
  87         },
  88         .virtual_x              = 1280,
  89         .virtual_y              = 800 * 2,
  90         .width                  = 223,
  91         .height                 = 125,
  92         .max_bpp                = 32,
  93         .default_bpp            = 24,
  94 };
  95
  96 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
  97         .win_mode = {
  98                 .left_margin    = 4,
  99                 .right_margin   = 4,
 100                 .upper_margin   = 4,
 101                 .lower_margin   = 4,
 102                 .hsync_len      = 4,
 103                 .vsync_len      = 4,
 104                 .xres           = 1280,
 105                 .yres           = 800,
 106         },
 107         .virtual_x              = 1280,
 108         .virtual_y              = 800 * 2,
 109         .width                  = 223,
 110         .height                 = 125,
 111         .max_bpp                = 32,
 112         .default_bpp            = 24,
 113 };
 114
 115 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 116         .win_mode = {
 117                 .left_margin    = 0x4,
 118                 .right_margin   = 0x4,
 119                 .upper_margin   = 4,
 120                 .lower_margin   = 4,
 121                 .hsync_len      = 4,
 122                 .vsync_len      = 4,
 123                 .xres           = 1280,
 124                 .yres           = 800,
 125         },
 126         .virtual_x              = 1280,
 127         .virtual_y              = 800 * 2,
 128         .width                  = 223,
 129         .height                 = 125,
 130         .max_bpp                = 32,
 131         .default_bpp            = 24,
 132 };
 133
 134 static struct fb_videomode snow_fb_window = {
 135         .left_margin    = 0x80,
 136         .right_margin   = 0x48,
 137         .upper_margin   = 14,
 138         .lower_margin   = 3,
 139         .hsync_len      = 5,
 140         .vsync_len      = 32,
 141         .xres           = 1366,
 142         .yres           = 768,
 143 };
 144
 145 static void exynos_fimd_gpio_setup_24bpp(void)
 146 {
 147         unsigned int reg = 0;
 148
 149         /*
 150          * Set DISP1BLK_CFG register for Display path selection
 151          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 152          * ---------------------
 153          * 0 | MIE/MDNIE
 154          * 1 | FIMD : selected
 155          */
 156         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 157         reg &= ~(1 << 15);      /* To save other reset values */
 158         reg |= (1 << 15);
 159         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 160 }
 161
 162 static void exynos_dp_gpio_setup_24bpp(void)
 163 {
 164         exynos_fimd_gpio_setup_24bpp();
 165
 166         /* Set Hotplug detect for DP */
 167         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 168         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 169 }
 170
 171 #ifdef CONFIG_DRM_EXYNOS_FIMD
 172 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 173         .panel.timing   = {
 174                 .xres           = 1280,
 175                 .yres           = 800,
 176                 .hsync_len      = 4,
 177                 .left_margin    = 0x4,
 178                 .right_margin   = 0x4,
 179                 .vsync_len      = 4,
 180                 .upper_margin   = 4,
 181                 .lower_margin   = 4,
 182                 .refresh        = 60,
 183         },
 184         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 185         .vidcon1        = VIDCON1_INV_VCLK,
 186         .default_win    = 0,
 187         .bpp            = 32,
 188         .clock_rate     = 800 * 1000 * 1000,
 189 };
 190 #else
 191 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 192         .win[0]         = &smdk5250_fb_win0,
 193         .win[1]         = &smdk5250_fb_win1,
 194         .win[2]         = &smdk5250_fb_win2,
 195         .default_win    = 0,
 196         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 197         .vidcon1        = VIDCON1_INV_VCLK,
 198         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 199 };
 200 #endif
 201
 202 static struct mipi_dsim_config dsim_info = {
 203         .e_interface            = DSIM_VIDEO,
 204         .e_pixel_format         = DSIM_24BPP_888,
 205         /* main frame fifo auto flush at VSYNC pulse */
 206         .auto_flush             = false,
 207         .eot_disable            = false,
 208         .auto_vertical_cnt      = false,
 209         .hse                    = false,
 210         .hfp                    = false,
 211         .hbp                    = false,
 212         .hsa                    = false,
 213
 214         .e_no_data_lane         = DSIM_DATA_LANE_4,
 215         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 216         .e_burst_mode           = DSIM_BURST,
 217
 218         .p                      = 3,
 219         .m                      = 115,
 220         .s                      = 1,
 221
 222         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 223         .pll_stable_time        = 500,
 224
 225         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 226
 227         /* stop state holding counter after bta change count 0 ~ 0xfff */
 228         .stop_holding_cnt       = 0x0f,
 229         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 230         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 231
 232         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 233 };
 234
 235 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 236         .rgb_timing.left_margin         = 0x4,
 237         .rgb_timing.right_margin        = 0x4,
 238         .rgb_timing.upper_margin        = 0x4,
 239         .rgb_timing.lower_margin        =  0x4,
 240         .rgb_timing.hsync_len           = 0x4,
 241         .rgb_timing.vsync_len           = 0x4,
 242         .cpu_timing.cs_setup            = 0,
 243         .cpu_timing.wr_setup            = 1,
 244         .cpu_timing.wr_act              = 0,
 245         .cpu_timing.wr_hold             = 0,
 246         .lcd_size.width                 = 1280,
 247         .lcd_size.height                = 800,
 248 };
 249
 250 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 251         .clk_name               = "dsim0",
 252         .dsim_config            = &dsim_info,
 253         .dsim_lcd_config        = &dsim_lcd_info,
 254
 255         .part_reset             = s5p_dsim_part_reset,
 256         .init_d_phy             = s5p_dsim_init_d_phy,
 257         .get_fb_frame_done      = NULL,
 258         .trigger                = NULL,
 259
 260         /*
 261          * the stable time of needing to write data on SFR
 262          * when the mipi mode becomes LP mode.
 263          */
 264         .delay_for_stabilization = 600,
 265 };
 266
 267 static struct platform_device exynos_drm_device = {
 268         .name           = "exynos-drm",
 269         .dev = {
 270                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 271                 .coherent_dma_mask = 0xffffffffUL,
 272         }
 273 };
 274
 275 static void lcd_set_power(struct plat_lcd_data *pd,
 276                         unsigned int power)
 277 {
 278         /* reset */
 279         gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 280
 281         mdelay(20);
 282         if (power) {
 283                 /* fire nRESET on power up */
 284                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 285                 mdelay(20);
 286                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 287                 mdelay(20);
 288                 gpio_free(EXYNOS5_GPX1(5));
 289         } else {
 290                 /* fire nRESET on power off */
 291                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 292                 mdelay(20);
 293                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 294                 mdelay(20);
 295                 gpio_free(EXYNOS5_GPX1(5));
 296         }
 297         mdelay(20);
 298         /*
 299          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 300          * TODO: Fix this so we are not at risk of requesting the GPIO
 301          * multiple times, this should be done with device tree, and
 302          * likely integrated into the plat-samsung/dev-backlight.c init.
 303          */
 304         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
 305 }
 306
 307 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 308 {
 309         /* Don't call .set_power callback while unblanking */
 310         return 0;
 311 }
 312
 313 static struct plat_lcd_data smdk5250_lcd_data = {
 314         .set_power      = lcd_set_power,
 315         .match_fb       = smdk5250_match_fb,
 316 };
 317
 318 static struct platform_device smdk5250_lcd = {
 319         .name                   = "platform-lcd",
 320         .dev.platform_data      = &smdk5250_lcd_data,
 321 };
 322
 323 static int smdk5250_bl_notify(struct device *unused, int brightness)
 324 {
 325         /* manage lcd_bl_en signal */
 326         if (brightness)
 327                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 328         else
 329                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 330
 331         return brightness;
 332 }
 333
 334 /* LCD Backlight data */
 335 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 336         .no     = EXYNOS5_GPB2(0),
 337         .func   = S3C_GPIO_SFN(2),
 338 };
 339
 340 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 341         .pwm_period_ns  = 1000,
 342         .notify         = smdk5250_bl_notify,
 343 };
 344
 345 struct platform_device exynos_device_md0 = {
 346         .name = "exynos-mdev",
 347         .id = 0,
 348 };
 349
 350 struct platform_device exynos_device_md1 = {
 351         .name = "exynos-mdev",
 352         .id = 1,
 353 };
 354
 355 struct platform_device exynos_device_md2 = {
 356         .name = "exynos-mdev",
 357         .id = 2,
 358 };
 359
 360 static struct regulator_consumer_supply wm8994_avdd1_supply =
 361         REGULATOR_SUPPLY("AVDD1", "1-001a");
 362
 363 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 364         REGULATOR_SUPPLY("DCVDD", "1-001a");
 365
 366 static struct regulator_init_data wm8994_ldo1_data = {
 367         .constraints    = {
 368                 .name           = "AVDD1",
 369         },
 370         .num_consumer_supplies  = 1,
 371         .consumer_supplies      = &wm8994_avdd1_supply,
 372 };
 373
 374 static struct regulator_init_data wm8994_ldo2_data = {
 375         .constraints    = {
 376         .name                   = "DCVDD",
 377                 },
 378         .num_consumer_supplies  = 1,
 379         .consumer_supplies      = &wm8994_dcvdd_supply,
 380 };
 381
 382 static struct wm8994_pdata wm8994_platform_data = {
 383         /* configure gpio1 function: 0x0001(Logic level input/output) */
 384         .gpio_defaults[0] = 0x0001,
 385         /* If the i2s0 and i2s2 is enabled simultaneously */
 386         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 387         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 388         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 389         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 390         .ldo[0] = { 0, &wm8994_ldo1_data },
 391         .ldo[1] = { 0, &wm8994_ldo2_data },
 392 };
 393
 394 static struct i2c_board_info i2c_devs1[] __initdata = {
 395         {
 396                 I2C_BOARD_INFO("wm8994", 0x1a),
 397                 .platform_data  = &wm8994_platform_data,
 398         },
 399 };
 400
 401 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 402         .dbgname = "mfc_l",
 403         .clockname = "sysmmu",
 404 };
 405
 406 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 407         .dbgname = "mfc_r",
 408         .clockname = "sysmmu",
 409 };
 410
 411 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 412         .dbgname = "gsc",
 413         .clockname = "sysmmu",
 414 };
 415
 416 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 417         .dbgname = "g2d",
 418         .clockname = "sysmmu",
 419 };
 420
 421 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 422         .dbgname = "fimd",
 423         .clockname = "sysmmu",
 424 };
 425
 426 struct sysmmu_platform_data platdata_sysmmu_tv = {
 427         .dbgname = "tv",
 428         .clockname = "sysmmu",
 429 };
 430
 431 #ifdef CONFIG_VIDEO_FIMG2D4X
 432 static struct fimg2d_platdata fimg2d_data __initdata = {
 433         .hw_ver         = 0x42,
 434         .gate_clkname   = "fimg2d",
 435 };
 436 #endif
 437
 438 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 439         .phy_init = s5p_usb_phy_init,
 440         .phy_exit = s5p_usb_phy_exit,
 441 };
 442
 443 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 444         .phy_init = s5p_usb_phy_init,
 445         .phy_exit = s5p_usb_phy_exit,
 446 };
 447
 448 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 449         .phy_type = S5P_USB_PHY_DRD,
 450         .phy_init = s5p_usb_phy_init,
 451         .phy_exit = s5p_usb_phy_exit,
 452 };
 453
 454 struct exynos_gpio_cfg {
 455         unsigned int    addr;
 456         unsigned int    num;
 457         unsigned int    bit;
 458 };
 459
 460 static const char *rclksrc[] = {
 461         [0] = "busclk",
 462         [1] = "i2sclk",
 463 };
 464
 465 static struct video_info smdk5250_dp_config = {
 466         .name                   = "eDP-LVDS NXP PTN3460",
 467
 468         .h_sync_polarity        = 0,
 469         .v_sync_polarity        = 0,
 470         .interlaced             = 0,
 471
 472         .color_space            = COLOR_RGB,
 473         .dynamic_range          = VESA,
 474         .ycbcr_coeff            = COLOR_YCBCR601,
 475         .color_depth            = COLOR_8,
 476
 477         .link_rate              = LINK_RATE_2_70GBPS,
 478         .lane_count             = LANE_COUNT2,
 479 };
 480
 481 static struct exynos_dp_platdata smdk5250_dp_data __initdata = {
 482         .video_info     = &smdk5250_dp_config,
 483         .training_type  = HW_LINK_TRAINING,
 484         .phy_init       = s5p_dp_phy_init,
 485         .phy_exit       = s5p_dp_phy_exit,
 486 };
 487
 488 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 489 {
 490         int id;
 491         /* configure GPIO for i2s port */
 492         struct exynos_gpio_cfg exynos5_cfg[3] = {
 493                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 494                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 495                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 496         };
 497
 498         if (pdev->dev.of_node) {
 499                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 500                 if (id < 0)
 501                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 502         } else {
 503                 id = pdev->id;
 504         }
 505
 506         if (id < 0 || id > 2) {
 507                 printk(KERN_ERR "Invalid Device %d\n", id);
 508                 return -EINVAL;
 509         }
 510
 511         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 512                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 513
 514         return 0;
 515 }
 516
 517 static struct s3c_audio_pdata i2sv5_pdata = {
 518         .cfg_gpio = exynos_cfg_i2s_gpio,
 519         .type = {
 520                 .i2s = {
 521                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 522                                          | QUIRK_NEED_RSTCLR,
 523                         .src_clk = rclksrc,
 524                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 525                 },
 526         },
 527 };
 528 /*
 529  * The following lookup table is used to override device names when devices
 530  * are registered from device tree. This is temporarily added to enable
 531  * device tree support addition for the EXYNOS5 architecture.
 532  *
 533  * For drivers that require platform data to be provided from the machine
 534  * file, a platform data pointer can also be supplied along with the
 535  * devices names. Usually, the platform data elements that cannot be parsed
 536  * from the device tree by the drivers (example: function pointers) are
 537  * supplied. But it should be noted that this is a temporary mechanism and
 538  * at some point, the drivers should be capable of parsing all the platform
 539  * data from the device tree.
 540  */
 541 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 542         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 543                                 "exynos4210-uart.0", NULL),
 544         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 545                                 "exynos4210-uart.1", NULL),
 546         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 547                                 "exynos4210-uart.2", NULL),
 548         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 549                                 "exynos4210-uart.3", NULL),
 550         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 551                                 "s3c2440-i2c.0", NULL),
 552         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 553                                 "s3c2440-i2c.1", NULL),
 554         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 555                                 "s3c2440-i2c.2", NULL),
 556         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 557                                 "s3c2440-hdmiphy-i2c", NULL),
 558         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 559                                 "exynos4210-spi.0", NULL),
 560         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 561                                 "exynos4210-spi.1", NULL),
 562         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 563                                 "exynos4210-spi.2", NULL),
 564         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 565                                 "dw_mmc.0", NULL),
 566         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 567                                 "dw_mmc.1", NULL),
 568         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 569                                 "dw_mmc.2", NULL),
 570         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 571                                 "dw_mmc.3", NULL),
 572         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 573         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 574         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 575         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 576                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 577         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 578                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 579         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 580                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 581         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 582                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 583         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 584                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 585         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 586                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 587         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 588                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 589         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 590                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 591         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 592                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 593         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 594                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 595         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 596                                 "s5p-mipi-dsim", &dsim_platform_data),
 597         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 598                                 "s5p-dp", &smdk5250_dp_data),
 599         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 600         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 601                                 "exynos-gsc.0", NULL),
 602         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 603                                 "exynos-gsc.1", NULL),
 604         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 605                                 "exynos-gsc.2", NULL),
 606         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 607                                 "exynos-gsc.3", NULL),
 608 #ifdef CONFIG_VIDEO_FIMG2D4X
 609         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 610                                 "s5p-g2d", &fimg2d_data),
 611 #endif
 612         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 613                                 "exynos-ohci", &smdk5250_ohci_pdata),
 614         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 615                                 "s5p-ehci", &smdk5250_ehci_pdata),
 616         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 617                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 618         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 619                                 "samsung-i2s.0", &i2sv5_pdata),
 620         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 621                                 "exynos5-hdmi", NULL),
 622         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000, "s5p-mixer", NULL),
 623         {},
 624 };
 625
 626 static struct platform_device *smdk5250_devices[] __initdata = {
 627         &smdk5250_lcd, /* for platform_lcd device */
 628         &exynos_device_md0, /* for media device framework */
 629         &exynos_device_md1, /* for media device framework */
 630         &exynos_device_md2, /* for media device framework */
 631         &samsung_asoc_dma,  /* for audio dma interface device */
 632         &exynos_drm_device,
 633 };
 634
 635 static struct regulator_consumer_supply dummy_supplies[] = {
 636         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 637         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 638 };
 639
 640 static void __init exynos5250_dt_map_io(void)
 641 {
 642         exynos_init_io(NULL, 0);
 643         s3c24xx_init_clocks(24000000);
 644 }
 645
 646 static void __init exynos5_reserve(void)
 647 {
 648         /* required to have enough address range to remap the IOMMU
 649          * allocated buffers */
 650         init_consistent_dma_size(SZ_64M);
 651 }
 652
 653 static void s5p_tv_setup(void)
 654 {
 655         /* direct HPD to HDMI chip */
 656         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 657
 658         gpio_direction_input(EXYNOS5_GPX3(7));
 659         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 660         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 661 }
 662
 663 static void exynos5_i2c_setup(void)
 664 {
 665         /* Setup the low-speed i2c controller interrupts */
 666         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 667 }
 668
 669 static void __init exynos5250_dt_machine_init(void)
 670 {
 671         struct device_node *srom_np, *np;
 672
 673         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 674
 675         /* Setup pins for any SMSC 911x controller on the SROMC bus */
 676         srom_np = of_find_node_by_path("/sromc-bus");
 677         if (!srom_np) {
 678                 printk(KERN_ERR "No /sromc-bus property.\n");
 679                 goto out;
 680         }
 681         for_each_child_of_node(srom_np, np) {
 682                 if (of_device_is_compatible(np, "smsc,lan9115")) {
 683                         u32 reg;
 684                         of_property_read_u32(np, "reg", &reg);
 685                         smsc911x_init(reg);
 686                 }
 687         }
 688
 689         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 690
 691         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 692                 "HOST_VBUS_CONTROL")) {
 693                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 694         } else {
 695                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 696                 gpio_free(EXYNOS5_GPX2(6));
 697         }
 698
 699         exynos5_i2c_setup();
 700
 701         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 702
 703         of_platform_populate(NULL, of_default_bus_match_table,
 704                                 exynos5250_auxdata_lookup, NULL);
 705
 706 #ifdef CONFIG_DRM_EXYNOS_FIMD
 707         exynos_fimd_gpio_setup_24bpp();
 708 #endif
 709         s5p_tv_setup();
 710
 711         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 712 out:
 713         of_node_put(srom_np);
 714         return;
 715 }
 716
 717 static char const *exynos5250_dt_compat[] __initdata = {
 718         "samsung,exynos5250",
 719         NULL
 720 };
 721
 722 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 723         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 724         .init_irq       = exynos5_init_irq,
 725         .reserve        = exynos5_reserve,
 726         .map_io         = exynos5250_dt_map_io,
 727         .handle_irq     = gic_handle_irq,
 728         .init_machine   = exynos5250_dt_machine_init,
 729         .timer          = &exynos4_timer,
 730         .dt_compat      = exynos5250_dt_compat,
 731         .restart        = exynos5_restart,
 732 MACHINE_END