arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dwc3-exynos.h>
  15 #include <linux/serial_core.h>
  16 #include <linux/smsc911x.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/pwm_backlight.h>
  20 #include <linux/mfd/wm8994/pdata.h>
  21 #include <linux/regulator/machine.h>
  22
  23 #include <asm/mach/arch.h>
  24 #include <asm/hardware/gic.h>
  25 #include <mach/map.h>
  26 #include <mach/ohci.h>
  27 #include <mach/regs-pmu.h>
  28 #include <mach/sysmmu.h>
  29 #include <mach/ohci.h>
  30 #include <mach/regs-audss.h>
  31
  32 #include <plat/audio.h>
  33 #include <plat/cpu.h>
  34 #include <plat/dsim.h>
  35 #include <plat/fb.h>
  36 #include <plat/mipi_dsi.h>
  37 #include <plat/gpio-cfg.h>
  38 #include <plat/regs-fb.h>
  39 #include <plat/regs-serial.h>
  40 #include <plat/regs-srom.h>
  41 #include <plat/backlight.h>
  42 #include <plat/devs.h>
  43 #include <plat/usb-phy.h>
  44 #include <plat/ehci.h>
  45 #include <plat/dp.h>
  46
  47 #include <video/platform_lcd.h>
  48
  49 #include "drm/exynos_drm.h"
  50 #include "common.h"
  51
  52 static void __init smsc911x_init(int ncs)
  53 {
  54         u32 data;
  55
  56         /* configure nCS1 width to 16 bits */
  57         data = __raw_readl(S5P_SROM_BW) &
  58                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  59         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  60                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  61                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  62         __raw_writel(data, S5P_SROM_BW);
  63
  64         /* set timing for nCS1 suitable for ethernet chip */
  65         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  66                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  67                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  68                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  69                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  70                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  71                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  72                 S5P_SROM_BC0 + (ncs * 4));
  73 }
  74
  75 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  76         .win_mode = {
  77                 .left_margin    = 4,
  78                 .right_margin   = 4,
  79                 .upper_margin   = 4,
  80                 .lower_margin   = 4,
  81                 .hsync_len      = 4,
  82                 .vsync_len      = 4,
  83                 .xres           = 1280,
  84                 .yres           = 800,
  85         },
  86         .virtual_x              = 1280,
  87         .virtual_y              = 800 * 2,
  88         .width                  = 223,
  89         .height                 = 125,
  90         .max_bpp                = 32,
  91         .default_bpp            = 24,
  92 };
  93
  94 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
  95         .win_mode = {
  96                 .left_margin    = 4,
  97                 .right_margin   = 4,
  98                 .upper_margin   = 4,
  99                 .lower_margin   = 4,
 100                 .hsync_len      = 4,
 101                 .vsync_len      = 4,
 102                 .xres           = 1280,
 103                 .yres           = 800,
 104         },
 105         .virtual_x              = 1280,
 106         .virtual_y              = 800 * 2,
 107         .width                  = 223,
 108         .height                 = 125,
 109         .max_bpp                = 32,
 110         .default_bpp            = 24,
 111 };
 112
 113 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 114         .win_mode = {
 115                 .left_margin    = 0x4,
 116                 .right_margin   = 0x4,
 117                 .upper_margin   = 4,
 118                 .lower_margin   = 4,
 119                 .hsync_len      = 4,
 120                 .vsync_len      = 4,
 121                 .xres           = 1280,
 122                 .yres           = 800,
 123         },
 124         .virtual_x              = 1280,
 125         .virtual_y              = 800 * 2,
 126         .width                  = 223,
 127         .height                 = 125,
 128         .max_bpp                = 32,
 129         .default_bpp            = 24,
 130 };
 131
 132 static struct fb_videomode snow_fb_window = {
 133         .left_margin    = 0x80,
 134         .right_margin   = 0x48,
 135         .upper_margin   = 14,
 136         .lower_margin   = 3,
 137         .hsync_len      = 5,
 138         .vsync_len      = 32,
 139         .xres           = 1366,
 140         .yres           = 768,
 141 };
 142
 143 static void exynos_fimd_gpio_setup_24bpp(void)
 144 {
 145         unsigned int reg = 0;
 146
 147         /*
 148          * Set DISP1BLK_CFG register for Display path selection
 149          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 150          * ---------------------
 151          * 0 | MIE/MDNIE
 152          * 1 | FIMD : selected
 153          */
 154         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 155         reg &= ~(1 << 15);      /* To save other reset values */
 156         reg |= (1 << 15);
 157         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 158 }
 159
 160 static void exynos_dp_gpio_setup_24bpp(void)
 161 {
 162         exynos_fimd_gpio_setup_24bpp();
 163
 164         /* Set Hotplug detect for DP */
 165         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 166         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 167 }
 168
 169 #ifdef CONFIG_DRM_EXYNOS_FIMD
 170 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 171         .panel.timing   = {
 172                 .xres           = 1280,
 173                 .yres           = 800,
 174                 .hsync_len      = 4,
 175                 .left_margin    = 0x4,
 176                 .right_margin   = 0x4,
 177                 .vsync_len      = 4,
 178                 .upper_margin   = 4,
 179                 .lower_margin   = 4,
 180                 .refresh        = 60,
 181         },
 182         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 183         .vidcon1        = VIDCON1_INV_VCLK,
 184         .default_win    = 0,
 185         .bpp            = 32,
 186         .clock_rate     = 800 * 1000 * 1000,
 187 };
 188 #else
 189 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 190         .win[0]         = &smdk5250_fb_win0,
 191         .win[1]         = &smdk5250_fb_win1,
 192         .win[2]         = &smdk5250_fb_win2,
 193         .default_win    = 0,
 194         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 195         .vidcon1        = VIDCON1_INV_VCLK,
 196         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 197 };
 198 #endif
 199
 200 static struct mipi_dsim_config dsim_info = {
 201         .e_interface            = DSIM_VIDEO,
 202         .e_pixel_format         = DSIM_24BPP_888,
 203         /* main frame fifo auto flush at VSYNC pulse */
 204         .auto_flush             = false,
 205         .eot_disable            = false,
 206         .auto_vertical_cnt      = false,
 207         .hse                    = false,
 208         .hfp                    = false,
 209         .hbp                    = false,
 210         .hsa                    = false,
 211
 212         .e_no_data_lane         = DSIM_DATA_LANE_4,
 213         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 214         .e_burst_mode           = DSIM_BURST,
 215
 216         .p                      = 3,
 217         .m                      = 115,
 218         .s                      = 1,
 219
 220         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 221         .pll_stable_time        = 500,
 222
 223         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 224
 225         /* stop state holding counter after bta change count 0 ~ 0xfff */
 226         .stop_holding_cnt       = 0x0f,
 227         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 228         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 229
 230         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 231 };
 232
 233 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 234         .rgb_timing.left_margin         = 0x4,
 235         .rgb_timing.right_margin        = 0x4,
 236         .rgb_timing.upper_margin        = 0x4,
 237         .rgb_timing.lower_margin        =  0x4,
 238         .rgb_timing.hsync_len           = 0x4,
 239         .rgb_timing.vsync_len           = 0x4,
 240         .cpu_timing.cs_setup            = 0,
 241         .cpu_timing.wr_setup            = 1,
 242         .cpu_timing.wr_act              = 0,
 243         .cpu_timing.wr_hold             = 0,
 244         .lcd_size.width                 = 1280,
 245         .lcd_size.height                = 800,
 246 };
 247
 248 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 249         .clk_name               = "dsim0",
 250         .dsim_config            = &dsim_info,
 251         .dsim_lcd_config        = &dsim_lcd_info,
 252
 253         .part_reset             = s5p_dsim_part_reset,
 254         .init_d_phy             = s5p_dsim_init_d_phy,
 255         .get_fb_frame_done      = NULL,
 256         .trigger                = NULL,
 257
 258         /*
 259          * the stable time of needing to write data on SFR
 260          * when the mipi mode becomes LP mode.
 261          */
 262         .delay_for_stabilization = 600,
 263 };
 264
 265 static struct platform_device exynos_drm_device = {
 266         .name           = "exynos-drm",
 267         .dev = {
 268                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 269                 .coherent_dma_mask = 0xffffffffUL,
 270         }
 271 };
 272
 273 static void lcd_set_power(struct plat_lcd_data *pd,
 274                         unsigned int power)
 275 {
 276         /* reset */
 277         gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 278
 279         mdelay(20);
 280         if (power) {
 281                 /* fire nRESET on power up */
 282                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 283                 mdelay(20);
 284                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 285                 mdelay(20);
 286                 gpio_free(EXYNOS5_GPX1(5));
 287         } else {
 288                 /* fire nRESET on power off */
 289                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 290                 mdelay(20);
 291                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 292                 mdelay(20);
 293                 gpio_free(EXYNOS5_GPX1(5));
 294         }
 295         mdelay(20);
 296         /*
 297          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 298          * TODO: Fix this so we are not at risk of requesting the GPIO
 299          * multiple times, this should be done with device tree, and
 300          * likely integrated into the plat-samsung/dev-backlight.c init.
 301          */
 302         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
 303 }
 304
 305 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 306 {
 307         /* Don't call .set_power callback while unblanking */
 308         return 0;
 309 }
 310
 311 static struct plat_lcd_data smdk5250_lcd_data = {
 312         .set_power      = lcd_set_power,
 313         .match_fb       = smdk5250_match_fb,
 314 };
 315
 316 static struct platform_device smdk5250_lcd = {
 317         .name                   = "platform-lcd",
 318         .dev.platform_data      = &smdk5250_lcd_data,
 319 };
 320
 321 static int smdk5250_bl_notify(struct device *unused, int brightness)
 322 {
 323         /* manage lcd_bl_en signal */
 324         if (brightness)
 325                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 326         else
 327                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 328
 329         return brightness;
 330 }
 331
 332 /* LCD Backlight data */
 333 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 334         .no     = EXYNOS5_GPB2(0),
 335         .func   = S3C_GPIO_SFN(2),
 336 };
 337
 338 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 339         .pwm_period_ns  = 1000,
 340         .notify         = smdk5250_bl_notify,
 341 };
 342
 343 struct platform_device exynos_device_md0 = {
 344         .name = "exynos-mdev",
 345         .id = 0,
 346 };
 347
 348 struct platform_device exynos_device_md1 = {
 349         .name = "exynos-mdev",
 350         .id = 1,
 351 };
 352
 353 struct platform_device exynos_device_md2 = {
 354         .name = "exynos-mdev",
 355         .id = 2,
 356 };
 357
 358 static struct regulator_consumer_supply wm8994_avdd1_supply =
 359         REGULATOR_SUPPLY("AVDD1", "1-001a");
 360
 361 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 362         REGULATOR_SUPPLY("DCVDD", "1-001a");
 363
 364 static struct regulator_init_data wm8994_ldo1_data = {
 365         .constraints    = {
 366                 .name           = "AVDD1",
 367         },
 368         .num_consumer_supplies  = 1,
 369         .consumer_supplies      = &wm8994_avdd1_supply,
 370 };
 371
 372 static struct regulator_init_data wm8994_ldo2_data = {
 373         .constraints    = {
 374         .name                   = "DCVDD",
 375                 },
 376         .num_consumer_supplies  = 1,
 377         .consumer_supplies      = &wm8994_dcvdd_supply,
 378 };
 379
 380 static struct wm8994_pdata wm8994_platform_data = {
 381         /* configure gpio1 function: 0x0001(Logic level input/output) */
 382         .gpio_defaults[0] = 0x0001,
 383         /* If the i2s0 and i2s2 is enabled simultaneously */
 384         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 385         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 386         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 387         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 388         .ldo[0] = { 0, &wm8994_ldo1_data },
 389         .ldo[1] = { 0, &wm8994_ldo2_data },
 390 };
 391
 392 static struct i2c_board_info i2c_devs1[] __initdata = {
 393         {
 394                 I2C_BOARD_INFO("wm8994", 0x1a),
 395                 .platform_data  = &wm8994_platform_data,
 396         },
 397 };
 398
 399 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 400         .dbgname = "mfc_l",
 401         .clockname = "sysmmu",
 402 };
 403
 404 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 405         .dbgname = "mfc_r",
 406         .clockname = "sysmmu",
 407 };
 408
 409 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 410         .dbgname = "gsc",
 411         .clockname = "sysmmu",
 412 };
 413
 414 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 415         .dbgname = "g2d",
 416         .clockname = "sysmmu",
 417 };
 418
 419 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 420         .dbgname = "fimd",
 421         .clockname = "sysmmu",
 422 };
 423
 424 struct sysmmu_platform_data platdata_sysmmu_tv = {
 425         .dbgname = "tv",
 426         .clockname = "sysmmu",
 427 };
 428
 429 #ifdef CONFIG_VIDEO_FIMG2D4X
 430 static struct fimg2d_platdata fimg2d_data __initdata = {
 431         .hw_ver         = 0x42,
 432         .gate_clkname   = "fimg2d",
 433 };
 434 #endif
 435
 436 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 437         .phy_init = s5p_usb_phy_init,
 438         .phy_exit = s5p_usb_phy_exit,
 439 };
 440
 441 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 442         .phy_init = s5p_usb_phy_init,
 443         .phy_exit = s5p_usb_phy_exit,
 444 };
 445
 446 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 447         .phy_type = S5P_USB_PHY_DRD,
 448         .phy_init = s5p_usb_phy_init,
 449         .phy_exit = s5p_usb_phy_exit,
 450 };
 451
 452 struct exynos_gpio_cfg {
 453         unsigned int    addr;
 454         unsigned int    num;
 455         unsigned int    bit;
 456 };
 457
 458 static const char *rclksrc[] = {
 459         [0] = "busclk",
 460         [1] = "i2sclk",
 461 };
 462
 463 static struct video_info smdk5250_dp_config = {
 464         .name                   = "eDP-LVDS NXP PTN3460",
 465
 466         .h_sync_polarity        = 0,
 467         .v_sync_polarity        = 0,
 468         .interlaced             = 0,
 469
 470         .color_space            = COLOR_RGB,
 471         .dynamic_range          = VESA,
 472         .ycbcr_coeff            = COLOR_YCBCR601,
 473         .color_depth            = COLOR_8,
 474
 475         .link_rate              = LINK_RATE_2_70GBPS,
 476         .lane_count             = LANE_COUNT2,
 477 };
 478
 479 static struct exynos_dp_platdata smdk5250_dp_data __initdata = {
 480         .video_info     = &smdk5250_dp_config,
 481         .training_type  = HW_LINK_TRAINING,
 482         .phy_init       = s5p_dp_phy_init,
 483         .phy_exit       = s5p_dp_phy_exit,
 484 };
 485
 486 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 487 {
 488         int id;
 489         /* configure GPIO for i2s port */
 490         struct exynos_gpio_cfg exynos5_cfg[3] = {
 491                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 492                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 493                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 494         };
 495
 496         if (pdev->dev.of_node) {
 497                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 498                 if (id < 0)
 499                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 500         } else {
 501                 id = pdev->id;
 502         }
 503
 504         if (id < 0 || id > 2) {
 505                 printk(KERN_ERR "Invalid Device %d\n", id);
 506                 return -EINVAL;
 507         }
 508
 509         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 510                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 511
 512         return 0;
 513 }
 514
 515 static struct s3c_audio_pdata i2sv5_pdata = {
 516         .cfg_gpio = exynos_cfg_i2s_gpio,
 517         .type = {
 518                 .i2s = {
 519                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 520                                          | QUIRK_NEED_RSTCLR,
 521                         .src_clk = rclksrc,
 522                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 523                 },
 524         },
 525 };
 526 /*
 527  * The following lookup table is used to override device names when devices
 528  * are registered from device tree. This is temporarily added to enable
 529  * device tree support addition for the EXYNOS5 architecture.
 530  *
 531  * For drivers that require platform data to be provided from the machine
 532  * file, a platform data pointer can also be supplied along with the
 533  * devices names. Usually, the platform data elements that cannot be parsed
 534  * from the device tree by the drivers (example: function pointers) are
 535  * supplied. But it should be noted that this is a temporary mechanism and
 536  * at some point, the drivers should be capable of parsing all the platform
 537  * data from the device tree.
 538  */
 539 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 540         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 541                                 "exynos4210-uart.0", NULL),
 542         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 543                                 "exynos4210-uart.1", NULL),
 544         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 545                                 "exynos4210-uart.2", NULL),
 546         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 547                                 "exynos4210-uart.3", NULL),
 548         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 549                                 "s3c2440-i2c.0", NULL),
 550         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 551                                 "s3c2440-i2c.1", NULL),
 552         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 553                                 "s3c2440-i2c.2", NULL),
 554         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 555                                 "s3c2440-hdmiphy-i2c", NULL),
 556         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 557                                 "exynos4210-spi.0", NULL),
 558         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 559                                 "exynos4210-spi.1", NULL),
 560         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 561                                 "exynos4210-spi.2", NULL),
 562         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 563                                 "dw_mmc.0", NULL),
 564         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 565                                 "dw_mmc.1", NULL),
 566         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 567                                 "dw_mmc.2", NULL),
 568         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 569                                 "dw_mmc.3", NULL),
 570         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 571         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 572         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 573         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 574                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 575         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 576                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 577         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 578                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 579         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 580                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 581         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 582                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 583         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 584                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 585         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 586                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 587         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 588                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 589         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 590                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 591         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 592                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 593         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 594                                 "s5p-mipi-dsim", &dsim_platform_data),
 595         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 596                                 "s5p-dp", &smdk5250_dp_data),
 597         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 598         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 599                                 "exynos-gsc.0", NULL),
 600         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 601                                 "exynos-gsc.1", NULL),
 602         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 603                                 "exynos-gsc.2", NULL),
 604         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 605                                 "exynos-gsc.3", NULL),
 606 #ifdef CONFIG_VIDEO_FIMG2D4X
 607         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 608                                 "s5p-g2d", &fimg2d_data),
 609 #endif
 610         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 611                                 "exynos-ohci", &smdk5250_ohci_pdata),
 612         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 613                                 "s5p-ehci", &smdk5250_ehci_pdata),
 614         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 615                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 616         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 617                                 "samsung-i2s.0", &i2sv5_pdata),
 618         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 619                                 "exynos5-hdmi", NULL),
 620         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000, "s5p-mixer", NULL),
 621         {},
 622 };
 623
 624 static struct platform_device *smdk5250_devices[] __initdata = {
 625         &smdk5250_lcd, /* for platform_lcd device */
 626         &exynos_device_md0, /* for media device framework */
 627         &exynos_device_md1, /* for media device framework */
 628         &exynos_device_md2, /* for media device framework */
 629         &samsung_asoc_dma,  /* for audio dma interface device */
 630         &exynos_drm_device,
 631 };
 632
 633 static void __init exynos5250_dt_map_io(void)
 634 {
 635         exynos_init_io(NULL, 0);
 636         s3c24xx_init_clocks(24000000);
 637 }
 638
 639 static void __init exynos5_reserve(void)
 640 {
 641         /* required to have enough address range to remap the IOMMU
 642          * allocated buffers */
 643         init_consistent_dma_size(SZ_64M);
 644 }
 645
 646 static void s5p_tv_setup(void)
 647 {
 648         /* direct HPD to HDMI chip */
 649         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 650
 651         gpio_direction_input(EXYNOS5_GPX3(7));
 652         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 653         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 654 }
 655
 656 static void exynos5_i2c_setup(void)
 657 {
 658         /* Setup the low-speed i2c controller interrupts */
 659         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 660 }
 661
 662 static void __init exynos5250_dt_machine_init(void)
 663 {
 664         if (of_machine_is_compatible("samsung,smdk5250"))
 665                 smsc911x_init(1);
 666         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 667
 668         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 669                 "HOST_VBUS_CONTROL")) {
 670                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 671         } else {
 672                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 673                 gpio_free(EXYNOS5_GPX2(6));
 674         }
 675
 676         exynos5_i2c_setup();
 677
 678         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 679
 680         of_platform_populate(NULL, of_default_bus_match_table,
 681                                 exynos5250_auxdata_lookup, NULL);
 682
 683 #ifdef CONFIG_DRM_EXYNOS_FIMD
 684         exynos_fimd_gpio_setup_24bpp();
 685 #endif
 686         s5p_tv_setup();
 687
 688         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 689 }
 690
 691 static char const *exynos5250_dt_compat[] __initdata = {
 692         "samsung,exynos5250",
 693         NULL
 694 };
 695
 696 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 697         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 698         .init_irq       = exynos5_init_irq,
 699         .reserve        = exynos5_reserve,
 700         .map_io         = exynos5250_dt_map_io,
 701         .handle_irq     = gic_handle_irq,
 702         .init_machine   = exynos5250_dt_machine_init,
 703         .timer          = &exynos4_timer,
 704         .dt_compat      = exynos5250_dt_compat,
 705         .restart        = exynos5_restart,
 706 MACHINE_END