arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/platform_data/dwc3-exynos.h>
  16 #include <linux/regulator/fixed.h>
  17 #include <linux/regulator/machine.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/smsc911x.h>
  20 #include <linux/delay.h>
  21 #include <linux/i2c.h>
  22 #include <linux/pwm_backlight.h>
  23 #include <linux/mfd/wm8994/pdata.h>
  24 #include <linux/regulator/machine.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/memblock.h>
  27 #include <linux/of_fdt.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/hardware/gic.h>
  31 #include <mach/map.h>
  32 #include <mach/ohci.h>
  33 #include <mach/regs-pmu.h>
  34 #include <mach/sysmmu.h>
  35 #include <mach/ohci.h>
  36 #include <mach/regs-audss.h>
  37 #include <mach/regs-pmu.h>
  38
  39 #include <plat/audio.h>
  40 #include <plat/cpu.h>
  41 #include <plat/dsim.h>
  42 #include <plat/fb.h>
  43 #include <plat/mipi_dsi.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/regs-fb.h>
  46 #include <plat/regs-serial.h>
  47 #include <plat/regs-srom.h>
  48 #include <plat/backlight.h>
  49 #include <plat/devs.h>
  50 #include <plat/usb-phy.h>
  51 #include <plat/ehci.h>
  52 #include <plat/dp.h>
  53 #include <plat/s3c64xx-spi.h>
  54 #include <plat/adc.h>
  55
  56 #include <video/platform_lcd.h>
  57
  58 #include "drm/exynos_drm.h"
  59 #include "common.h"
  60
  61 static void __init smsc911x_init(int ncs)
  62 {
  63         u32 data;
  64
  65         /* configure nCS1 width to 16 bits */
  66         data = __raw_readl(S5P_SROM_BW) &
  67                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  68         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  69                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  70                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  71         __raw_writel(data, S5P_SROM_BW);
  72
  73         /* set timing for nCS1 suitable for ethernet chip */
  74         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  75                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  76                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  77                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  78                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  79                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  80                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  81                 S5P_SROM_BC0 + (ncs * 4));
  82 }
  83
  84 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  85         .win_mode = {
  86                 .left_margin    = 4,
  87                 .right_margin   = 4,
  88                 .upper_margin   = 4,
  89                 .lower_margin   = 4,
  90                 .hsync_len      = 4,
  91                 .vsync_len      = 4,
  92                 .xres           = 1280,
  93                 .yres           = 800,
  94         },
  95         .virtual_x              = 1280,
  96         .virtual_y              = 800 * 2,
  97         .width                  = 223,
  98         .height                 = 125,
  99         .max_bpp                = 32,
 100         .default_bpp            = 24,
 101 };
 102
 103 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
 104         .win_mode = {
 105                 .left_margin    = 4,
 106                 .right_margin   = 4,
 107                 .upper_margin   = 4,
 108                 .lower_margin   = 4,
 109                 .hsync_len      = 4,
 110                 .vsync_len      = 4,
 111                 .xres           = 1280,
 112                 .yres           = 800,
 113         },
 114         .virtual_x              = 1280,
 115         .virtual_y              = 800 * 2,
 116         .width                  = 223,
 117         .height                 = 125,
 118         .max_bpp                = 32,
 119         .default_bpp            = 24,
 120 };
 121
 122 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 123         .win_mode = {
 124                 .left_margin    = 0x4,
 125                 .right_margin   = 0x4,
 126                 .upper_margin   = 4,
 127                 .lower_margin   = 4,
 128                 .hsync_len      = 4,
 129                 .vsync_len      = 4,
 130                 .xres           = 1280,
 131                 .yres           = 800,
 132         },
 133         .virtual_x              = 1280,
 134         .virtual_y              = 800 * 2,
 135         .width                  = 223,
 136         .height                 = 125,
 137         .max_bpp                = 32,
 138         .default_bpp            = 24,
 139 };
 140
 141 static struct fb_videomode snow_fb_window[] = {
 142         [0] = { /* Only LCD Connected */
 143                 .left_margin    = 0,
 144                 .right_margin   = 0,
 145                 .upper_margin   = 4,
 146                 .lower_margin   = 4,
 147                 .hsync_len      = 5,
 148                 .vsync_len      = 32,
 149                 .xres           = 1366,
 150                 .yres           = 768,
 151         },
 152         [1] = { /* TV & LCD Connected */
 153                 .left_margin    = 70,
 154                 .right_margin   = 70,
 155                 .upper_margin   = 12,
 156                 .lower_margin   = 13,
 157                 .hsync_len      = 5,
 158                 .vsync_len      = 32,
 159                 .xres           = 1280,
 160                 .yres           = 720,
 161         },
 162         [2] = {
 163                 .xres           = -1,
 164                 .yres           = -1,
 165         },
 166 };
 167
 168 static void exynos_fimd_gpio_setup_24bpp(void)
 169 {
 170         unsigned int reg = 0;
 171
 172         /*
 173          * Set DISP1BLK_CFG register for Display path selection
 174          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 175          * ---------------------
 176          * 0 | MIE/MDNIE
 177          * 1 | FIMD : selected
 178          */
 179         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 180         reg &= ~(1 << 15);      /* To save other reset values */
 181         reg |= (1 << 15);
 182         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 183 }
 184
 185 static void exynos_dp_gpio_setup_24bpp(void)
 186 {
 187         exynos_fimd_gpio_setup_24bpp();
 188
 189         /* Set Hotplug detect for DP */
 190         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 191         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 192 }
 193
 194 #ifdef CONFIG_DRM_EXYNOS_HDMI
 195 static struct platform_device exynos_drm_hdmi_device = {
 196         .name           = "exynos-drm-hdmi",
 197 };
 198
 199 static struct exynos_drm_hdmi_pdata drm_mixer_pdata = {
 200         .timing = {
 201                 .xres    = 1920,
 202                 .yres    = 1080,
 203                 .refresh = 60,
 204         },
 205         .default_win    = 0,
 206         .bpp            = 32,
 207         .is_v13         = 0,
 208         .is_soc_exynos5 = 1,
 209 };
 210
 211 static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = {
 212         .timing = {
 213                 .xres    = 1920,
 214                 .yres    = 1080,
 215                 .refresh    = 60,
 216         },
 217         .default_win    = 0,
 218         .bpp            = 32,
 219         .is_v13         = 0,
 220         .is_soc_exynos5 = 1,
 221 };
 222 #endif
 223
 224 #ifdef CONFIG_DRM_EXYNOS_FIMD
 225 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 226         .panel[0].timing   = {
 227                 .xres           = 1280,
 228                 .yres           = 800,
 229                 .hsync_len      = 4,
 230                 .left_margin    = 0x4,
 231                 .right_margin   = 0x4,
 232                 .vsync_len      = 4,
 233                 .upper_margin   = 4,
 234                 .lower_margin   = 4,
 235                 .refresh        = 60,
 236         },
 237         .panel[1].timing   = {
 238                 .xres           = 1280,
 239                 .yres           = 720,
 240                 .hsync_len      = 4,
 241                 .left_margin    = 0x4,
 242                 .right_margin   = 0x4,
 243                 .vsync_len      = 4,
 244                 .upper_margin   = 4,
 245                 .lower_margin   = 4,
 246                 .refresh        = 60,
 247         },
 248         .panel[2].timing   = {
 249                 .xres           = -1,
 250                 .yres           = -1,
 251         },
 252         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 253         .vidcon1        = VIDCON1_INV_VCLK,
 254         .default_win    = 0,
 255         .bpp            = 32,
 256         .clock_rate     = 800 * 1000 * 1000,
 257 };
 258 #else
 259 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 260         .win[0]         = &smdk5250_fb_win0,
 261         .win[1]         = &smdk5250_fb_win1,
 262         .win[2]         = &smdk5250_fb_win2,
 263         .default_win    = 0,
 264         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 265         .vidcon1        = VIDCON1_INV_VCLK,
 266         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 267         .clock_rate     = 800 * 1000 * 1000,
 268 };
 269 #endif
 270
 271 static struct mipi_dsim_config dsim_info = {
 272         .e_interface            = DSIM_VIDEO,
 273         .e_pixel_format         = DSIM_24BPP_888,
 274         /* main frame fifo auto flush at VSYNC pulse */
 275         .auto_flush             = false,
 276         .eot_disable            = false,
 277         .auto_vertical_cnt      = false,
 278         .hse                    = false,
 279         .hfp                    = false,
 280         .hbp                    = false,
 281         .hsa                    = false,
 282
 283         .e_no_data_lane         = DSIM_DATA_LANE_4,
 284         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 285         .e_burst_mode           = DSIM_BURST,
 286
 287         .p                      = 3,
 288         .m                      = 115,
 289         .s                      = 1,
 290
 291         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 292         .pll_stable_time        = 500,
 293
 294         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 295
 296         /* stop state holding counter after bta change count 0 ~ 0xfff */
 297         .stop_holding_cnt       = 0x0f,
 298         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 299         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 300
 301         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 302 };
 303
 304 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 305         .rgb_timing.left_margin         = 0x4,
 306         .rgb_timing.right_margin        = 0x4,
 307         .rgb_timing.upper_margin        = 0x4,
 308         .rgb_timing.lower_margin        =  0x4,
 309         .rgb_timing.hsync_len           = 0x4,
 310         .rgb_timing.vsync_len           = 0x4,
 311         .cpu_timing.cs_setup            = 0,
 312         .cpu_timing.wr_setup            = 1,
 313         .cpu_timing.wr_act              = 0,
 314         .cpu_timing.wr_hold             = 0,
 315         .lcd_size.width                 = 1280,
 316         .lcd_size.height                = 800,
 317 };
 318
 319 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 320         .clk_name               = "dsim0",
 321         .dsim_config            = &dsim_info,
 322         .dsim_lcd_config        = &dsim_lcd_info,
 323
 324         .part_reset             = s5p_dsim_part_reset,
 325         .init_d_phy             = s5p_dsim_init_d_phy,
 326         .get_fb_frame_done      = NULL,
 327         .trigger                = NULL,
 328
 329         /*
 330          * the stable time of needing to write data on SFR
 331          * when the mipi mode becomes LP mode.
 332          */
 333         .delay_for_stabilization = 600,
 334 };
 335
 336 static struct platform_device exynos_drm_device = {
 337         .name           = "exynos-drm",
 338         .dev = {
 339                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 340                 .coherent_dma_mask = 0xffffffffUL,
 341         }
 342 };
 343
 344 static void lcd_set_power(struct plat_lcd_data *pd,
 345                         unsigned int power)
 346 {
 347         if (of_machine_is_compatible("google,daisy") ||
 348                         of_machine_is_compatible("google,snow")) {
 349                 struct regulator *lcd_fet;
 350
 351                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 352                 if (!IS_ERR(lcd_fet)) {
 353                         if (power)
 354                                 regulator_enable(lcd_fet);
 355                         else
 356                                 regulator_disable(lcd_fet);
 357
 358                         regulator_put(lcd_fet);
 359                 }
 360         }
 361
 362         if (!of_machine_is_compatible("google,snow")) {
 363                 /* reset */
 364                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 365                 mdelay(20);
 366                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 367                 mdelay(20);
 368                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 369                 mdelay(20);
 370                 gpio_free(EXYNOS5_GPX1(5));
 371                 mdelay(20);
 372         }
 373
 374
 375         /* Turn on regulator for backlight */
 376         if (of_machine_is_compatible("google,daisy") ||
 377                         of_machine_is_compatible("google,snow")) {
 378                 struct regulator *backlight_fet;
 379
 380                 backlight_fet = regulator_get(NULL, "vcd_led");
 381                 if (!IS_ERR(backlight_fet)) {
 382                         if (power)
 383                                 regulator_enable(backlight_fet);
 384                         else
 385                                 regulator_disable(backlight_fet);
 386
 387                         regulator_put(backlight_fet);
 388                 }
 389                 /* Wait 10 ms between regulator on and PWM start per spec */
 390                 mdelay(10);
 391         }
 392 }
 393
 394 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 395 {
 396         /* Don't call .set_power callback while unblanking */
 397         return 0;
 398 }
 399
 400 static struct plat_lcd_data smdk5250_lcd_data = {
 401         .set_power      = lcd_set_power,
 402         .match_fb       = smdk5250_match_fb,
 403 };
 404
 405 static struct platform_device smdk5250_lcd = {
 406         .name                   = "platform-lcd",
 407         .dev.platform_data      = &smdk5250_lcd_data,
 408 };
 409
 410 static int smdk5250_bl_notify(struct device *unused, int brightness)
 411 {
 412         /* manage lcd_bl_en signal */
 413         if (brightness)
 414                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 415         else
 416                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 417
 418         return brightness;
 419 }
 420
 421 /* LCD Backlight data */
 422 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 423         .no     = EXYNOS5_GPB2(0),
 424         .func   = S3C_GPIO_SFN(2),
 425 };
 426
 427 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 428         .pwm_period_ns  = 1000000,
 429         .notify         = smdk5250_bl_notify,
 430 };
 431
 432 struct platform_device exynos_device_md0 = {
 433         .name = "exynos-mdev",
 434         .id = 0,
 435 };
 436
 437 struct platform_device exynos_device_md1 = {
 438         .name = "exynos-mdev",
 439         .id = 1,
 440 };
 441
 442 struct platform_device exynos_device_md2 = {
 443         .name = "exynos-mdev",
 444         .id = 2,
 445 };
 446
 447 static struct regulator_consumer_supply wm8994_avdd1_supply =
 448         REGULATOR_SUPPLY("AVDD1", "1-001a");
 449
 450 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 451         REGULATOR_SUPPLY("DCVDD", "1-001a");
 452
 453 static struct regulator_init_data wm8994_ldo1_data = {
 454         .constraints    = {
 455                 .name           = "AVDD1",
 456         },
 457         .num_consumer_supplies  = 1,
 458         .consumer_supplies      = &wm8994_avdd1_supply,
 459 };
 460
 461 static struct regulator_init_data wm8994_ldo2_data = {
 462         .constraints    = {
 463         .name                   = "DCVDD",
 464                 },
 465         .num_consumer_supplies  = 1,
 466         .consumer_supplies      = &wm8994_dcvdd_supply,
 467 };
 468
 469 static struct wm8994_pdata wm8994_platform_data = {
 470         /* configure gpio1 function: 0x0001(Logic level input/output) */
 471         .gpio_defaults[0] = 0x0001,
 472         /* If the i2s0 and i2s2 is enabled simultaneously */
 473         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 474         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 475         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 476         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 477         .ldo[0] = { 0, &wm8994_ldo1_data },
 478         .ldo[1] = { 0, &wm8994_ldo2_data },
 479 };
 480
 481 static struct i2c_board_info i2c_devs1[] __initdata = {
 482         {
 483                 I2C_BOARD_INFO("wm8994", 0x1a),
 484                 .platform_data  = &wm8994_platform_data,
 485         },
 486 };
 487
 488 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 489         [0] = {
 490                 .line           = EXYNOS5_GPA2(5),
 491                 .fb_delay       = 0x2,
 492         },
 493 };
 494
 495 static struct spi_board_info spi1_board_info[] __initdata = {
 496         {
 497                 .modalias               = "spidev",
 498                 .platform_data          = NULL,
 499                 .max_speed_hz           = 10*1000*1000,
 500                 .bus_num                = 1,
 501                 .chip_select            = 0,
 502                 .mode                   = SPI_MODE_0,
 503                 .controller_data        = spi1_csi,
 504         }
 505 };
 506
 507 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 508         .dbgname = "mfc_l",
 509         .clockname = "sysmmu",
 510 };
 511
 512 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 513         .dbgname = "mfc_r",
 514         .clockname = "sysmmu",
 515 };
 516
 517 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 518         .dbgname = "gsc",
 519         .clockname = "sysmmu",
 520 };
 521
 522 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 523         .dbgname = "g2d",
 524         .clockname = "sysmmu",
 525 };
 526
 527 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 528         .dbgname = "fimd",
 529         .clockname = "sysmmu",
 530 };
 531
 532 struct sysmmu_platform_data platdata_sysmmu_tv = {
 533         .dbgname = "tv",
 534         .clockname = "sysmmu",
 535 };
 536
 537 #ifdef CONFIG_VIDEO_FIMG2D4X
 538 static struct fimg2d_platdata fimg2d_data __initdata = {
 539         .hw_ver         = 0x42,
 540         .gate_clkname   = "fimg2d",
 541 };
 542 #endif
 543
 544 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 545         .phy_init = s5p_usb_phy_init,
 546         .phy_exit = s5p_usb_phy_exit,
 547 };
 548
 549 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 550         .phy_init = s5p_usb_phy_init,
 551         .phy_exit = s5p_usb_phy_exit,
 552 };
 553
 554 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 555         .phy_type = S5P_USB_PHY_DRD,
 556         .phy_init = s5p_usb_phy_init,
 557         .phy_exit = s5p_usb_phy_exit,
 558 };
 559
 560 struct exynos_gpio_cfg {
 561         unsigned int    addr;
 562         unsigned int    num;
 563         unsigned int    bit;
 564 };
 565
 566 static const char *rclksrc[] = {
 567         [0] = "busclk",
 568         [1] = "i2sclk",
 569 };
 570
 571 static struct video_info smdk5250_dp_config = {
 572         .name                   = "eDP-LVDS NXP PTN3460",
 573
 574         .h_sync_polarity        = 0,
 575         .v_sync_polarity        = 0,
 576         .interlaced             = 0,
 577
 578         .color_space            = COLOR_RGB,
 579         .dynamic_range          = VESA,
 580         .ycbcr_coeff            = COLOR_YCBCR601,
 581         .color_depth            = COLOR_8,
 582
 583         .link_rate              = LINK_RATE_2_70GBPS,
 584         .lane_count             = LANE_COUNT2,
 585 };
 586
 587 static void get_dp_bridge_gpios(int *pd_n_gpio, int *rst_n_gpio)
 588 {
 589         struct device_node *np;
 590
 591         np = of_find_compatible_node(NULL, NULL, "nxp,ptn3460");
 592         *pd_n_gpio = np ? of_get_named_gpio(np, "pd_n_gpio", 0) : -1;
 593         *rst_n_gpio = np ? of_get_named_gpio(np, "rst_n_gpio", 0) : -1;
 594 }
 595
 596 static void dp_phy_init(void)
 597 {
 598         int pd_n_gpio, rst_n_gpio;
 599
 600         get_dp_bridge_gpios(&pd_n_gpio, &rst_n_gpio);
 601         if (pd_n_gpio >= 0)
 602                 gpio_set_value(pd_n_gpio, 1);
 603
 604         if (rst_n_gpio >= 0) {
 605                 gpio_set_value(rst_n_gpio, 0);
 606                 udelay(10);
 607                 gpio_set_value(rst_n_gpio, 1);
 608         }
 609
 610         /* This really sucks, but we can't trust HPD from the bridge */
 611         if (pd_n_gpio >= 0)
 612                 msleep(90);
 613
 614         s5p_dp_phy_init();
 615 }
 616
 617 static struct exynos_dp_platdata smdk5250_dp_data = {
 618         .video_info     = &smdk5250_dp_config,
 619         .training_type  = SW_LINK_TRAINING,
 620         .phy_init       = dp_phy_init,
 621         .phy_exit       = s5p_dp_phy_exit,
 622 };
 623
 624 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 625 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 626 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 627 /* Mask bit[12:8] for xxti clock selection */
 628 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 629
 630 static void __init enable_xclkout(void)
 631 {
 632        unsigned int tmp;
 633
 634        tmp = readl(S5P_PMU_DEBUG);
 635        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 636        tmp |= PMU_DEBUG_XXTI;
 637        writel(tmp, S5P_PMU_DEBUG);
 638 }
 639
 640 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 641 {
 642         int id;
 643         /* configure GPIO for i2s port */
 644         struct exynos_gpio_cfg exynos5_cfg[3] = {
 645                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 646                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 647                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 648         };
 649
 650         if (pdev->dev.of_node) {
 651                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 652                 if (id < 0)
 653                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 654         } else {
 655                 id = pdev->id;
 656         }
 657
 658         if (id < 0 || id > 2) {
 659                 printk(KERN_ERR "Invalid Device %d\n", id);
 660                 return -EINVAL;
 661         }
 662
 663         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 664                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 665
 666         return 0;
 667 }
 668
 669 static struct s3c_audio_pdata i2sv5_pdata = {
 670         .cfg_gpio = exynos_cfg_i2s_gpio,
 671         .type = {
 672                 .i2s = {
 673                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 674                                          | QUIRK_NEED_RSTCLR,
 675                         .src_clk = rclksrc,
 676                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 677                 },
 678         },
 679 };
 680
 681 static struct resource exynos5_adc_resource[] = {
 682         [0] = DEFINE_RES_MEM(EXYNOS5_PA_ADC, SZ_256),
 683         [1] = DEFINE_RES_IRQ(EXYNOS5_IRQ_ADC0),
 684 };
 685
 686 struct platform_device exynos5_device_adc = {
 687         .name           = "samsung-adc-v4",
 688         .id             = -1,
 689         .num_resources  = ARRAY_SIZE(exynos5_adc_resource),
 690         .resource       = exynos5_adc_resource,
 691 };
 692
 693 /*
 694  * The following lookup table is used to override device names when devices
 695  * are registered from device tree. This is temporarily added to enable
 696  * device tree support addition for the EXYNOS5 architecture.
 697  *
 698  * For drivers that require platform data to be provided from the machine
 699  * file, a platform data pointer can also be supplied along with the
 700  * devices names. Usually, the platform data elements that cannot be parsed
 701  * from the device tree by the drivers (example: function pointers) are
 702  * supplied. But it should be noted that this is a temporary mechanism and
 703  * at some point, the drivers should be capable of parsing all the platform
 704  * data from the device tree.
 705  */
 706 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 707         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 708                                 "exynos4210-uart.0", NULL),
 709         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 710                                 "exynos4210-uart.1", NULL),
 711         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 712                                 "exynos4210-uart.2", NULL),
 713         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 714                                 "exynos4210-uart.3", NULL),
 715         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 716                                 "s3c2440-i2c.0", NULL),
 717         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 718                                 "s3c2440-i2c.1", NULL),
 719         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 720                                 "s3c2440-i2c.2", NULL),
 721         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 722                                 "s3c2440-i2c.3", NULL),
 723         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 724                                 "s3c2440-i2c.4", NULL),
 725         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 726                                 "s3c2440-i2c.5", NULL),
 727         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 728                                 "s3c2440-i2c.6", NULL),
 729         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 730                                 "s3c2440-i2c.7", NULL),
 731         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 732                                 "s3c2440-hdmiphy-i2c", NULL),
 733         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 734                                 "exynos4210-spi.0", NULL),
 735         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 736                                 "exynos4210-spi.1", NULL),
 737         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 738                                 "exynos4210-spi.2", NULL),
 739         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 740                                 "dw_mmc.0", NULL),
 741         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 742                                 "dw_mmc.1", NULL),
 743         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 744                                 "dw_mmc.2", NULL),
 745         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 746                                 "dw_mmc.3", NULL),
 747         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 748         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 749         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 750         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 751                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 752         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 753                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 754         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 755                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 756         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 757                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 758         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 759                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 760         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 761                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 762         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 763                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 764         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 765                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 766         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 767                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 768         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 769                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 770         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 771                                 "s5p-mipi-dsim", &dsim_platform_data),
 772         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 773                                 "s5p-dp", &smdk5250_dp_data),
 774         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 775         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 776                                 "exynos-gsc.0", NULL),
 777         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 778                                 "exynos-gsc.1", NULL),
 779         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 780                                 "exynos-gsc.2", NULL),
 781         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 782                                 "exynos-gsc.3", NULL),
 783 #ifdef CONFIG_VIDEO_FIMG2D4X
 784         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 785                                 "s5p-g2d", &fimg2d_data),
 786 #endif
 787         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 788                                 "exynos-ohci", &smdk5250_ohci_pdata),
 789         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 790                                 "s5p-ehci", &smdk5250_ehci_pdata),
 791         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 792                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 793         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 794                                 "samsung-i2s.0", &i2sv5_pdata),
 795 #ifdef CONFIG_DRM_EXYNOS_HDMI
 796         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 797                                 "exynos5-hdmi", &drm_hdmi_pdata),
 798         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 799                                 "s5p-mixer", &drm_mixer_pdata),
 800 #else
 801         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 802                                 "exynos5-hdmi", NULL),
 803         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 804                                 "s5p-mixer", NULL),
 805 #endif
 806         {},
 807 };
 808
 809 static struct platform_device *smdk5250_devices[] __initdata = {
 810         &exynos5_device_adc,
 811         &smdk5250_lcd, /* for platform_lcd device */
 812         &exynos_device_md0, /* for media device framework */
 813         &exynos_device_md1, /* for media device framework */
 814         &exynos_device_md2, /* for media device framework */
 815         &samsung_asoc_dma,  /* for audio dma interface device */
 816         &exynos_drm_device,
 817 #ifdef CONFIG_DRM_EXYNOS_HDMI
 818         &exynos_drm_hdmi_device,
 819 #endif
 820 };
 821
 822 static struct regulator_consumer_supply dummy_supplies[] = {
 823         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 824         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 825 };
 826
 827 static void __init exynos5250_dt_map_io(void)
 828 {
 829         exynos_init_io(NULL, 0);
 830         s3c24xx_init_clocks(24000000);
 831 }
 832
 833 static unsigned long ramoops_dt_start, ramoops_dt_size;
 834 static int __init init_dt_scan_ramoops(unsigned long node, const char *uname,
 835                                         int depth, void *data)
 836 {
 837         __be32 *reg, *endp;
 838         unsigned long l;
 839
 840         if (!of_flat_dt_is_compatible(node, "ramoops"))
 841                 return 0;
 842
 843         reg = of_get_flat_dt_prop(node, "reg", &l);
 844         if (!reg)
 845                 return 0;
 846         endp = reg + (l / sizeof(__be32));
 847
 848         /* This architecture uses single cells for address and size.
 849          * Other architectures may differ. */
 850         ramoops_dt_start = be32_to_cpu(reg[0]);
 851         ramoops_dt_size = be32_to_cpu(reg[1]);
 852         return 0;
 853 }
 854
 855 static void __init exynos5_ramoops_reserve(void)
 856 {
 857         unsigned long start, size;
 858
 859         of_scan_flat_dt(init_dt_scan_ramoops, NULL);
 860
 861         /* If necessary, lower start and raise size to align to 1M. */
 862         start = round_down(ramoops_dt_start, SZ_1M);
 863         size = ramoops_dt_size + ramoops_dt_start - start;
 864         size = round_up(size, SZ_1M);
 865
 866         if (memblock_remove(start, size)) {
 867                 pr_err("Failed to remove ramoops %08lx@%08lx from memory\n",
 868                         size, start);
 869         } else {
 870                 pr_info("Ramoops: %08lx - %08lx\n", start, start + size - 1);
 871         }
 872 }
 873
 874 static void __init exynos5_reserve(void)
 875 {
 876         /* required to have enough address range to remap the IOMMU
 877          * allocated buffers */
 878         init_consistent_dma_size(SZ_64M);
 879
 880         exynos5_ramoops_reserve();
 881 }
 882
 883 static void s5p_tv_setup(void)
 884 {
 885         /* direct HPD to HDMI chip */
 886         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 887
 888         gpio_direction_input(EXYNOS5_GPX3(7));
 889         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 890         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 891 }
 892
 893 static void exynos5_i2c_setup(void)
 894 {
 895         /* Setup the low-speed i2c controller interrupts */
 896         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 897 }
 898
 899 static void __init exynos5250_dt_machine_init(void)
 900 {
 901         struct device_node *srom_np, *np;
 902         int ret,i;
 903
 904         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 905
 906         /* Setup pins for any SMSC 911x controller on the SROMC bus */
 907         srom_np = of_find_node_by_path("/sromc-bus");
 908         if (!srom_np) {
 909                 printk(KERN_ERR "No /sromc-bus property.\n");
 910                 goto out;
 911         }
 912         for_each_child_of_node(srom_np, np) {
 913                 if (of_device_is_compatible(np, "smsc,lan9115")) {
 914                         u32 reg;
 915                         of_property_read_u32(np, "reg", &reg);
 916                         smsc911x_init(reg);
 917                 }
 918         }
 919
 920         /*
 921          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 922          * TODO: Fix this so we are not at risk of requesting the GPIO
 923          * multiple times, this should be done with device tree, and
 924          * likely integrated into the plat-samsung/dev-backlight.c init.
 925          */
 926         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_HIGH, "lcd_bl_en");
 927
 928         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 929
 930         /*
 931          * HACK ALERT! TODO: FIXME!
 932          *
 933          * We're going to hack in Daisy LCD info here for bringup purposes.
 934          * Lots of things wrong with what we're doing here, but it works for
 935          * bringup purposes.
 936          */
 937
 938         if (of_machine_is_compatible("google,daisy")) {
 939 #ifdef CONFIG_DRM_EXYNOS_FIMD
 940                 smdk5250_lcd1_pdata.panel[0].timing.xres = 1366;
 941                 smdk5250_lcd1_pdata.panel[0].timing.yres = 768;
 942                 smdk5250_lcd1_pdata.panel[1].timing.xres = 1280;
 943                 smdk5250_lcd1_pdata.panel[1].timing.yres = 720;
 944                 smdk5250_lcd1_pdata.panel[2].timing.xres = -1;
 945                 smdk5250_lcd1_pdata.panel[2].timing.yres = -1;
 946                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
 947 #else
 948                 smdk5250_fb_win0.win_mode.xres = 1366;
 949                 smdk5250_fb_win0.win_mode.yres = 768;
 950                 smdk5250_fb_win0.virtual_x = 1366;
 951                 smdk5250_fb_win0.virtual_y = 768 * 2;
 952
 953                 smdk5250_fb_win1.win_mode.xres = 1366;
 954                 smdk5250_fb_win1.win_mode.yres = 768;
 955                 smdk5250_fb_win1.virtual_x = 1366;
 956                 smdk5250_fb_win1.virtual_y = 768 * 2;
 957
 958                 smdk5250_fb_win2.win_mode.xres = 1366;
 959                 smdk5250_fb_win2.win_mode.yres = 768;
 960                 smdk5250_fb_win2.virtual_x = 1366;
 961                 smdk5250_fb_win2.virtual_y = 768 * 2;
 962 #endif
 963                 dsim_lcd_info.lcd_size.width = 1366;
 964                 dsim_lcd_info.lcd_size.height = 768;
 965         } else if (of_machine_is_compatible("google,snow")) {
 966                 int pd_n_gpio, rst_n_gpio;
 967 #ifdef CONFIG_DRM_EXYNOS_FIMD
 968                 for (i = 0;i < ARRAY_SIZE(snow_fb_window);i++)
 969                         smdk5250_lcd1_pdata.panel[i].timing = snow_fb_window[i];
 970
 971                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
 972                 smdk5250_lcd1_pdata.clock_rate = 267 * 1000 * 1000;
 973                 smdk5250_lcd1_pdata.vidcon1 = 0;
 974 #endif
 975
 976                 get_dp_bridge_gpios(&pd_n_gpio, &rst_n_gpio);
 977                 if (pd_n_gpio >= 0) {
 978                         ret = gpio_request_one(pd_n_gpio, GPIOF_OUT_INIT_HIGH,
 979                                                 "DP_PD_N");
 980                         WARN_ON(ret);
 981                 }
 982                 if (rst_n_gpio >= 0) {
 983                         ret = gpio_request_one(rst_n_gpio, GPIOF_OUT_INIT_HIGH,
 984                                                 "DP_RST_N");
 985                         WARN_ON(ret);
 986                 }
 987         }
 988
 989         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 990                 "HOST_VBUS_CONTROL")) {
 991                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 992         } else {
 993                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 994                 gpio_free(EXYNOS5_GPX2(6));
 995         }
 996
 997         exynos5_i2c_setup();
 998
 999         /*
1000          * MAX77686 PMIC interrupt setup code
1001          * TODO: Convert the device tree wakeup_int domain to support
1002          * pull-up flags
1003          */
1004         s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_NONE);
1005
1006         /*
1007          * BIG HACK: The wm8994 is not device tree enabled apparently, so
1008          * needs to be added manually.  ...but it's only on SMDK5250.
1009          */
1010         if (of_machine_is_compatible("samsung,smdk5250")) {
1011                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
1012         }
1013
1014         /* XCLKOUT needs to be moved over to the clock interface, but enable it
1015          * here for now.
1016          */
1017         enable_xclkout();
1018
1019         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
1020                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
1021         } else {
1022                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
1023                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
1024                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
1025                 spi_register_board_info(spi1_board_info,
1026                                         ARRAY_SIZE(spi1_board_info));
1027         }
1028
1029         of_platform_populate(NULL, of_default_bus_match_table,
1030                                 exynos5250_auxdata_lookup, NULL);
1031
1032 #ifdef CONFIG_DRM_EXYNOS_FIMD
1033         if (of_machine_is_compatible("google,snow"))
1034                 exynos_dp_gpio_setup_24bpp();
1035         else
1036                 exynos_fimd_gpio_setup_24bpp();
1037 #endif
1038         s5p_tv_setup();
1039
1040         /* Enable power to ADC */
1041         __raw_writel(0x1, S5P_ADC_PHY_CONTROL);
1042
1043         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
1044 out:
1045         of_node_put(srom_np);
1046         return;
1047 }
1048
1049 static char const *exynos5250_dt_compat[] __initdata = {
1050         "samsung,exynos5250",
1051         NULL
1052 };
1053
1054 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
1055         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1056         .init_irq       = exynos5_init_irq,
1057         .reserve        = exynos5_reserve,
1058         .map_io         = exynos5250_dt_map_io,
1059         .handle_irq     = gic_handle_irq,
1060         .init_machine   = exynos5250_dt_machine_init,
1061         .timer          = &exynos4_timer,
1062         .dt_compat      = exynos5250_dt_compat,
1063         .restart        = exynos5_restart,
1064 MACHINE_END