arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/platform_data/dwc3-exynos.h>
  16 #include <linux/regulator/fixed.h>
  17 #include <linux/regulator/machine.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/smsc911x.h>
  20 #include <linux/delay.h>
  21 #include <linux/i2c.h>
  22 #include <linux/pwm_backlight.h>
  23 #include <linux/mfd/wm8994/pdata.h>
  24 #include <linux/regulator/machine.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/memblock.h>
  27 #include <linux/of_fdt.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_data/ntc_thermistor.h>
  30
  31 #include <asm/mach/arch.h>
  32 #include <asm/hardware/gic.h>
  33 #include <mach/map.h>
  34 #include <mach/ppmu.h>
  35 #include <mach/dev.h>
  36 #include <mach/ohci.h>
  37 #include <mach/regs-pmu.h>
  38 #include <mach/sysmmu.h>
  39 #include <mach/ohci.h>
  40 #include <mach/regs-audss.h>
  41 #include <mach/regs-pmu.h>
  42
  43 #include <plat/audio.h>
  44 #include <plat/adc.h>   /* for s3c_adc_register and friends */
  45 #include <plat/cpu.h>
  46 #include <plat/dsim.h>
  47 #include <plat/fb.h>
  48 #include <plat/mipi_dsi.h>
  49 #include <plat/gpio-cfg.h>
  50 #include <plat/regs-fb.h>
  51 #include <plat/regs-serial.h>
  52 #include <plat/regs-srom.h>
  53 #include <plat/backlight.h>
  54 #include <plat/devs.h>
  55 #include <plat/usb-phy.h>
  56 #include <plat/ehci.h>
  57 #include <plat/dp.h>
  58 #include <plat/s3c64xx-spi.h>
  59
  60 #include <video/platform_lcd.h>
  61
  62 #include "drm/exynos_drm.h"
  63 #include "common.h"
  64
  65 static void __init smsc911x_init(int ncs)
  66 {
  67         u32 data;
  68
  69         /* configure nCS1 width to 16 bits */
  70         data = __raw_readl(S5P_SROM_BW) &
  71                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  72         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  73                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  74                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  75         __raw_writel(data, S5P_SROM_BW);
  76
  77         /* set timing for nCS1 suitable for ethernet chip */
  78         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  79                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  80                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  81                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  82                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  83                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  84                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  85                 S5P_SROM_BC0 + (ncs * 4));
  86 }
  87
  88 #ifndef CONFIG_DRM_EXYNOS_FIMD
  89 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  90         .win_mode = {
  91                 .left_margin    = 4,
  92                 .right_margin   = 4,
  93                 .upper_margin   = 4,
  94                 .lower_margin   = 4,
  95                 .hsync_len      = 4,
  96                 .vsync_len      = 4,
  97                 .xres           = 1280,
  98                 .yres           = 800,
  99         },
 100         .virtual_x              = 1280,
 101         .virtual_y              = 800 * 2,
 102         .width                  = 223,
 103         .height                 = 125,
 104         .max_bpp                = 32,
 105         .default_bpp            = 24,
 106 };
 107
 108 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
 109         .win_mode = {
 110                 .left_margin    = 4,
 111                 .right_margin   = 4,
 112                 .upper_margin   = 4,
 113                 .lower_margin   = 4,
 114                 .hsync_len      = 4,
 115                 .vsync_len      = 4,
 116                 .xres           = 1280,
 117                 .yres           = 800,
 118         },
 119         .virtual_x              = 1280,
 120         .virtual_y              = 800 * 2,
 121         .width                  = 223,
 122         .height                 = 125,
 123         .max_bpp                = 32,
 124         .default_bpp            = 24,
 125 };
 126
 127 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 128         .win_mode = {
 129                 .left_margin    = 0x4,
 130                 .right_margin   = 0x4,
 131                 .upper_margin   = 4,
 132                 .lower_margin   = 4,
 133                 .hsync_len      = 4,
 134                 .vsync_len      = 4,
 135                 .xres           = 1280,
 136                 .yres           = 800,
 137         },
 138         .virtual_x              = 1280,
 139         .virtual_y              = 800 * 2,
 140         .width                  = 223,
 141         .height                 = 125,
 142         .max_bpp                = 32,
 143         .default_bpp            = 24,
 144 };
 145 #endif
 146
 147 /*
 148  * - 70000000. / ((1366 + 34 + 34 + 32) * (768 + 10 + 12 + 6))
 149  *   59.98615176839176
 150  */
 151 static struct fb_videomode snow_fb_window[] = {
 152         {
 153                 .left_margin    = 34,
 154                 .right_margin   = 34,
 155                 .upper_margin   = 10,
 156                 .lower_margin   = 12,
 157                 .hsync_len      = 32,
 158                 .vsync_len      = 6,
 159                 .xres           = 1366,
 160                 .yres           = 768,
 161         }, {
 162                 .xres           = -1,
 163                 .yres           = -1,
 164         },
 165 };
 166
 167 static void exynos_fimd_gpio_setup_24bpp(void)
 168 {
 169         unsigned int reg = 0;
 170
 171         /*
 172          * Set DISP1BLK_CFG register for Display path selection
 173          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 174          * ---------------------
 175          * 0 | MIE/MDNIE
 176          * 1 | FIMD : selected
 177          */
 178         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 179         reg &= ~(1 << 15);      /* To save other reset values */
 180         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 181 }
 182
 183 static void exynos_dp_gpio_setup_24bpp(void)
 184 {
 185         exynos_fimd_gpio_setup_24bpp();
 186
 187         /* Set Hotplug detect for DP */
 188         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 189         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 190 }
 191
 192 #ifdef CONFIG_DRM_EXYNOS_HDMI
 193 static struct platform_device exynos_drm_hdmi_device = {
 194         .name           = "exynos-drm-hdmi",
 195 };
 196
 197 static struct exynos_drm_hdmi_pdata drm_mixer_pdata = {
 198         .timing = {
 199                 .xres    = 1920,
 200                 .yres    = 1080,
 201                 .refresh = 60,
 202         },
 203         .default_win    = 0,
 204         .bpp            = 32,
 205         .is_v13         = 0,
 206         .is_soc_exynos5 = 1,
 207 };
 208
 209 static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = {
 210         .timing = {
 211                 .xres    = 1920,
 212                 .yres    = 1080,
 213                 .refresh    = 60,
 214         },
 215         .default_win    = 0,
 216         .bpp            = 32,
 217         .is_v13         = 0,
 218         .is_soc_exynos5 = 1,
 219 };
 220 #endif
 221
 222 #ifdef CONFIG_DRM_EXYNOS_FIMD
 223 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 224         .panel[0].timing   = {
 225                 .xres           = 1280,
 226                 .yres           = 800,
 227                 .hsync_len      = 4,
 228                 .left_margin    = 0x4,
 229                 .right_margin   = 0x4,
 230                 .vsync_len      = 4,
 231                 .upper_margin   = 4,
 232                 .lower_margin   = 4,
 233                 .refresh        = 60,
 234         },
 235         .panel[1].timing   = {
 236                 .xres           = 1280,
 237                 .yres           = 720,
 238                 .hsync_len      = 4,
 239                 .left_margin    = 0x4,
 240                 .right_margin   = 0x4,
 241                 .vsync_len      = 4,
 242                 .upper_margin   = 4,
 243                 .lower_margin   = 4,
 244                 .refresh        = 60,
 245         },
 246         .panel[2].timing   = {
 247                 .xres           = -1,
 248                 .yres           = -1,
 249         },
 250         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 251         .vidcon1        = VIDCON1_INV_VCLK,
 252         .default_win    = 0,
 253         .bpp            = 32,
 254         .clock_rate     = 800 * 1000 * 1000,
 255 };
 256 #else
 257 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 258         .win[0]         = &smdk5250_fb_win0,
 259         .win[1]         = &smdk5250_fb_win1,
 260         .win[2]         = &smdk5250_fb_win2,
 261         .default_win    = 0,
 262         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 263         .vidcon1        = VIDCON1_INV_VCLK,
 264         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 265         .clock_rate     = 800 * 1000 * 1000,
 266 };
 267 #endif
 268
 269 static struct mipi_dsim_config dsim_info = {
 270         .e_interface            = DSIM_VIDEO,
 271         .e_pixel_format         = DSIM_24BPP_888,
 272         /* main frame fifo auto flush at VSYNC pulse */
 273         .auto_flush             = false,
 274         .eot_disable            = false,
 275         .auto_vertical_cnt      = false,
 276         .hse                    = false,
 277         .hfp                    = false,
 278         .hbp                    = false,
 279         .hsa                    = false,
 280
 281         .e_no_data_lane         = DSIM_DATA_LANE_4,
 282         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 283         .e_burst_mode           = DSIM_BURST,
 284
 285         .p                      = 3,
 286         .m                      = 115,
 287         .s                      = 1,
 288
 289         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 290         .pll_stable_time        = 500,
 291
 292         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 293
 294         /* stop state holding counter after bta change count 0 ~ 0xfff */
 295         .stop_holding_cnt       = 0x0f,
 296         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 297         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 298
 299         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 300 };
 301
 302 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 303         .rgb_timing.left_margin         = 0x4,
 304         .rgb_timing.right_margin        = 0x4,
 305         .rgb_timing.upper_margin        = 0x4,
 306         .rgb_timing.lower_margin        =  0x4,
 307         .rgb_timing.hsync_len           = 0x4,
 308         .rgb_timing.vsync_len           = 0x4,
 309         .cpu_timing.cs_setup            = 0,
 310         .cpu_timing.wr_setup            = 1,
 311         .cpu_timing.wr_act              = 0,
 312         .cpu_timing.wr_hold             = 0,
 313         .lcd_size.width                 = 1280,
 314         .lcd_size.height                = 800,
 315 };
 316
 317 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 318         .clk_name               = "dsim0",
 319         .dsim_config            = &dsim_info,
 320         .dsim_lcd_config        = &dsim_lcd_info,
 321
 322         .part_reset             = s5p_dsim_part_reset,
 323         .init_d_phy             = s5p_dsim_init_d_phy,
 324         .get_fb_frame_done      = NULL,
 325         .trigger                = NULL,
 326
 327         /*
 328          * the stable time of needing to write data on SFR
 329          * when the mipi mode becomes LP mode.
 330          */
 331         .delay_for_stabilization = 600,
 332 };
 333
 334 static struct platform_device exynos_drm_device = {
 335         .name           = "exynos-drm",
 336         .dev = {
 337                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 338                 .coherent_dma_mask = 0xffffffffUL,
 339         }
 340 };
 341
 342 static void exynos_wifi_bt_set_power(u32, u32); /* TODO(sleffler) hack */
 343
 344 static void lcd_set_power(struct plat_lcd_data *pd,
 345                         unsigned int power)
 346 {
 347         if (of_machine_is_compatible("google,daisy") ||
 348                         of_machine_is_compatible("google,snow")) {
 349                 struct regulator *lcd_fet;
 350
 351                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 352                 if (!IS_ERR(lcd_fet)) {
 353                         if (power)
 354                                 regulator_enable(lcd_fet);
 355                         else
 356                                 regulator_disable(lcd_fet);
 357
 358                         regulator_put(lcd_fet);
 359                 }
 360         }
 361
 362         if (!of_machine_is_compatible("google,snow")) {
 363                 /* reset */
 364                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 365                 mdelay(20);
 366                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 367                 mdelay(20);
 368                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 369                 mdelay(20);
 370                 gpio_free(EXYNOS5_GPX1(5));
 371                 mdelay(20);
 372         }
 373
 374
 375         /* Turn on regulator for backlight */
 376         if (of_machine_is_compatible("google,daisy") ||
 377                         of_machine_is_compatible("google,snow")) {
 378                 struct regulator *backlight_fet;
 379
 380                 backlight_fet = regulator_get(NULL, "vcd_led");
 381                 if (!IS_ERR(backlight_fet)) {
 382                         if (power)
 383                                 regulator_enable(backlight_fet);
 384                         else
 385                                 regulator_disable(backlight_fet);
 386
 387                         regulator_put(backlight_fet);
 388                 }
 389                 /* Wait 10 ms between regulator on and PWM start per spec */
 390                 mdelay(10);
 391         }
 392         exynos_wifi_bt_set_power(0, power);     /* TODO(sleffler) hack */
 393 }
 394
 395 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 396 {
 397         /* Don't call .set_power callback while unblanking */
 398         return 0;
 399 }
 400
 401 static struct plat_lcd_data smdk5250_lcd_data = {
 402         .set_power      = lcd_set_power,
 403         .match_fb       = smdk5250_match_fb,
 404 };
 405
 406 static struct platform_device smdk5250_lcd = {
 407         .name                   = "platform-lcd",
 408         .dev.platform_data      = &smdk5250_lcd_data,
 409 };
 410
 411 static int smdk5250_bl_notify(struct device *unused, int brightness)
 412 {
 413         /* manage lcd_bl_en signal */
 414         if (brightness)
 415                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 416         else
 417                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 418
 419         return brightness;
 420 }
 421
 422 /* LCD Backlight data */
 423 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 424         .no     = EXYNOS5_GPB2(0),
 425         .func   = S3C_GPIO_SFN(2),
 426 };
 427
 428 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 429         .pwm_period_ns  = 1000000,
 430         .notify         = smdk5250_bl_notify,
 431 };
 432
 433 struct platform_device exynos_device_md0 = {
 434         .name = "exynos-mdev",
 435         .id = 0,
 436 };
 437
 438 struct platform_device exynos_device_md1 = {
 439         .name = "exynos-mdev",
 440         .id = 1,
 441 };
 442
 443 struct platform_device exynos_device_md2 = {
 444         .name = "exynos-mdev",
 445         .id = 2,
 446 };
 447
 448 static struct regulator_consumer_supply wm8994_avdd1_supply =
 449         REGULATOR_SUPPLY("AVDD1", "1-001a");
 450
 451 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 452         REGULATOR_SUPPLY("DCVDD", "1-001a");
 453
 454 static struct regulator_init_data wm8994_ldo1_data = {
 455         .constraints    = {
 456                 .name           = "AVDD1",
 457         },
 458         .num_consumer_supplies  = 1,
 459         .consumer_supplies      = &wm8994_avdd1_supply,
 460 };
 461
 462 static struct regulator_init_data wm8994_ldo2_data = {
 463         .constraints    = {
 464         .name                   = "DCVDD",
 465                 },
 466         .num_consumer_supplies  = 1,
 467         .consumer_supplies      = &wm8994_dcvdd_supply,
 468 };
 469
 470 static struct wm8994_pdata wm8994_platform_data = {
 471         /* configure gpio1 function: 0x0001(Logic level input/output) */
 472         .gpio_defaults[0] = 0x0001,
 473         /* If the i2s0 and i2s2 is enabled simultaneously */
 474         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 475         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 476         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 477         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 478         .ldo[0] = { 0, &wm8994_ldo1_data },
 479         .ldo[1] = { 0, &wm8994_ldo2_data },
 480 };
 481
 482 static struct i2c_board_info i2c_devs1[] __initdata = {
 483         {
 484                 I2C_BOARD_INFO("wm8994", 0x1a),
 485                 .platform_data  = &wm8994_platform_data,
 486         },
 487 };
 488
 489 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 490         [0] = {
 491                 .line           = EXYNOS5_GPA2(5),
 492                 .fb_delay       = 0x2,
 493         },
 494 };
 495
 496 static struct spi_board_info spi1_board_info[] __initdata = {
 497         {
 498                 .modalias               = "spidev",
 499                 .platform_data          = NULL,
 500                 .max_speed_hz           = 10*1000*1000,
 501                 .bus_num                = 1,
 502                 .chip_select            = 0,
 503                 .mode                   = SPI_MODE_0,
 504                 .controller_data        = spi1_csi,
 505         }
 506 };
 507
 508 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 509         .dbgname = "mfc_l",
 510         .clockname = "sysmmu",
 511 };
 512
 513 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 514         .dbgname = "mfc_r",
 515         .clockname = "sysmmu",
 516 };
 517
 518 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 519         .dbgname = "gsc",
 520         .clockname = "sysmmu",
 521 };
 522
 523 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 524         .dbgname = "g2d",
 525         .clockname = "sysmmu",
 526 };
 527
 528 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 529         .dbgname = "fimd",
 530         .clockname = "sysmmu",
 531 };
 532
 533 struct sysmmu_platform_data platdata_sysmmu_tv = {
 534         .dbgname = "tv",
 535         .clockname = "sysmmu",
 536 };
 537
 538 #ifdef CONFIG_VIDEO_FIMG2D4X
 539 static struct fimg2d_platdata fimg2d_data __initdata = {
 540         .hw_ver         = 0x42,
 541         .gate_clkname   = "fimg2d",
 542 };
 543 #endif
 544
 545 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 546         .phy_init = s5p_usb_phy_init,
 547         .phy_exit = s5p_usb_phy_exit,
 548 };
 549
 550 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 551         .phy_init = s5p_usb_phy_init,
 552         .phy_exit = s5p_usb_phy_exit,
 553 };
 554
 555 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 556         .phy_type = S5P_USB_PHY_DRD,
 557         .phy_init = s5p_usb_phy_init,
 558         .phy_exit = s5p_usb_phy_exit,
 559         .phyclk_switch = exynos5_dwc_phyclk_switch,
 560 };
 561
 562 struct exynos_gpio_cfg {
 563         unsigned int    addr;
 564         unsigned int    num;
 565         unsigned int    bit;
 566 };
 567
 568 static const char *rclksrc[] = {
 569         [0] = "busclk",
 570         [1] = "i2sclk",
 571 };
 572
 573 static struct video_info smdk5250_dp_config = {
 574         .name                   = "eDP-LVDS NXP PTN3460",
 575
 576         .h_sync_polarity        = 0,
 577         .v_sync_polarity        = 0,
 578         .interlaced             = 0,
 579
 580         .color_space            = COLOR_RGB,
 581         .dynamic_range          = VESA,
 582         .ycbcr_coeff            = COLOR_YCBCR601,
 583         .color_depth            = COLOR_8,
 584
 585         .link_rate              = LINK_RATE_2_70GBPS,
 586         .lane_count             = LANE_COUNT2,
 587 };
 588
 589 static struct exynos_dp_platdata smdk5250_dp_data = {
 590         .video_info     = &smdk5250_dp_config,
 591         .training_type  = SW_LINK_TRAINING,
 592         .phy_init       = s5p_dp_phy_init,
 593         .phy_exit       = s5p_dp_phy_exit,
 594 };
 595
 596 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 597 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 598 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 599 /* Mask bit[12:8] for xxti clock selection */
 600 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 601
 602 static void __init enable_xclkout(void)
 603 {
 604        unsigned int tmp;
 605
 606        tmp = readl(S5P_PMU_DEBUG);
 607        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 608        tmp |= PMU_DEBUG_XXTI;
 609        writel(tmp, S5P_PMU_DEBUG);
 610 }
 611
 612 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 613 {
 614         int id;
 615         /* configure GPIO for i2s port */
 616         struct exynos_gpio_cfg exynos5_cfg[3] = {
 617                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 618                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 619                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 620         };
 621
 622         if (pdev->dev.of_node) {
 623                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 624                 if (id < 0)
 625                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 626         } else {
 627                 id = pdev->id;
 628         }
 629
 630         if (id < 0 || id > 2) {
 631                 printk(KERN_ERR "Invalid Device %d\n", id);
 632                 return -EINVAL;
 633         }
 634
 635         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 636                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 637
 638         return 0;
 639 }
 640
 641 static struct s3c_audio_pdata i2sv5_pdata = {
 642         .cfg_gpio = exynos_cfg_i2s_gpio,
 643         .type = {
 644                 .i2s = {
 645                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 646                                          | QUIRK_NEED_RSTCLR,
 647                         .src_clk = rclksrc,
 648                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 649                 },
 650         },
 651 };
 652
 653 /*
 654  * Hack to do power-on sequence after the 32khz SLP_CLK is
 655  * running as doing this entirely in the DT is problematic.
 656  * We attach an auxdata record to dw_mmc2 with a set_power
 657  * method that frobs the regulators.  This work is not board
 658  * specific but must be done before the device is recognized
 659  * so cannot go in the driver.
 660  */
 661 static bool enable_mwi87xx(void)
 662 {
 663         struct regulator *wifi_en, *wifi_rst;
 664         bool ok;
 665
 666         wifi_en = regulator_get(NULL, "wifi-en");
 667         wifi_rst = regulator_get(NULL, "wifi-rst-l");
 668         ok = !IS_ERR(wifi_en) && !IS_ERR(wifi_rst);
 669         if (ok) {
 670                 /*
 671                  * This assumes SLP_CLK is enabled and stable by the
 672                  * time we get here.  Also any delay required between
 673                  * RESETn and PDn should be set in startup-delay-us
 674                  * in the DT.
 675                  */
 676                 regulator_enable(wifi_rst);
 677                 regulator_enable(wifi_en);
 678         }
 679
 680         if (!IS_ERR(wifi_rst))
 681                 regulator_put(wifi_rst);
 682         if (!IS_ERR(wifi_en))
 683                 regulator_put(wifi_en);
 684         return ok;
 685 }
 686
 687 static void exynos_wifi_bt_set_power(u32 slot_id, u32 volt)
 688 {
 689         if (volt == 0 || (!of_machine_is_compatible("google,snow") &&
 690                           !of_machine_is_compatible("google,daisy")))
 691                 return;
 692         if (!enable_mwi87xx())
 693                 pr_err("%s: problem enabling WiFi+BT\n", __func__);
 694         /* NB: bt-reset-l is tied to wifi-rst-l so BT should be ready too */
 695 }
 696
 697
 698 /* NTC Thermistor. Attached to S3C-ADC in some Samsung SoC Devices */
 699 struct s3c_adc_client *ntc_adc_clients[4];
 700 struct mutex ntc_adc_locks[] = {
 701         __MUTEX_INITIALIZER(ntc_adc_locks[0]),
 702         __MUTEX_INITIALIZER(ntc_adc_locks[1]),
 703         __MUTEX_INITIALIZER(ntc_adc_locks[2]),
 704         __MUTEX_INITIALIZER(ntc_adc_locks[3]),
 705 };
 706
 707 static int __init s3c_adc_ntc_init(struct platform_device *pdev)
 708 {
 709         struct s3c_adc_client *ntc_adc_client;
 710
 711         ntc_adc_client = s3c_adc_register(pdev, NULL, NULL, 0);
 712         if (IS_ERR(ntc_adc_client))
 713                 return PTR_ERR(ntc_adc_client);
 714
 715         ntc_adc_clients[pdev->id] = ntc_adc_client;
 716
 717         return 0;
 718 }
 719
 720 /*
 721  * read_thermistor_uV: is a call back from ntc_thermistor driver.
 722  * returns the temperature of the thermistor in celsius
 723  */
 724 static int read_thermistor_uV(struct platform_device *pdev)
 725 {
 726         static unsigned int ntc_adc_ports[] = {3, 4, 5, 6};
 727         s64 converted;
 728         unsigned int port = ntc_adc_ports[pdev->id];
 729         struct s3c_adc_client *client = ntc_adc_clients[pdev->id];
 730         struct ntc_thermistor_platform_data *pdata = pdev->dev.platform_data;
 731         struct mutex *lock = ntc_adc_locks + pdev->id;
 732         int ret;
 733
 734         /* Arrays are sized; make sure we haven't blown over */
 735         BUG_ON(pdev->id >= ARRAY_SIZE(ntc_adc_locks));
 736
 737         /*
 738          * s3c_adc_read() assumes two processes aren't using the same client
 739          * at the same time (yes, it's a bad design), so grab a per-client
 740          * mutex to ensure this is OK.
 741          */
 742         mutex_lock(lock);
 743         ret = s3c_adc_read(client, port);
 744         mutex_unlock(lock);
 745
 746         if (ret < 0) {
 747                 dev_warn(&pdev->dev, "Thermistor read err: 0x%08x\n", ret);
 748                 return ret;
 749         }
 750
 751         converted = pdata->pullup_uV * (s64) ret;
 752         converted >>= 12;
 753
 754         return (int) converted;
 755 }
 756
 757 static struct ntc_thermistor_platform_data ntc_adc_pdata = {
 758         .read_uV        = read_thermistor_uV,
 759         .pullup_uV      = 1800000, /* voltage of vdd for ADC */
 760         .pullup_ohm     = 47000,
 761         .pulldown_ohm   = 0,
 762         .connect        = NTC_CONNECTED_GROUND,
 763 };
 764
 765 struct platform_device s3c_device_adc_ntc_thermistor0 = {
 766         .name                   = "ncp15wb473",
 767         .id                     = 0,
 768         .dev                    = {
 769                 .platform_data = &ntc_adc_pdata,
 770         },
 771 };
 772
 773 struct platform_device s3c_device_adc_ntc_thermistor1 = {
 774         .name                   = "ncp15wb473",
 775         .id                     = 1,
 776         .dev                    = {
 777         .platform_data = &ntc_adc_pdata,
 778         },
 779 };
 780
 781 struct platform_device s3c_device_adc_ntc_thermistor2 = {
 782         .name                   = "ncp15wb473",
 783         .id                     = 2,
 784         .dev                    = {
 785                 .platform_data = &ntc_adc_pdata,
 786         },
 787 };
 788
 789 struct platform_device s3c_device_adc_ntc_thermistor3 = {
 790         .name                   = "ncp15wb473",
 791         .id                     = 3,
 792         .dev                    = {
 793                 .platform_data = &ntc_adc_pdata,
 794         },
 795 };
 796
 797 /*
 798  * The following lookup table is used to override device names when devices
 799  * are registered from device tree. This is temporarily added to enable
 800  * device tree support addition for the EXYNOS5 architecture.
 801  *
 802  * For drivers that require platform data to be provided from the machine
 803  * file, a platform data pointer can also be supplied along with the
 804  * devices names. Usually, the platform data elements that cannot be parsed
 805  * from the device tree by the drivers (example: function pointers) are
 806  * supplied. But it should be noted that this is a temporary mechanism and
 807  * at some point, the drivers should be capable of parsing all the platform
 808  * data from the device tree.
 809  */
 810 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 811         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 812                                 "exynos4210-uart.0", NULL),
 813         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 814                                 "exynos4210-uart.1", NULL),
 815         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 816                                 "exynos4210-uart.2", NULL),
 817         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 818                                 "exynos4210-uart.3", NULL),
 819         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 820                                 "s3c2440-i2c.0", NULL),
 821         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 822                                 "s3c2440-i2c.1", NULL),
 823         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 824                                 "s3c2440-i2c.2", NULL),
 825         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 826                                 "s3c2440-i2c.3", NULL),
 827         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 828                                 "s3c2440-i2c.4", NULL),
 829         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 830                                 "s3c2440-i2c.5", NULL),
 831         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 832                                 "s3c2440-i2c.6", NULL),
 833         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 834                                 "s3c2440-i2c.7", NULL),
 835         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 836                                 "s3c2440-hdmiphy-i2c", NULL),
 837         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 838                                 "exynos4210-spi.0", NULL),
 839         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 840                                 "exynos4210-spi.1", NULL),
 841         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 842                                 "exynos4210-spi.2", NULL),
 843         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 844                                 "dw_mmc.0", NULL),
 845         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 846                                 "dw_mmc.1", NULL),
 847         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 848                                 "dw_mmc.2", NULL),
 849         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 850                                 "dw_mmc.3", NULL),
 851         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 852         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 853         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 854         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 855                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 856         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 857                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 858         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 859                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 860         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 861                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 862         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 863                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 864         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 865                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 866         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 867                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 868         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 869                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 870         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 871                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 872         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 873                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 874         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 875                                 "s5p-mipi-dsim", &dsim_platform_data),
 876         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 877                                 "s5p-dp", &smdk5250_dp_data),
 878         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 879         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 880                                 "exynos-gsc.0", NULL),
 881         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 882                                 "exynos-gsc.1", NULL),
 883         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 884                                 "exynos-gsc.2", NULL),
 885         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 886                                 "exynos-gsc.3", NULL),
 887 #ifdef CONFIG_VIDEO_FIMG2D4X
 888         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 889                                 "s5p-g2d", &fimg2d_data),
 890 #endif
 891         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 892                                 "exynos-ohci", &smdk5250_ohci_pdata),
 893         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 894                                 "s5p-ehci", &smdk5250_ehci_pdata),
 895         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 896                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 897         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 898                                 "samsung-i2s.0", &i2sv5_pdata),
 899 #ifdef CONFIG_DRM_EXYNOS_HDMI
 900         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 901                                 "exynos5-hdmi", &drm_hdmi_pdata),
 902         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 903                                 "s5p-mixer", &drm_mixer_pdata),
 904 #else
 905         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 906                                 "exynos5-hdmi", NULL),
 907         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 908                                 "s5p-mixer", NULL),
 909 #endif
 910         {},
 911 };
 912
 913 #ifdef CONFIG_BUSFREQ_OPP
 914 /* BUSFREQ to control memory/bus*/
 915 static struct device_domain busfreq;
 916
 917 static struct platform_device exynos5_busfreq = {
 918         .id = -1,
 919         .name = "exynos-busfreq",
 920 };
 921 #endif
 922
 923 static struct platform_device *smdk5250_devices[] __initdata = {
 924         &smdk5250_lcd, /* for platform_lcd device */
 925         &exynos_device_md0, /* for media device framework */
 926         &exynos_device_md1, /* for media device framework */
 927         &exynos_device_md2, /* for media device framework */
 928         &samsung_asoc_dma,  /* for audio dma interface device */
 929         &exynos_drm_device,
 930 #ifdef CONFIG_DRM_EXYNOS_HDMI
 931         &exynos_drm_hdmi_device,
 932 #endif
 933         &s3c_device_adc_ntc_thermistor0,
 934         &s3c_device_adc_ntc_thermistor1,
 935         &s3c_device_adc_ntc_thermistor2,
 936         &s3c_device_adc_ntc_thermistor3,
 937 #ifdef CONFIG_BUSFREQ_OPP
 938         &exynos5_busfreq,
 939 #endif
 940 };
 941
 942 static struct regulator_consumer_supply dummy_supplies[] = {
 943         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 944         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 945 };
 946
 947 static void __init exynos5250_dt_map_io(void)
 948 {
 949         exynos_init_io(NULL, 0);
 950         s3c24xx_init_clocks(24000000);
 951 }
 952
 953 static unsigned long ramoops_dt_start, ramoops_dt_size;
 954 static int __init init_dt_scan_ramoops(unsigned long node, const char *uname,
 955                                         int depth, void *data)
 956 {
 957         __be32 *reg, *endp;
 958         unsigned long l;
 959
 960         if (!of_flat_dt_is_compatible(node, "ramoops"))
 961                 return 0;
 962
 963         reg = of_get_flat_dt_prop(node, "reg", &l);
 964         if (!reg)
 965                 return 0;
 966         endp = reg + (l / sizeof(__be32));
 967
 968         /* This architecture uses single cells for address and size.
 969          * Other architectures may differ. */
 970         ramoops_dt_start = be32_to_cpu(reg[0]);
 971         ramoops_dt_size = be32_to_cpu(reg[1]);
 972         return 0;
 973 }
 974
 975 static void __init exynos5_ramoops_reserve(void)
 976 {
 977         unsigned long start, size;
 978
 979         of_scan_flat_dt(init_dt_scan_ramoops, NULL);
 980
 981         /* If necessary, lower start and raise size to align to 1M. */
 982         start = round_down(ramoops_dt_start, SZ_1M);
 983         size = ramoops_dt_size + ramoops_dt_start - start;
 984         size = round_up(size, SZ_1M);
 985
 986         if (memblock_remove(start, size)) {
 987                 pr_err("Failed to remove ramoops %08lx@%08lx from memory\n",
 988                         size, start);
 989         } else {
 990                 pr_info("Ramoops: %08lx - %08lx\n", start, start + size - 1);
 991         }
 992 }
 993
 994 static void __init exynos5_reserve(void)
 995 {
 996         /* required to have enough address range to remap the IOMMU
 997          * allocated buffers */
 998         init_consistent_dma_size(SZ_64M);
 999
1000         exynos5_ramoops_reserve();
1001 }
1002
1003 static void s5p_tv_setup(void)
1004 {
1005         /* direct HPD to HDMI chip */
1006         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
1007
1008         gpio_direction_input(EXYNOS5_GPX3(7));
1009         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
1010         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
1011 }
1012
1013 static void exynos5_i2c_setup(void)
1014 {
1015         /* Setup the low-speed i2c controller interrupts */
1016         writel(0x0, EXYNOS5_SYS_I2C_CFG);
1017 }
1018
1019 static void __init exynos5250_dt_machine_init(void)
1020 {
1021         struct device_node *srom_np, *np;
1022         int i;
1023
1024         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1025
1026         /* Setup pins for any SMSC 911x controller on the SROMC bus */
1027         srom_np = of_find_node_by_path("/sromc-bus");
1028         if (!srom_np) {
1029                 printk(KERN_ERR "No /sromc-bus property.\n");
1030                 goto out;
1031         }
1032         for_each_child_of_node(srom_np, np) {
1033                 if (of_device_is_compatible(np, "smsc,lan9115")) {
1034                         u32 reg;
1035                         of_property_read_u32(np, "reg", &reg);
1036                         smsc911x_init(reg);
1037                 }
1038         }
1039
1040         /*
1041          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
1042          * TODO: Fix this so we are not at risk of requesting the GPIO
1043          * multiple times, this should be done with device tree, and
1044          * likely integrated into the plat-samsung/dev-backlight.c init.
1045          */
1046         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_HIGH, "lcd_bl_en");
1047
1048         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
1049
1050         /*
1051          * HACK ALERT! TODO: FIXME!
1052          *
1053          * We're going to hack in Daisy LCD info here for bringup purposes.
1054          * Lots of things wrong with what we're doing here, but it works for
1055          * bringup purposes.
1056          */
1057
1058         if (of_machine_is_compatible("google,daisy")) {
1059 #ifdef CONFIG_DRM_EXYNOS_FIMD
1060                 smdk5250_lcd1_pdata.panel[0].timing.xres = 1366;
1061                 smdk5250_lcd1_pdata.panel[0].timing.yres = 768;
1062                 smdk5250_lcd1_pdata.panel[1].timing.xres = 1280;
1063                 smdk5250_lcd1_pdata.panel[1].timing.yres = 720;
1064                 smdk5250_lcd1_pdata.panel[2].timing.xres = -1;
1065                 smdk5250_lcd1_pdata.panel[2].timing.yres = -1;
1066                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
1067 #else
1068                 smdk5250_fb_win0.win_mode.xres = 1366;
1069                 smdk5250_fb_win0.win_mode.yres = 768;
1070                 smdk5250_fb_win0.virtual_x = 1366;
1071                 smdk5250_fb_win0.virtual_y = 768 * 2;
1072
1073                 smdk5250_fb_win1.win_mode.xres = 1366;
1074                 smdk5250_fb_win1.win_mode.yres = 768;
1075                 smdk5250_fb_win1.virtual_x = 1366;
1076                 smdk5250_fb_win1.virtual_y = 768 * 2;
1077
1078                 smdk5250_fb_win2.win_mode.xres = 1366;
1079                 smdk5250_fb_win2.win_mode.yres = 768;
1080                 smdk5250_fb_win2.virtual_x = 1366;
1081                 smdk5250_fb_win2.virtual_y = 768 * 2;
1082 #endif
1083                 dsim_lcd_info.lcd_size.width = 1366;
1084                 dsim_lcd_info.lcd_size.height = 768;
1085         } else if (of_machine_is_compatible("google,snow")) {
1086 #ifdef CONFIG_DRM_EXYNOS_FIMD
1087                 for (i = 0;i < ARRAY_SIZE(snow_fb_window);i++)
1088                         smdk5250_lcd1_pdata.panel[i].timing = snow_fb_window[i];
1089
1090                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
1091                 smdk5250_lcd1_pdata.clock_rate = 70000000;
1092                 smdk5250_lcd1_pdata.vidcon1 = 0;
1093 #endif
1094         }
1095
1096         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
1097                 "HOST_VBUS_CONTROL")) {
1098                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
1099         } else {
1100                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
1101                 gpio_free(EXYNOS5_GPX2(6));
1102         }
1103
1104         exynos5_i2c_setup();
1105
1106         /*
1107          * MAX77686 PMIC interrupt setup code
1108          * TODO: Convert the device tree wakeup_int domain to support
1109          * pull-up flags
1110          */
1111         s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_NONE);
1112
1113         /*
1114          * BIG HACK: The wm8994 is not device tree enabled apparently, so
1115          * needs to be added manually.  ...but it's only on SMDK5250.
1116          */
1117         if (of_machine_is_compatible("samsung,smdk5250")) {
1118                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
1119         }
1120
1121         /* XCLKOUT needs to be moved over to the clock interface, but enable it
1122          * here for now.
1123          */
1124         enable_xclkout();
1125
1126         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
1127                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
1128         } else {
1129                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
1130                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
1131                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
1132                 spi_register_board_info(spi1_board_info,
1133                                         ARRAY_SIZE(spi1_board_info));
1134         }
1135
1136         of_platform_populate(NULL, of_default_bus_match_table,
1137                                 exynos5250_auxdata_lookup, NULL);
1138
1139 #ifdef CONFIG_DRM_EXYNOS_FIMD
1140         if (of_machine_is_compatible("google,snow"))
1141                 exynos_dp_gpio_setup_24bpp();
1142         else
1143                 exynos_fimd_gpio_setup_24bpp();
1144 #endif
1145         s5p_tv_setup();
1146
1147         /* Enable power to ADC */
1148         __raw_writel(0x1, S5P_ADC_PHY_CONTROL);
1149
1150         s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor0);
1151         s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor1);
1152         s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor2);
1153         s3c_adc_ntc_init(&s3c_device_adc_ntc_thermistor3);
1154
1155 #ifdef CONFIG_BUSFREQ_OPP
1156         dev_add(&busfreq, &exynos5_busfreq.dev);
1157         ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev);
1158         ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev);
1159         ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev);
1160         ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev);
1161         ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev);
1162 #endif
1163         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
1164 out:
1165         of_node_put(srom_np);
1166         return;
1167 }
1168
1169 static char const *exynos5250_dt_compat[] __initdata = {
1170         "samsung,exynos5250",
1171         NULL
1172 };
1173
1174 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
1175         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1176         .init_irq       = exynos5_init_irq,
1177         .reserve        = exynos5_reserve,
1178         .map_io         = exynos5250_dt_map_io,
1179         .handle_irq     = gic_handle_irq,
1180         .init_machine   = exynos5250_dt_machine_init,
1181         .timer          = &exynos4_timer,
1182         .dt_compat      = exynos5250_dt_compat,
1183         .restart        = exynos5_restart,
1184 MACHINE_END