arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dwc3-exynos.h>
  15 #include <linux/regulator/fixed.h>
  16 #include <linux/regulator/machine.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/smsc911x.h>
  19 #include <linux/delay.h>
  20 #include <linux/i2c.h>
  21 #include <linux/pwm_backlight.h>
  22 #include <linux/mfd/wm8994/pdata.h>
  23 #include <linux/regulator/machine.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/hardware/gic.h>
  28 #include <mach/map.h>
  29 #include <mach/ohci.h>
  30 #include <mach/regs-pmu.h>
  31 #include <mach/sysmmu.h>
  32 #include <mach/ohci.h>
  33 #include <mach/regs-audss.h>
  34
  35 #include <plat/audio.h>
  36 #include <plat/cpu.h>
  37 #include <plat/dsim.h>
  38 #include <plat/fb.h>
  39 #include <plat/mipi_dsi.h>
  40 #include <plat/gpio-cfg.h>
  41 #include <plat/regs-fb.h>
  42 #include <plat/regs-serial.h>
  43 #include <plat/regs-srom.h>
  44 #include <plat/backlight.h>
  45 #include <plat/devs.h>
  46 #include <plat/usb-phy.h>
  47 #include <plat/ehci.h>
  48 #include <plat/dp.h>
  49 #include <plat/s3c64xx-spi.h>
  50
  51 #include <video/platform_lcd.h>
  52
  53 #include "drm/exynos_drm.h"
  54 #include "common.h"
  55
  56 static void __init smsc911x_init(int ncs)
  57 {
  58         u32 data;
  59
  60         /* configure nCS1 width to 16 bits */
  61         data = __raw_readl(S5P_SROM_BW) &
  62                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  63         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  64                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  65                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  66         __raw_writel(data, S5P_SROM_BW);
  67
  68         /* set timing for nCS1 suitable for ethernet chip */
  69         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  70                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  71                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  72                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  73                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  74                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  75                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  76                 S5P_SROM_BC0 + (ncs * 4));
  77 }
  78
  79 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  80         .win_mode = {
  81                 .left_margin    = 4,
  82                 .right_margin   = 4,
  83                 .upper_margin   = 4,
  84                 .lower_margin   = 4,
  85                 .hsync_len      = 4,
  86                 .vsync_len      = 4,
  87                 .xres           = 1280,
  88                 .yres           = 800,
  89         },
  90         .virtual_x              = 1280,
  91         .virtual_y              = 800 * 2,
  92         .width                  = 223,
  93         .height                 = 125,
  94         .max_bpp                = 32,
  95         .default_bpp            = 24,
  96 };
  97
  98 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
  99         .win_mode = {
 100                 .left_margin    = 4,
 101                 .right_margin   = 4,
 102                 .upper_margin   = 4,
 103                 .lower_margin   = 4,
 104                 .hsync_len      = 4,
 105                 .vsync_len      = 4,
 106                 .xres           = 1280,
 107                 .yres           = 800,
 108         },
 109         .virtual_x              = 1280,
 110         .virtual_y              = 800 * 2,
 111         .width                  = 223,
 112         .height                 = 125,
 113         .max_bpp                = 32,
 114         .default_bpp            = 24,
 115 };
 116
 117 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 118         .win_mode = {
 119                 .left_margin    = 0x4,
 120                 .right_margin   = 0x4,
 121                 .upper_margin   = 4,
 122                 .lower_margin   = 4,
 123                 .hsync_len      = 4,
 124                 .vsync_len      = 4,
 125                 .xres           = 1280,
 126                 .yres           = 800,
 127         },
 128         .virtual_x              = 1280,
 129         .virtual_y              = 800 * 2,
 130         .width                  = 223,
 131         .height                 = 125,
 132         .max_bpp                = 32,
 133         .default_bpp            = 24,
 134 };
 135
 136 static struct fb_videomode snow_fb_window[] = {
 137         [0] = { /* Only LCD Connected */
 138                 .left_margin    = 0,
 139                 .right_margin   = 0,
 140                 .upper_margin   = 4,
 141                 .lower_margin   = 4,
 142                 .hsync_len      = 5,
 143                 .vsync_len      = 32,
 144                 .xres           = 1366,
 145                 .yres           = 768,
 146         },
 147         [1] = { /* TV & LCD Connected */
 148                 .left_margin    = 70,
 149                 .right_margin   = 70,
 150                 .upper_margin   = 12,
 151                 .lower_margin   = 13,
 152                 .hsync_len      = 5,
 153                 .vsync_len      = 32,
 154                 .xres           = 1280,
 155                 .yres           = 720,
 156         },
 157         [2] = {
 158                 .xres           = -1,
 159                 .yres           = -1,
 160         },
 161 };
 162
 163 static void exynos_fimd_gpio_setup_24bpp(void)
 164 {
 165         unsigned int reg = 0;
 166
 167         /*
 168          * Set DISP1BLK_CFG register for Display path selection
 169          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 170          * ---------------------
 171          * 0 | MIE/MDNIE
 172          * 1 | FIMD : selected
 173          */
 174         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 175         reg &= ~(1 << 15);      /* To save other reset values */
 176         reg |= (1 << 15);
 177         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 178 }
 179
 180 static void exynos_dp_gpio_setup_24bpp(void)
 181 {
 182         exynos_fimd_gpio_setup_24bpp();
 183
 184         /* Set Hotplug detect for DP */
 185         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 186         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 187 }
 188
 189 #ifdef CONFIG_DRM_EXYNOS_HDMI
 190 static struct platform_device exynos_drm_hdmi_device = {
 191         .name           = "exynos-drm-hdmi",
 192 };
 193
 194 static struct exynos_drm_hdmi_pdata drm_mixer_pdata = {
 195         .timing = {
 196                 .xres    = 1920,
 197                 .yres    = 1080,
 198                 .refresh = 60,
 199         },
 200         .default_win    = 0,
 201         .bpp            = 32,
 202         .is_v13         = 0,
 203         .is_soc_exynos5 = 1,
 204 };
 205
 206 static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = {
 207         .timing = {
 208                 .xres    = 1920,
 209                 .yres    = 1080,
 210                 .refresh    = 60,
 211         },
 212         .default_win    = 0,
 213         .bpp            = 32,
 214         .is_v13         = 0,
 215         .is_soc_exynos5 = 1,
 216 };
 217 #endif
 218
 219 #ifdef CONFIG_DRM_EXYNOS_FIMD
 220 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 221         .panel[0].timing   = {
 222                 .xres           = 1280,
 223                 .yres           = 800,
 224                 .hsync_len      = 4,
 225                 .left_margin    = 0x4,
 226                 .right_margin   = 0x4,
 227                 .vsync_len      = 4,
 228                 .upper_margin   = 4,
 229                 .lower_margin   = 4,
 230                 .refresh        = 60,
 231         },
 232         .panel[1].timing   = {
 233                 .xres           = 1280,
 234                 .yres           = 720,
 235                 .hsync_len      = 4,
 236                 .left_margin    = 0x4,
 237                 .right_margin   = 0x4,
 238                 .vsync_len      = 4,
 239                 .upper_margin   = 4,
 240                 .lower_margin   = 4,
 241                 .refresh        = 60,
 242         },
 243         .panel[2].timing   = {
 244                 .xres           = -1,
 245                 .yres           = -1,
 246         },
 247         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 248         .vidcon1        = VIDCON1_INV_VCLK,
 249         .default_win    = 0,
 250         .bpp            = 32,
 251         .clock_rate     = 800 * 1000 * 1000,
 252 };
 253 #else
 254 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 255         .win[0]         = &smdk5250_fb_win0,
 256         .win[1]         = &smdk5250_fb_win1,
 257         .win[2]         = &smdk5250_fb_win2,
 258         .default_win    = 0,
 259         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 260         .vidcon1        = VIDCON1_INV_VCLK,
 261         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 262         .clock_rate     = 800 * 1000 * 1000,
 263 };
 264 #endif
 265
 266 static struct mipi_dsim_config dsim_info = {
 267         .e_interface            = DSIM_VIDEO,
 268         .e_pixel_format         = DSIM_24BPP_888,
 269         /* main frame fifo auto flush at VSYNC pulse */
 270         .auto_flush             = false,
 271         .eot_disable            = false,
 272         .auto_vertical_cnt      = false,
 273         .hse                    = false,
 274         .hfp                    = false,
 275         .hbp                    = false,
 276         .hsa                    = false,
 277
 278         .e_no_data_lane         = DSIM_DATA_LANE_4,
 279         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 280         .e_burst_mode           = DSIM_BURST,
 281
 282         .p                      = 3,
 283         .m                      = 115,
 284         .s                      = 1,
 285
 286         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 287         .pll_stable_time        = 500,
 288
 289         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 290
 291         /* stop state holding counter after bta change count 0 ~ 0xfff */
 292         .stop_holding_cnt       = 0x0f,
 293         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 294         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 295
 296         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 297 };
 298
 299 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 300         .rgb_timing.left_margin         = 0x4,
 301         .rgb_timing.right_margin        = 0x4,
 302         .rgb_timing.upper_margin        = 0x4,
 303         .rgb_timing.lower_margin        =  0x4,
 304         .rgb_timing.hsync_len           = 0x4,
 305         .rgb_timing.vsync_len           = 0x4,
 306         .cpu_timing.cs_setup            = 0,
 307         .cpu_timing.wr_setup            = 1,
 308         .cpu_timing.wr_act              = 0,
 309         .cpu_timing.wr_hold             = 0,
 310         .lcd_size.width                 = 1280,
 311         .lcd_size.height                = 800,
 312 };
 313
 314 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 315         .clk_name               = "dsim0",
 316         .dsim_config            = &dsim_info,
 317         .dsim_lcd_config        = &dsim_lcd_info,
 318
 319         .part_reset             = s5p_dsim_part_reset,
 320         .init_d_phy             = s5p_dsim_init_d_phy,
 321         .get_fb_frame_done      = NULL,
 322         .trigger                = NULL,
 323
 324         /*
 325          * the stable time of needing to write data on SFR
 326          * when the mipi mode becomes LP mode.
 327          */
 328         .delay_for_stabilization = 600,
 329 };
 330
 331 static struct platform_device exynos_drm_device = {
 332         .name           = "exynos-drm",
 333         .dev = {
 334                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 335                 .coherent_dma_mask = 0xffffffffUL,
 336         }
 337 };
 338
 339 static void lcd_set_power(struct plat_lcd_data *pd,
 340                         unsigned int power)
 341 {
 342         if (of_machine_is_compatible("google,daisy") ||
 343                         of_machine_is_compatible("google,snow")) {
 344                 struct regulator *lcd_fet;
 345
 346                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 347                 if (!IS_ERR(lcd_fet)) {
 348                         if (power)
 349                                 regulator_enable(lcd_fet);
 350                         else
 351                                 regulator_disable(lcd_fet);
 352
 353                         regulator_put(lcd_fet);
 354                 }
 355         }
 356
 357         if (!of_machine_is_compatible("google,snow")) {
 358                 /* reset */
 359                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 360                 mdelay(20);
 361                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 362                 mdelay(20);
 363                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 364                 mdelay(20);
 365                 gpio_free(EXYNOS5_GPX1(5));
 366                 mdelay(20);
 367         }
 368
 369
 370         /* Turn on regulator for backlight */
 371         if (of_machine_is_compatible("google,daisy") ||
 372                         of_machine_is_compatible("google,snow")) {
 373                 struct regulator *backlight_fet;
 374
 375                 backlight_fet = regulator_get(NULL, "vcd_led");
 376                 if (!IS_ERR(backlight_fet)) {
 377                         if (power)
 378                                 regulator_enable(backlight_fet);
 379                         else
 380                                 regulator_disable(backlight_fet);
 381
 382                         regulator_put(backlight_fet);
 383                 }
 384                 /* Wait 10 ms between regulator on and PWM start per spec */
 385                 mdelay(10);
 386         }
 387 }
 388
 389 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 390 {
 391         /* Don't call .set_power callback while unblanking */
 392         return 0;
 393 }
 394
 395 static struct plat_lcd_data smdk5250_lcd_data = {
 396         .set_power      = lcd_set_power,
 397         .match_fb       = smdk5250_match_fb,
 398 };
 399
 400 static struct platform_device smdk5250_lcd = {
 401         .name                   = "platform-lcd",
 402         .dev.platform_data      = &smdk5250_lcd_data,
 403 };
 404
 405 static int smdk5250_bl_notify(struct device *unused, int brightness)
 406 {
 407         /* manage lcd_bl_en signal */
 408         if (brightness)
 409                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 410         else
 411                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 412
 413         return brightness;
 414 }
 415
 416 /* LCD Backlight data */
 417 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 418         .no     = EXYNOS5_GPB2(0),
 419         .func   = S3C_GPIO_SFN(2),
 420 };
 421
 422 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 423         .pwm_period_ns  = 1000000,
 424         .notify         = smdk5250_bl_notify,
 425 };
 426
 427 struct platform_device exynos_device_md0 = {
 428         .name = "exynos-mdev",
 429         .id = 0,
 430 };
 431
 432 struct platform_device exynos_device_md1 = {
 433         .name = "exynos-mdev",
 434         .id = 1,
 435 };
 436
 437 struct platform_device exynos_device_md2 = {
 438         .name = "exynos-mdev",
 439         .id = 2,
 440 };
 441
 442 static struct regulator_consumer_supply wm8994_avdd1_supply =
 443         REGULATOR_SUPPLY("AVDD1", "1-001a");
 444
 445 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 446         REGULATOR_SUPPLY("DCVDD", "1-001a");
 447
 448 static struct regulator_init_data wm8994_ldo1_data = {
 449         .constraints    = {
 450                 .name           = "AVDD1",
 451         },
 452         .num_consumer_supplies  = 1,
 453         .consumer_supplies      = &wm8994_avdd1_supply,
 454 };
 455
 456 static struct regulator_init_data wm8994_ldo2_data = {
 457         .constraints    = {
 458         .name                   = "DCVDD",
 459                 },
 460         .num_consumer_supplies  = 1,
 461         .consumer_supplies      = &wm8994_dcvdd_supply,
 462 };
 463
 464 static struct wm8994_pdata wm8994_platform_data = {
 465         /* configure gpio1 function: 0x0001(Logic level input/output) */
 466         .gpio_defaults[0] = 0x0001,
 467         /* If the i2s0 and i2s2 is enabled simultaneously */
 468         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 469         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 470         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 471         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 472         .ldo[0] = { 0, &wm8994_ldo1_data },
 473         .ldo[1] = { 0, &wm8994_ldo2_data },
 474 };
 475
 476 static struct i2c_board_info i2c_devs1[] __initdata = {
 477         {
 478                 I2C_BOARD_INFO("wm8994", 0x1a),
 479                 .platform_data  = &wm8994_platform_data,
 480         },
 481 };
 482
 483 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 484         [0] = {
 485                 .line           = EXYNOS5_GPA2(5),
 486                 .fb_delay       = 0x2,
 487         },
 488 };
 489
 490 static struct spi_board_info spi1_board_info[] __initdata = {
 491         {
 492                 .modalias               = "spidev",
 493                 .platform_data          = NULL,
 494                 .max_speed_hz           = 10*1000*1000,
 495                 .bus_num                = 1,
 496                 .chip_select            = 0,
 497                 .mode                   = SPI_MODE_0,
 498                 .controller_data        = spi1_csi,
 499         }
 500 };
 501
 502 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 503         .dbgname = "mfc_l",
 504         .clockname = "sysmmu",
 505 };
 506
 507 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 508         .dbgname = "mfc_r",
 509         .clockname = "sysmmu",
 510 };
 511
 512 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 513         .dbgname = "gsc",
 514         .clockname = "sysmmu",
 515 };
 516
 517 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 518         .dbgname = "g2d",
 519         .clockname = "sysmmu",
 520 };
 521
 522 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 523         .dbgname = "fimd",
 524         .clockname = "sysmmu",
 525 };
 526
 527 struct sysmmu_platform_data platdata_sysmmu_tv = {
 528         .dbgname = "tv",
 529         .clockname = "sysmmu",
 530 };
 531
 532 #ifdef CONFIG_VIDEO_FIMG2D4X
 533 static struct fimg2d_platdata fimg2d_data __initdata = {
 534         .hw_ver         = 0x42,
 535         .gate_clkname   = "fimg2d",
 536 };
 537 #endif
 538
 539 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 540         .phy_init = s5p_usb_phy_init,
 541         .phy_exit = s5p_usb_phy_exit,
 542 };
 543
 544 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 545         .phy_init = s5p_usb_phy_init,
 546         .phy_exit = s5p_usb_phy_exit,
 547 };
 548
 549 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 550         .phy_type = S5P_USB_PHY_DRD,
 551         .phy_init = s5p_usb_phy_init,
 552         .phy_exit = s5p_usb_phy_exit,
 553 };
 554
 555 struct exynos_gpio_cfg {
 556         unsigned int    addr;
 557         unsigned int    num;
 558         unsigned int    bit;
 559 };
 560
 561 static const char *rclksrc[] = {
 562         [0] = "busclk",
 563         [1] = "i2sclk",
 564 };
 565
 566 static struct video_info smdk5250_dp_config = {
 567         .name                   = "eDP-LVDS NXP PTN3460",
 568
 569         .h_sync_polarity        = 0,
 570         .v_sync_polarity        = 0,
 571         .interlaced             = 0,
 572
 573         .color_space            = COLOR_RGB,
 574         .dynamic_range          = VESA,
 575         .ycbcr_coeff            = COLOR_YCBCR601,
 576         .color_depth            = COLOR_8,
 577
 578         .link_rate              = LINK_RATE_2_70GBPS,
 579         .lane_count             = LANE_COUNT2,
 580 };
 581
 582 static struct exynos_dp_platdata smdk5250_dp_data = {
 583         .video_info     = &smdk5250_dp_config,
 584         .training_type  = SW_LINK_TRAINING,
 585         .phy_init       = s5p_dp_phy_init,
 586         .phy_exit       = s5p_dp_phy_exit,
 587 };
 588
 589 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 590 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 591 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 592 /* Mask bit[12:8] for xxti clock selection */
 593 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 594
 595 static void __init enable_xclkout(void)
 596 {
 597        unsigned int tmp;
 598
 599        tmp = readl(S5P_PMU_DEBUG);
 600        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 601        tmp |= PMU_DEBUG_XXTI;
 602        writel(tmp, S5P_PMU_DEBUG);
 603 }
 604
 605 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 606 {
 607         int id;
 608         /* configure GPIO for i2s port */
 609         struct exynos_gpio_cfg exynos5_cfg[3] = {
 610                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 611                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 612                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 613         };
 614
 615         if (pdev->dev.of_node) {
 616                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 617                 if (id < 0)
 618                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 619         } else {
 620                 id = pdev->id;
 621         }
 622
 623         if (id < 0 || id > 2) {
 624                 printk(KERN_ERR "Invalid Device %d\n", id);
 625                 return -EINVAL;
 626         }
 627
 628         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 629                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 630
 631         return 0;
 632 }
 633
 634 static struct s3c_audio_pdata i2sv5_pdata = {
 635         .cfg_gpio = exynos_cfg_i2s_gpio,
 636         .type = {
 637                 .i2s = {
 638                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 639                                          | QUIRK_NEED_RSTCLR,
 640                         .src_clk = rclksrc,
 641                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 642                 },
 643         },
 644 };
 645 /*
 646  * The following lookup table is used to override device names when devices
 647  * are registered from device tree. This is temporarily added to enable
 648  * device tree support addition for the EXYNOS5 architecture.
 649  *
 650  * For drivers that require platform data to be provided from the machine
 651  * file, a platform data pointer can also be supplied along with the
 652  * devices names. Usually, the platform data elements that cannot be parsed
 653  * from the device tree by the drivers (example: function pointers) are
 654  * supplied. But it should be noted that this is a temporary mechanism and
 655  * at some point, the drivers should be capable of parsing all the platform
 656  * data from the device tree.
 657  */
 658 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 659         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 660                                 "exynos4210-uart.0", NULL),
 661         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 662                                 "exynos4210-uart.1", NULL),
 663         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 664                                 "exynos4210-uart.2", NULL),
 665         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 666                                 "exynos4210-uart.3", NULL),
 667         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 668                                 "s3c2440-i2c.0", NULL),
 669         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 670                                 "s3c2440-i2c.1", NULL),
 671         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 672                                 "s3c2440-i2c.2", NULL),
 673         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 674                                 "s3c2440-i2c.3", NULL),
 675         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 676                                 "s3c2440-i2c.4", NULL),
 677         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 678                                 "s3c2440-i2c.5", NULL),
 679         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 680                                 "s3c2440-i2c.6", NULL),
 681         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 682                                 "s3c2440-i2c.7", NULL),
 683         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 684                                 "s3c2440-hdmiphy-i2c", NULL),
 685         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 686                                 "exynos4210-spi.0", NULL),
 687         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 688                                 "exynos4210-spi.1", NULL),
 689         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 690                                 "exynos4210-spi.2", NULL),
 691         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 692                                 "dw_mmc.0", NULL),
 693         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 694                                 "dw_mmc.1", NULL),
 695         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 696                                 "dw_mmc.2", NULL),
 697         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 698                                 "dw_mmc.3", NULL),
 699         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 700         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 701         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 702         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 703                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 704         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 705                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 706         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 707                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 708         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 709                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 710         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 711                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 712         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 713                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 714         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 715                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 716         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 717                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 718         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 719                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 720         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 721                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 722         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 723                                 "s5p-mipi-dsim", &dsim_platform_data),
 724         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 725                                 "s5p-dp", &smdk5250_dp_data),
 726         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 727         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 728                                 "exynos-gsc.0", NULL),
 729         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 730                                 "exynos-gsc.1", NULL),
 731         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 732                                 "exynos-gsc.2", NULL),
 733         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 734                                 "exynos-gsc.3", NULL),
 735 #ifdef CONFIG_VIDEO_FIMG2D4X
 736         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 737                                 "s5p-g2d", &fimg2d_data),
 738 #endif
 739         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 740                                 "exynos-ohci", &smdk5250_ohci_pdata),
 741         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 742                                 "s5p-ehci", &smdk5250_ehci_pdata),
 743         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 744                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 745         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 746                                 "samsung-i2s.0", &i2sv5_pdata),
 747 #ifdef CONFIG_DRM_EXYNOS_HDMI
 748         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 749                                 "exynos5-hdmi", &drm_hdmi_pdata),
 750         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 751                                 "s5p-mixer", &drm_mixer_pdata),
 752 #else
 753         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 754                                 "exynos5-hdmi", NULL),
 755         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000,
 756                                 "s5p-mixer", NULL),
 757 #endif
 758         {},
 759 };
 760
 761 static struct platform_device *smdk5250_devices[] __initdata = {
 762         &smdk5250_lcd, /* for platform_lcd device */
 763         &exynos_device_md0, /* for media device framework */
 764         &exynos_device_md1, /* for media device framework */
 765         &exynos_device_md2, /* for media device framework */
 766         &samsung_asoc_dma,  /* for audio dma interface device */
 767         &exynos_drm_device,
 768 #ifdef CONFIG_DRM_EXYNOS_HDMI
 769         &exynos_drm_hdmi_device,
 770 #endif
 771 };
 772
 773 static struct regulator_consumer_supply dummy_supplies[] = {
 774         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 775         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 776 };
 777
 778 static void __init exynos5250_dt_map_io(void)
 779 {
 780         exynos_init_io(NULL, 0);
 781         s3c24xx_init_clocks(24000000);
 782 }
 783
 784 static void __init exynos5_reserve(void)
 785 {
 786         /* required to have enough address range to remap the IOMMU
 787          * allocated buffers */
 788         init_consistent_dma_size(SZ_64M);
 789 }
 790
 791 static void s5p_tv_setup(void)
 792 {
 793         /* direct HPD to HDMI chip */
 794         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 795
 796         gpio_direction_input(EXYNOS5_GPX3(7));
 797         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 798         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 799 }
 800
 801 static void exynos5_i2c_setup(void)
 802 {
 803         /* Setup the low-speed i2c controller interrupts */
 804         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 805 }
 806
 807 static void __init exynos5250_dt_machine_init(void)
 808 {
 809         struct device_node *srom_np, *np;
 810         int ret,i;
 811
 812         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 813
 814         /* Setup pins for any SMSC 911x controller on the SROMC bus */
 815         srom_np = of_find_node_by_path("/sromc-bus");
 816         if (!srom_np) {
 817                 printk(KERN_ERR "No /sromc-bus property.\n");
 818                 goto out;
 819         }
 820         for_each_child_of_node(srom_np, np) {
 821                 if (of_device_is_compatible(np, "smsc,lan9115")) {
 822                         u32 reg;
 823                         of_property_read_u32(np, "reg", &reg);
 824                         smsc911x_init(reg);
 825                 }
 826         }
 827
 828         /*
 829          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 830          * TODO: Fix this so we are not at risk of requesting the GPIO
 831          * multiple times, this should be done with device tree, and
 832          * likely integrated into the plat-samsung/dev-backlight.c init.
 833          */
 834         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "lcd_bl_en");
 835
 836         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 837
 838         /*
 839          * HACK ALERT! TODO: FIXME!
 840          *
 841          * We're going to hack in Daisy LCD info here for bringup purposes.
 842          * Lots of things wrong with what we're doing here, but it works for
 843          * bringup purposes.
 844          */
 845
 846         if (of_machine_is_compatible("google,daisy")) {
 847 #ifdef CONFIG_DRM_EXYNOS_FIMD
 848                 smdk5250_lcd1_pdata.panel[0].timing.xres = 1366;
 849                 smdk5250_lcd1_pdata.panel[0].timing.yres = 768;
 850                 smdk5250_lcd1_pdata.panel[1].timing.xres = 1280;
 851                 smdk5250_lcd1_pdata.panel[1].timing.yres = 720;
 852                 smdk5250_lcd1_pdata.panel[2].timing.xres = -1;
 853                 smdk5250_lcd1_pdata.panel[2].timing.yres = -1;
 854                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
 855 #else
 856                 smdk5250_fb_win0.win_mode.xres = 1366;
 857                 smdk5250_fb_win0.win_mode.yres = 768;
 858                 smdk5250_fb_win0.virtual_x = 1366;
 859                 smdk5250_fb_win0.virtual_y = 768 * 2;
 860
 861                 smdk5250_fb_win1.win_mode.xres = 1366;
 862                 smdk5250_fb_win1.win_mode.yres = 768;
 863                 smdk5250_fb_win1.virtual_x = 1366;
 864                 smdk5250_fb_win1.virtual_y = 768 * 2;
 865
 866                 smdk5250_fb_win2.win_mode.xres = 1366;
 867                 smdk5250_fb_win2.win_mode.yres = 768;
 868                 smdk5250_fb_win2.virtual_x = 1366;
 869                 smdk5250_fb_win2.virtual_y = 768 * 2;
 870 #endif
 871                 dsim_lcd_info.lcd_size.width = 1366;
 872                 dsim_lcd_info.lcd_size.height = 768;
 873         } else if (of_machine_is_compatible("google,snow")) {
 874 #ifdef CONFIG_DRM_EXYNOS_FIMD
 875                 for (i = 0;i < ARRAY_SIZE(snow_fb_window);i++)
 876                         smdk5250_lcd1_pdata.panel[i].timing = snow_fb_window[i];
 877
 878                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
 879                 smdk5250_lcd1_pdata.clock_rate = 267 * 1000 * 1000;
 880                 smdk5250_lcd1_pdata.vidcon1 = 0;
 881 #endif
 882                 ret = gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH,
 883                                         "DP_PD_N");
 884                 WARN_ON(ret);
 885         }
 886
 887         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 888                 "HOST_VBUS_CONTROL")) {
 889                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 890         } else {
 891                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 892                 gpio_free(EXYNOS5_GPX2(6));
 893         }
 894
 895         exynos5_i2c_setup();
 896
 897         /*
 898          * MAX77686 PMIC interrupt setup code
 899          * TODO: Convert the device tree wakeup_int domain to support
 900          * pull-up flags
 901          */
 902         s3c_gpio_setpull(EXYNOS5_GPX3(2), S3C_GPIO_PULL_NONE);
 903
 904         /*
 905          * BIG HACK: The wm8994 is not device tree enabled apparently, so
 906          * needs to be added manually.  ...but it's only on SMDK5250.
 907          */
 908         if (of_machine_is_compatible("samsung,smdk5250")) {
 909                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 910         }
 911
 912         /* XCLKOUT needs to be moved over to the clock interface, but enable it
 913          * here for now.
 914          */
 915         enable_xclkout();
 916
 917         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
 918                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
 919         } else {
 920                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
 921                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
 922                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
 923                 spi_register_board_info(spi1_board_info,
 924                                         ARRAY_SIZE(spi1_board_info));
 925         }
 926
 927         of_platform_populate(NULL, of_default_bus_match_table,
 928                                 exynos5250_auxdata_lookup, NULL);
 929
 930 #ifdef CONFIG_DRM_EXYNOS_FIMD
 931         if (of_machine_is_compatible("google,snow"))
 932                 exynos_dp_gpio_setup_24bpp();
 933         else
 934                 exynos_fimd_gpio_setup_24bpp();
 935 #endif
 936         s5p_tv_setup();
 937
 938         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 939 out:
 940         of_node_put(srom_np);
 941         return;
 942 }
 943
 944 static char const *exynos5250_dt_compat[] __initdata = {
 945         "samsung,exynos5250",
 946         NULL
 947 };
 948
 949 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 950         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 951         .init_irq       = exynos5_init_irq,
 952         .reserve        = exynos5_reserve,
 953         .map_io         = exynos5250_dt_map_io,
 954         .handle_irq     = gic_handle_irq,
 955         .init_machine   = exynos5250_dt_machine_init,
 956         .timer          = &exynos4_timer,
 957         .dt_compat      = exynos5250_dt_compat,
 958         .restart        = exynos5_restart,
 959 MACHINE_END