arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dwc3-exynos.h>
  15 #include <linux/serial_core.h>
  16 #include <linux/smsc911x.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/pwm_backlight.h>
  20 #include <linux/mfd/wm8994/pdata.h>
  21 #include <linux/regulator/machine.h>
  22
  23 #include <asm/mach/arch.h>
  24 #include <asm/hardware/gic.h>
  25 #include <mach/map.h>
  26 #include <mach/ohci.h>
  27 #include <mach/regs-pmu.h>
  28 #include <mach/sysmmu.h>
  29 #include <mach/ohci.h>
  30 #include <mach/regs-audss.h>
  31
  32 #include <plat/audio.h>
  33 #include <plat/cpu.h>
  34 #include <plat/dsim.h>
  35 #include <plat/fb.h>
  36 #include <plat/mipi_dsi.h>
  37 #include <plat/gpio-cfg.h>
  38 #include <plat/regs-fb.h>
  39 #include <plat/regs-serial.h>
  40 #include <plat/regs-srom.h>
  41 #include <plat/backlight.h>
  42 #include <plat/devs.h>
  43 #include <plat/usb-phy.h>
  44 #include <plat/ehci.h>
  45
  46 #include <video/platform_lcd.h>
  47
  48 #include "drm/exynos_drm.h"
  49 #include "common.h"
  50
  51 static void __init smsc911x_init(int ncs)
  52 {
  53         u32 data;
  54
  55         /* configure nCS1 width to 16 bits */
  56         data = __raw_readl(S5P_SROM_BW) &
  57                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  58         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  59                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  60                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  61         __raw_writel(data, S5P_SROM_BW);
  62
  63         /* set timing for nCS1 suitable for ethernet chip */
  64         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  65                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  66                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  67                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  68                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  69                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  70                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  71                 S5P_SROM_BC0 + (ncs * 4));
  72 }
  73
  74 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  75         .win_mode = {
  76                 .left_margin    = 4,
  77                 .right_margin   = 4,
  78                 .upper_margin   = 4,
  79                 .lower_margin   = 4,
  80                 .hsync_len      = 4,
  81                 .vsync_len      = 4,
  82                 .xres           = 1280,
  83                 .yres           = 800,
  84         },
  85         .virtual_x              = 1280,
  86         .virtual_y              = 800 * 2,
  87         .width                  = 223,
  88         .height                 = 125,
  89         .max_bpp                = 32,
  90         .default_bpp            = 24,
  91 };
  92
  93 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
  94         .win_mode = {
  95                 .left_margin    = 4,
  96                 .right_margin   = 4,
  97                 .upper_margin   = 4,
  98                 .lower_margin   = 4,
  99                 .hsync_len      = 4,
 100                 .vsync_len      = 4,
 101                 .xres           = 1280,
 102                 .yres           = 800,
 103         },
 104         .virtual_x              = 1280,
 105         .virtual_y              = 800 * 2,
 106         .width                  = 223,
 107         .height                 = 125,
 108         .max_bpp                = 32,
 109         .default_bpp            = 24,
 110 };
 111
 112 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 113         .win_mode = {
 114                 .left_margin    = 0x4,
 115                 .right_margin   = 0x4,
 116                 .upper_margin   = 4,
 117                 .lower_margin   = 4,
 118                 .hsync_len      = 4,
 119                 .vsync_len      = 4,
 120                 .xres           = 1280,
 121                 .yres           = 800,
 122         },
 123         .virtual_x              = 1280,
 124         .virtual_y              = 800 * 2,
 125         .width                  = 223,
 126         .height                 = 125,
 127         .max_bpp                = 32,
 128         .default_bpp            = 24,
 129 };
 130
 131 static void exynos_fimd_gpio_setup_24bpp(void)
 132 {
 133         unsigned int reg = 0;
 134
 135         /*
 136          * Set DISP1BLK_CFG register for Display path selection
 137          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 138          * ---------------------
 139          * 0 | MIE/MDNIE
 140          * 1 | FIMD : selected
 141          */
 142         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 143         reg &= ~(1 << 15);      /* To save other reset values */
 144         reg |= (1 << 15);
 145         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 146 }
 147
 148 #ifdef CONFIG_DRM_EXYNOS_FIMD
 149 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 150         .panel.timing   = {
 151                 .xres           = 1280,
 152                 .yres           = 800,
 153                 .hsync_len      = 4,
 154                 .left_margin    = 0x4,
 155                 .right_margin   = 0x4,
 156                 .vsync_len      = 4,
 157                 .upper_margin   = 4,
 158                 .lower_margin   = 4,
 159                 .refresh        = 60,
 160         },
 161         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 162         .vidcon1        = VIDCON1_INV_VCLK,
 163         .default_win    = 0,
 164         .bpp            = 32,
 165 };
 166 #else
 167 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 168         .win[0]         = &smdk5250_fb_win0,
 169         .win[1]         = &smdk5250_fb_win1,
 170         .win[2]         = &smdk5250_fb_win2,
 171         .default_win    = 0,
 172         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 173         .vidcon1        = VIDCON1_INV_VCLK,
 174         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 175 };
 176 #endif
 177
 178 static struct mipi_dsim_config dsim_info = {
 179         .e_interface            = DSIM_VIDEO,
 180         .e_pixel_format         = DSIM_24BPP_888,
 181         /* main frame fifo auto flush at VSYNC pulse */
 182         .auto_flush             = false,
 183         .eot_disable            = false,
 184         .auto_vertical_cnt      = false,
 185         .hse                    = false,
 186         .hfp                    = false,
 187         .hbp                    = false,
 188         .hsa                    = false,
 189
 190         .e_no_data_lane         = DSIM_DATA_LANE_4,
 191         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 192         .e_burst_mode           = DSIM_BURST,
 193
 194         .p                      = 3,
 195         .m                      = 115,
 196         .s                      = 1,
 197
 198         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 199         .pll_stable_time        = 500,
 200
 201         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 202
 203         /* stop state holding counter after bta change count 0 ~ 0xfff */
 204         .stop_holding_cnt       = 0x0f,
 205         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 206         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 207
 208         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 209 };
 210
 211 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 212         .rgb_timing.left_margin         = 0x4,
 213         .rgb_timing.right_margin        = 0x4,
 214         .rgb_timing.upper_margin        = 0x4,
 215         .rgb_timing.lower_margin        =  0x4,
 216         .rgb_timing.hsync_len           = 0x4,
 217         .rgb_timing.vsync_len           = 0x4,
 218         .cpu_timing.cs_setup            = 0,
 219         .cpu_timing.wr_setup            = 1,
 220         .cpu_timing.wr_act              = 0,
 221         .cpu_timing.wr_hold             = 0,
 222         .lcd_size.width                 = 1280,
 223         .lcd_size.height                = 800,
 224 };
 225
 226 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 227         .clk_name               = "dsim0",
 228         .dsim_config            = &dsim_info,
 229         .dsim_lcd_config        = &dsim_lcd_info,
 230
 231         .part_reset             = s5p_dsim_part_reset,
 232         .init_d_phy             = s5p_dsim_init_d_phy,
 233         .get_fb_frame_done      = NULL,
 234         .trigger                = NULL,
 235
 236         /*
 237          * the stable time of needing to write data on SFR
 238          * when the mipi mode becomes LP mode.
 239          */
 240         .delay_for_stabilization = 600,
 241 };
 242
 243 static struct platform_device exynos_drm_device = {
 244         .name           = "exynos-drm",
 245         .dev = {
 246                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 247                 .coherent_dma_mask = 0xffffffffUL,
 248         }
 249 };
 250
 251 static void lcd_set_power(struct plat_lcd_data *pd,
 252                         unsigned int power)
 253 {
 254         /* reset */
 255         gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 256
 257         mdelay(20);
 258         if (power) {
 259                 /* fire nRESET on power up */
 260                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 261                 mdelay(20);
 262                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 263                 mdelay(20);
 264                 gpio_free(EXYNOS5_GPX1(5));
 265         } else {
 266                 /* fire nRESET on power off */
 267                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 268                 mdelay(20);
 269                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 270                 mdelay(20);
 271                 gpio_free(EXYNOS5_GPX1(5));
 272         }
 273         mdelay(20);
 274         /*
 275          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 276          * TODO: Fix this so we are not at risk of requesting the GPIO
 277          * multiple times, this should be done with device tree, and
 278          * likely integrated into the plat-samsung/dev-backlight.c init.
 279          */
 280         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
 281 }
 282
 283 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 284 {
 285         /* Don't call .set_power callback while unblanking */
 286         return 0;
 287 }
 288
 289 static struct plat_lcd_data smdk5250_lcd_data = {
 290         .set_power      = lcd_set_power,
 291         .match_fb       = smdk5250_match_fb,
 292 };
 293
 294 static struct platform_device smdk5250_lcd = {
 295         .name                   = "platform-lcd",
 296         .dev.platform_data      = &smdk5250_lcd_data,
 297 };
 298
 299 static int smdk5250_bl_notify(struct device *unused, int brightness)
 300 {
 301         /* manage lcd_bl_en signal */
 302         if (brightness)
 303                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 304         else
 305                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 306
 307         return brightness;
 308 }
 309
 310 /* LCD Backlight data */
 311 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 312         .no     = EXYNOS5_GPB2(0),
 313         .func   = S3C_GPIO_SFN(2),
 314 };
 315
 316 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 317         .pwm_period_ns  = 1000,
 318         .notify         = smdk5250_bl_notify,
 319 };
 320
 321 struct platform_device exynos_device_md0 = {
 322         .name = "exynos-mdev",
 323         .id = 0,
 324 };
 325
 326 struct platform_device exynos_device_md1 = {
 327         .name = "exynos-mdev",
 328         .id = 1,
 329 };
 330
 331 struct platform_device exynos_device_md2 = {
 332         .name = "exynos-mdev",
 333         .id = 2,
 334 };
 335
 336 static struct regulator_consumer_supply wm8994_avdd1_supply =
 337         REGULATOR_SUPPLY("AVDD1", "1-001a");
 338
 339 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 340         REGULATOR_SUPPLY("DCVDD", "1-001a");
 341
 342 static struct regulator_init_data wm8994_ldo1_data = {
 343         .constraints    = {
 344                 .name           = "AVDD1",
 345         },
 346         .num_consumer_supplies  = 1,
 347         .consumer_supplies      = &wm8994_avdd1_supply,
 348 };
 349
 350 static struct regulator_init_data wm8994_ldo2_data = {
 351         .constraints    = {
 352         .name                   = "DCVDD",
 353                 },
 354         .num_consumer_supplies  = 1,
 355         .consumer_supplies      = &wm8994_dcvdd_supply,
 356 };
 357
 358 static struct wm8994_pdata wm8994_platform_data = {
 359         /* configure gpio1 function: 0x0001(Logic level input/output) */
 360         .gpio_defaults[0] = 0x0001,
 361         /* If the i2s0 and i2s2 is enabled simultaneously */
 362         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 363         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 364         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 365         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 366         .ldo[0] = { 0, &wm8994_ldo1_data },
 367         .ldo[1] = { 0, &wm8994_ldo2_data },
 368 };
 369
 370 static struct i2c_board_info i2c_devs1[] __initdata = {
 371         {
 372                 I2C_BOARD_INFO("wm8994", 0x1a),
 373                 .platform_data  = &wm8994_platform_data,
 374         },
 375 };
 376
 377 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 378         .dbgname = "mfc_l",
 379         .clockname = "sysmmu",
 380 };
 381
 382 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 383         .dbgname = "mfc_r",
 384         .clockname = "sysmmu",
 385 };
 386
 387 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 388         .dbgname = "gsc",
 389         .clockname = "sysmmu",
 390 };
 391
 392 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 393         .dbgname = "g2d",
 394         .clockname = "sysmmu",
 395 };
 396
 397 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 398         .dbgname = "fimd",
 399         .clockname = "sysmmu",
 400 };
 401
 402 struct sysmmu_platform_data platdata_sysmmu_tv = {
 403         .dbgname = "tv",
 404         .clockname = "sysmmu",
 405 };
 406
 407 #ifdef CONFIG_VIDEO_FIMG2D4X
 408 static struct fimg2d_platdata fimg2d_data __initdata = {
 409         .hw_ver         = 0x42,
 410         .gate_clkname   = "fimg2d",
 411 };
 412 #endif
 413
 414 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 415         .phy_init = s5p_usb_phy_init,
 416         .phy_exit = s5p_usb_phy_exit,
 417 };
 418
 419 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 420         .phy_init = s5p_usb_phy_init,
 421         .phy_exit = s5p_usb_phy_exit,
 422 };
 423
 424 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 425         .phy_type = S5P_USB_PHY_DRD,
 426         .phy_init = s5p_usb_phy_init,
 427         .phy_exit = s5p_usb_phy_exit,
 428 };
 429
 430 struct exynos_gpio_cfg {
 431         unsigned int    addr;
 432         unsigned int    num;
 433         unsigned int    bit;
 434 };
 435
 436 static const char *rclksrc[] = {
 437         [0] = "busclk",
 438         [1] = "i2sclk",
 439 };
 440
 441 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 442 {
 443         int id;
 444         /* configure GPIO for i2s port */
 445         struct exynos_gpio_cfg exynos5_cfg[3] = {
 446                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 447                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 448                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 449         };
 450
 451         if (pdev->dev.of_node) {
 452                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 453                 if (id < 0)
 454                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 455         } else {
 456                 id = pdev->id;
 457         }
 458
 459         if (id < 0 || id > 2) {
 460                 printk(KERN_ERR "Invalid Device %d\n", id);
 461                 return -EINVAL;
 462         }
 463
 464         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 465                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 466
 467         return 0;
 468 }
 469
 470 static struct s3c_audio_pdata i2sv5_pdata = {
 471         .cfg_gpio = exynos_cfg_i2s_gpio,
 472         .type = {
 473                 .i2s = {
 474                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 475                                          | QUIRK_NEED_RSTCLR,
 476                         .src_clk = rclksrc,
 477                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 478                 },
 479         },
 480 };
 481 /*
 482  * The following lookup table is used to override device names when devices
 483  * are registered from device tree. This is temporarily added to enable
 484  * device tree support addition for the EXYNOS5 architecture.
 485  *
 486  * For drivers that require platform data to be provided from the machine
 487  * file, a platform data pointer can also be supplied along with the
 488  * devices names. Usually, the platform data elements that cannot be parsed
 489  * from the device tree by the drivers (example: function pointers) are
 490  * supplied. But it should be noted that this is a temporary mechanism and
 491  * at some point, the drivers should be capable of parsing all the platform
 492  * data from the device tree.
 493  */
 494 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 495         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 496                                 "exynos4210-uart.0", NULL),
 497         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 498                                 "exynos4210-uart.1", NULL),
 499         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 500                                 "exynos4210-uart.2", NULL),
 501         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 502                                 "exynos4210-uart.3", NULL),
 503         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 504                                 "s3c2440-i2c.0", NULL),
 505         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 506                                 "s3c2440-i2c.1", NULL),
 507         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 508                                 "s3c2440-i2c.2", NULL),
 509         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 510                                 "s3c2440-hdmiphy-i2c", NULL),
 511         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 512                                 "dw_mmc.0", NULL),
 513         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 514                                 "dw_mmc.1", NULL),
 515         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 516                                 "dw_mmc.2", NULL),
 517         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 518                                 "dw_mmc.3", NULL),
 519         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 520         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 521         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 522         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 523                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 524         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 525                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 526         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 527                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 528         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 529                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 530         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 531                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 532         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 533                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 534         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 535                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 536         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 537                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 538         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 539                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 540         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 541                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 542         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 543                                 "s5p-mipi-dsim", &dsim_platform_data),
 544         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 545         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 546                                 "exynos-gsc.0", NULL),
 547         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 548                                 "exynos-gsc.1", NULL),
 549         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 550                                 "exynos-gsc.2", NULL),
 551         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 552                                 "exynos-gsc.3", NULL),
 553 #ifdef CONFIG_VIDEO_FIMG2D4X
 554         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 555                                 "s5p-g2d", &fimg2d_data),
 556 #endif
 557         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 558                                 "exynos-ohci", &smdk5250_ohci_pdata),
 559         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 560                                 "s5p-ehci", &smdk5250_ehci_pdata),
 561         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 562                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 563         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 564                                 "samsung-i2s.0", &i2sv5_pdata),
 565         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 566                                 "exynos5-hdmi", NULL),
 567         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000, "s5p-mixer", NULL),
 568         {},
 569 };
 570
 571 static struct platform_device *smdk5250_devices[] __initdata = {
 572         &smdk5250_lcd, /* for platform_lcd device */
 573         &exynos_device_md0, /* for media device framework */
 574         &exynos_device_md1, /* for media device framework */
 575         &exynos_device_md2, /* for media device framework */
 576         &samsung_asoc_dma,  /* for audio dma interface device */
 577         &exynos_drm_device,
 578 };
 579
 580 static void __init exynos5250_dt_map_io(void)
 581 {
 582         exynos_init_io(NULL, 0);
 583         s3c24xx_init_clocks(24000000);
 584 }
 585
 586 static void __init exynos5_reserve(void)
 587 {
 588         /* required to have enough address range to remap the IOMMU
 589          * allocated buffers */
 590         init_consistent_dma_size(SZ_64M);
 591 }
 592
 593 static void s5p_tv_setup(void)
 594 {
 595         /* direct HPD to HDMI chip */
 596         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 597
 598         gpio_direction_input(EXYNOS5_GPX3(7));
 599         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 600         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 601 }
 602
 603 static void exynos5_i2c_setup(void)
 604 {
 605         /* Setup the low-speed i2c controller interrupts */
 606         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 607 }
 608
 609 static void __init exynos5250_dt_machine_init(void)
 610 {
 611         if (of_machine_is_compatible("samsung,smdk5250"))
 612                 smsc911x_init(1);
 613         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 614
 615         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 616                 "HOST_VBUS_CONTROL")) {
 617                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 618         } else {
 619                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 620                 gpio_free(EXYNOS5_GPX2(6));
 621         }
 622
 623         exynos5_i2c_setup();
 624
 625         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 626
 627         of_platform_populate(NULL, of_default_bus_match_table,
 628                                 exynos5250_auxdata_lookup, NULL);
 629
 630 #ifdef CONFIG_DRM_EXYNOS_FIMD
 631         exynos_fimd_gpio_setup_24bpp();
 632 #endif
 633         s5p_tv_setup();
 634
 635         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 636 }
 637
 638 static char const *exynos5250_dt_compat[] __initdata = {
 639         "samsung,exynos5250",
 640         NULL
 641 };
 642
 643 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 644         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 645         .init_irq       = exynos5_init_irq,
 646         .reserve        = exynos5_reserve,
 647         .map_io         = exynos5250_dt_map_io,
 648         .handle_irq     = gic_handle_irq,
 649         .init_machine   = exynos5250_dt_machine_init,
 650         .timer          = &exynos4_timer,
 651         .dt_compat      = exynos5250_dt_compat,
 652         .restart        = exynos5_restart,
 653 MACHINE_END