arch/arm/mach-exynos/mach-exynos5-dt.c

   1 /*
   2  * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_data/dwc3-exynos.h>
  15 #include <linux/regulator/fixed.h>
  16 #include <linux/regulator/machine.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/smsc911x.h>
  19 #include <linux/delay.h>
  20 #include <linux/i2c.h>
  21 #include <linux/pwm_backlight.h>
  22 #include <linux/mfd/wm8994/pdata.h>
  23 #include <linux/regulator/machine.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/hardware/gic.h>
  28 #include <mach/map.h>
  29 #include <mach/ohci.h>
  30 #include <mach/regs-pmu.h>
  31 #include <mach/sysmmu.h>
  32 #include <mach/ohci.h>
  33 #include <mach/regs-audss.h>
  34
  35 #include <plat/audio.h>
  36 #include <plat/cpu.h>
  37 #include <plat/dsim.h>
  38 #include <plat/fb.h>
  39 #include <plat/mipi_dsi.h>
  40 #include <plat/gpio-cfg.h>
  41 #include <plat/regs-fb.h>
  42 #include <plat/regs-serial.h>
  43 #include <plat/regs-srom.h>
  44 #include <plat/backlight.h>
  45 #include <plat/devs.h>
  46 #include <plat/usb-phy.h>
  47 #include <plat/ehci.h>
  48 #include <plat/dp.h>
  49 #include <plat/s3c64xx-spi.h>
  50
  51 #include <video/platform_lcd.h>
  52
  53 #include "drm/exynos_drm.h"
  54 #include "common.h"
  55
  56 static void __init smsc911x_init(int ncs)
  57 {
  58         u32 data;
  59
  60         /* configure nCS1 width to 16 bits */
  61         data = __raw_readl(S5P_SROM_BW) &
  62                 ~(S5P_SROM_BW__CS_MASK << (ncs * 4));
  63         data |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
  64                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
  65                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << (ncs * 4);
  66         __raw_writel(data, S5P_SROM_BW);
  67
  68         /* set timing for nCS1 suitable for ethernet chip */
  69         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
  70                 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
  71                 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
  72                 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
  73                 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
  74                 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
  75                 (0x1 << S5P_SROM_BCX__TACS__SHIFT),
  76                 S5P_SROM_BC0 + (ncs * 4));
  77 }
  78
  79 static struct s3c_fb_pd_win smdk5250_fb_win0 = {
  80         .win_mode = {
  81                 .left_margin    = 4,
  82                 .right_margin   = 4,
  83                 .upper_margin   = 4,
  84                 .lower_margin   = 4,
  85                 .hsync_len      = 4,
  86                 .vsync_len      = 4,
  87                 .xres           = 1280,
  88                 .yres           = 800,
  89         },
  90         .virtual_x              = 1280,
  91         .virtual_y              = 800 * 2,
  92         .width                  = 223,
  93         .height                 = 125,
  94         .max_bpp                = 32,
  95         .default_bpp            = 24,
  96 };
  97
  98 static struct s3c_fb_pd_win smdk5250_fb_win1 = {
  99         .win_mode = {
 100                 .left_margin    = 4,
 101                 .right_margin   = 4,
 102                 .upper_margin   = 4,
 103                 .lower_margin   = 4,
 104                 .hsync_len      = 4,
 105                 .vsync_len      = 4,
 106                 .xres           = 1280,
 107                 .yres           = 800,
 108         },
 109         .virtual_x              = 1280,
 110         .virtual_y              = 800 * 2,
 111         .width                  = 223,
 112         .height                 = 125,
 113         .max_bpp                = 32,
 114         .default_bpp            = 24,
 115 };
 116
 117 static struct s3c_fb_pd_win smdk5250_fb_win2 = {
 118         .win_mode = {
 119                 .left_margin    = 0x4,
 120                 .right_margin   = 0x4,
 121                 .upper_margin   = 4,
 122                 .lower_margin   = 4,
 123                 .hsync_len      = 4,
 124                 .vsync_len      = 4,
 125                 .xres           = 1280,
 126                 .yres           = 800,
 127         },
 128         .virtual_x              = 1280,
 129         .virtual_y              = 800 * 2,
 130         .width                  = 223,
 131         .height                 = 125,
 132         .max_bpp                = 32,
 133         .default_bpp            = 24,
 134 };
 135
 136 static struct fb_videomode snow_fb_window = {
 137         .left_margin    = 0x80,
 138         .right_margin   = 0x48,
 139         .upper_margin   = 14,
 140         .lower_margin   = 3,
 141         .hsync_len      = 5,
 142         .vsync_len      = 32,
 143         .xres           = 1366,
 144         .yres           = 768,
 145 };
 146
 147 static void exynos_fimd_gpio_setup_24bpp(void)
 148 {
 149         unsigned int reg = 0;
 150
 151         /*
 152          * Set DISP1BLK_CFG register for Display path selection
 153          * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15]
 154          * ---------------------
 155          * 0 | MIE/MDNIE
 156          * 1 | FIMD : selected
 157          */
 158         reg = __raw_readl(S3C_VA_SYS + 0x0214);
 159         reg &= ~(1 << 15);      /* To save other reset values */
 160         reg |= (1 << 15);
 161         __raw_writel(reg, S3C_VA_SYS + 0x0214);
 162 }
 163
 164 static void exynos_dp_gpio_setup_24bpp(void)
 165 {
 166         exynos_fimd_gpio_setup_24bpp();
 167
 168         /* Set Hotplug detect for DP */
 169         gpio_request(EXYNOS5_GPX0(7), "DP hotplug");
 170         s3c_gpio_cfgpin(EXYNOS5_GPX0(7), S3C_GPIO_SFN(3));
 171 }
 172
 173 #ifdef CONFIG_DRM_EXYNOS_FIMD
 174 static struct exynos_drm_fimd_pdata smdk5250_lcd1_pdata = {
 175         .panel.timing   = {
 176                 .xres           = 1280,
 177                 .yres           = 800,
 178                 .hsync_len      = 4,
 179                 .left_margin    = 0x4,
 180                 .right_margin   = 0x4,
 181                 .vsync_len      = 4,
 182                 .upper_margin   = 4,
 183                 .lower_margin   = 4,
 184                 .refresh        = 60,
 185         },
 186         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 187         .vidcon1        = VIDCON1_INV_VCLK,
 188         .default_win    = 0,
 189         .bpp            = 32,
 190         .clock_rate     = 800 * 1000 * 1000,
 191 };
 192 #else
 193 static struct s3c_fb_platdata smdk5250_lcd1_pdata __initdata = {
 194         .win[0]         = &smdk5250_fb_win0,
 195         .win[1]         = &smdk5250_fb_win1,
 196         .win[2]         = &smdk5250_fb_win2,
 197         .default_win    = 0,
 198         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 199         .vidcon1        = VIDCON1_INV_VCLK,
 200         .setup_gpio     = exynos_fimd_gpio_setup_24bpp,
 201         .clock_rate     = 800 * 1000 * 1000,
 202 };
 203 #endif
 204
 205 static struct mipi_dsim_config dsim_info = {
 206         .e_interface            = DSIM_VIDEO,
 207         .e_pixel_format         = DSIM_24BPP_888,
 208         /* main frame fifo auto flush at VSYNC pulse */
 209         .auto_flush             = false,
 210         .eot_disable            = false,
 211         .auto_vertical_cnt      = false,
 212         .hse                    = false,
 213         .hfp                    = false,
 214         .hbp                    = false,
 215         .hsa                    = false,
 216
 217         .e_no_data_lane         = DSIM_DATA_LANE_4,
 218         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 219         .e_burst_mode           = DSIM_BURST,
 220
 221         .p                      = 3,
 222         .m                      = 115,
 223         .s                      = 1,
 224
 225         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 226         .pll_stable_time        = 500,
 227
 228         .esc_clk                = 0.4 * 1000000, /* escape clk : 10MHz */
 229
 230         /* stop state holding counter after bta change count 0 ~ 0xfff */
 231         .stop_holding_cnt       = 0x0f,
 232         .bta_timeout            = 0xff,         /* bta timeout 0 ~ 0xff */
 233         .rx_timeout             = 0xffff,       /* lp rx timeout 0 ~ 0xffff */
 234
 235         .dsim_ddi_pd = &tc358764_mipi_lcd_driver,
 236 };
 237
 238 static struct mipi_dsim_lcd_config dsim_lcd_info = {
 239         .rgb_timing.left_margin         = 0x4,
 240         .rgb_timing.right_margin        = 0x4,
 241         .rgb_timing.upper_margin        = 0x4,
 242         .rgb_timing.lower_margin        =  0x4,
 243         .rgb_timing.hsync_len           = 0x4,
 244         .rgb_timing.vsync_len           = 0x4,
 245         .cpu_timing.cs_setup            = 0,
 246         .cpu_timing.wr_setup            = 1,
 247         .cpu_timing.wr_act              = 0,
 248         .cpu_timing.wr_hold             = 0,
 249         .lcd_size.width                 = 1280,
 250         .lcd_size.height                = 800,
 251 };
 252
 253 static struct s5p_platform_mipi_dsim dsim_platform_data = {
 254         .clk_name               = "dsim0",
 255         .dsim_config            = &dsim_info,
 256         .dsim_lcd_config        = &dsim_lcd_info,
 257
 258         .part_reset             = s5p_dsim_part_reset,
 259         .init_d_phy             = s5p_dsim_init_d_phy,
 260         .get_fb_frame_done      = NULL,
 261         .trigger                = NULL,
 262
 263         /*
 264          * the stable time of needing to write data on SFR
 265          * when the mipi mode becomes LP mode.
 266          */
 267         .delay_for_stabilization = 600,
 268 };
 269
 270 static struct platform_device exynos_drm_device = {
 271         .name           = "exynos-drm",
 272         .dev = {
 273                 .dma_mask = &exynos_drm_device.dev.coherent_dma_mask,
 274                 .coherent_dma_mask = 0xffffffffUL,
 275         }
 276 };
 277
 278 static void lcd_set_power(struct plat_lcd_data *pd,
 279                         unsigned int power)
 280 {
 281         if (of_machine_is_compatible("google,daisy") ||
 282                         of_machine_is_compatible("google,snow")) {
 283                 struct regulator *lcd_fet;
 284
 285                 lcd_fet = regulator_get(NULL, "lcd_vdd");
 286                 if (!IS_ERR(lcd_fet)) {
 287                         if (power)
 288                                 regulator_enable(lcd_fet);
 289                         else
 290                                 regulator_disable(lcd_fet);
 291
 292                         regulator_put(lcd_fet);
 293                 }
 294         }
 295
 296         if (!of_machine_is_compatible("google,snow")) {
 297                 /* reset */
 298                 gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH, "GPX1");
 299                 mdelay(20);
 300                 gpio_set_value(EXYNOS5_GPX1(5), 0);
 301                 mdelay(20);
 302                 gpio_set_value(EXYNOS5_GPX1(5), 1);
 303                 mdelay(20);
 304                 gpio_free(EXYNOS5_GPX1(5));
 305                 mdelay(20);
 306         }
 307
 308
 309         /* Turn on regulator for backlight */
 310         if (of_machine_is_compatible("google,daisy") ||
 311                         of_machine_is_compatible("google,snow")) {
 312                 struct regulator *backlight_fet;
 313
 314                 backlight_fet = regulator_get(NULL, "vcd_led");
 315                 if (!IS_ERR(backlight_fet)) {
 316                         if (power)
 317                                 regulator_enable(backlight_fet);
 318                         else
 319                                 regulator_disable(backlight_fet);
 320
 321                         regulator_put(backlight_fet);
 322                 }
 323                 /* Wait 10 ms between regulator on and PWM start per spec */
 324                 mdelay(10);
 325         }
 326
 327         /*
 328          * Request lcd_bl_en GPIO for smdk5250_bl_notify().
 329          * TODO: Fix this so we are not at risk of requesting the GPIO
 330          * multiple times, this should be done with device tree, and
 331          * likely integrated into the plat-samsung/dev-backlight.c init.
 332          */
 333         gpio_request_one(EXYNOS5_GPX3(0), GPIOF_OUT_INIT_LOW, "GPX3");
 334 }
 335
 336 static int smdk5250_match_fb(struct plat_lcd_data *pd, struct fb_info *info)
 337 {
 338         /* Don't call .set_power callback while unblanking */
 339         return 0;
 340 }
 341
 342 static struct plat_lcd_data smdk5250_lcd_data = {
 343         .set_power      = lcd_set_power,
 344         .match_fb       = smdk5250_match_fb,
 345 };
 346
 347 static struct platform_device smdk5250_lcd = {
 348         .name                   = "platform-lcd",
 349         .dev.platform_data      = &smdk5250_lcd_data,
 350 };
 351
 352 static int smdk5250_bl_notify(struct device *unused, int brightness)
 353 {
 354         /* manage lcd_bl_en signal */
 355         if (brightness)
 356                 gpio_set_value(EXYNOS5_GPX3(0), 1);
 357         else
 358                 gpio_set_value(EXYNOS5_GPX3(0), 0);
 359
 360         return brightness;
 361 }
 362
 363 /* LCD Backlight data */
 364 static struct samsung_bl_gpio_info smdk5250_bl_gpio_info = {
 365         .no     = EXYNOS5_GPB2(0),
 366         .func   = S3C_GPIO_SFN(2),
 367 };
 368
 369 static struct platform_pwm_backlight_data smdk5250_bl_data = {
 370         .pwm_period_ns  = 1000000,
 371         .notify         = smdk5250_bl_notify,
 372 };
 373
 374 struct platform_device exynos_device_md0 = {
 375         .name = "exynos-mdev",
 376         .id = 0,
 377 };
 378
 379 struct platform_device exynos_device_md1 = {
 380         .name = "exynos-mdev",
 381         .id = 1,
 382 };
 383
 384 struct platform_device exynos_device_md2 = {
 385         .name = "exynos-mdev",
 386         .id = 2,
 387 };
 388
 389 static struct regulator_consumer_supply wm8994_avdd1_supply =
 390         REGULATOR_SUPPLY("AVDD1", "1-001a");
 391
 392 static struct regulator_consumer_supply wm8994_dcvdd_supply =
 393         REGULATOR_SUPPLY("DCVDD", "1-001a");
 394
 395 static struct regulator_init_data wm8994_ldo1_data = {
 396         .constraints    = {
 397                 .name           = "AVDD1",
 398         },
 399         .num_consumer_supplies  = 1,
 400         .consumer_supplies      = &wm8994_avdd1_supply,
 401 };
 402
 403 static struct regulator_init_data wm8994_ldo2_data = {
 404         .constraints    = {
 405         .name                   = "DCVDD",
 406                 },
 407         .num_consumer_supplies  = 1,
 408         .consumer_supplies      = &wm8994_dcvdd_supply,
 409 };
 410
 411 static struct wm8994_pdata wm8994_platform_data = {
 412         /* configure gpio1 function: 0x0001(Logic level input/output) */
 413         .gpio_defaults[0] = 0x0001,
 414         /* If the i2s0 and i2s2 is enabled simultaneously */
 415         .gpio_defaults[7] = 0x8100, /* GPIO8  DACDAT3 in */
 416         .gpio_defaults[8] = 0x0100, /* GPIO9  ADCDAT3 out */
 417         .gpio_defaults[9] = 0x0100, /* GPIO10 LRCLK3  out */
 418         .gpio_defaults[10] = 0x0100,/* GPIO11 BCLK3   out */
 419         .ldo[0] = { 0, &wm8994_ldo1_data },
 420         .ldo[1] = { 0, &wm8994_ldo2_data },
 421 };
 422
 423 static struct i2c_board_info i2c_devs1[] __initdata = {
 424         {
 425                 I2C_BOARD_INFO("wm8994", 0x1a),
 426                 .platform_data  = &wm8994_platform_data,
 427         },
 428 };
 429
 430 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 431         [0] = {
 432                 .line           = EXYNOS5_GPA2(5),
 433                 .fb_delay       = 0x2,
 434         },
 435 };
 436
 437 static struct spi_board_info spi1_board_info[] __initdata = {
 438         {
 439                 .modalias               = "spidev",
 440                 .platform_data          = NULL,
 441                 .max_speed_hz           = 10*1000*1000,
 442                 .bus_num                = 1,
 443                 .chip_select            = 0,
 444                 .mode                   = SPI_MODE_0,
 445                 .controller_data        = spi1_csi,
 446         }
 447 };
 448
 449 struct sysmmu_platform_data platdata_sysmmu_mfc_l = {
 450         .dbgname = "mfc_l",
 451         .clockname = "sysmmu",
 452 };
 453
 454 struct sysmmu_platform_data platdata_sysmmu_mfc_r = {
 455         .dbgname = "mfc_r",
 456         .clockname = "sysmmu",
 457 };
 458
 459 struct sysmmu_platform_data platdata_sysmmu_gsc = {
 460         .dbgname = "gsc",
 461         .clockname = "sysmmu",
 462 };
 463
 464 struct sysmmu_platform_data platdata_sysmmu_g2d = {
 465         .dbgname = "g2d",
 466         .clockname = "sysmmu",
 467 };
 468
 469 struct sysmmu_platform_data platdata_sysmmu_fimd = {
 470         .dbgname = "fimd",
 471         .clockname = "sysmmu",
 472 };
 473
 474 struct sysmmu_platform_data platdata_sysmmu_tv = {
 475         .dbgname = "tv",
 476         .clockname = "sysmmu",
 477 };
 478
 479 #ifdef CONFIG_VIDEO_FIMG2D4X
 480 static struct fimg2d_platdata fimg2d_data __initdata = {
 481         .hw_ver         = 0x42,
 482         .gate_clkname   = "fimg2d",
 483 };
 484 #endif
 485
 486 static struct exynos4_ohci_platdata smdk5250_ohci_pdata = {
 487         .phy_init = s5p_usb_phy_init,
 488         .phy_exit = s5p_usb_phy_exit,
 489 };
 490
 491 static struct s5p_ehci_platdata smdk5250_ehci_pdata = {
 492         .phy_init = s5p_usb_phy_init,
 493         .phy_exit = s5p_usb_phy_exit,
 494 };
 495
 496 static struct dwc3_exynos_data smdk5250_xhci_pdata = {
 497         .phy_type = S5P_USB_PHY_DRD,
 498         .phy_init = s5p_usb_phy_init,
 499         .phy_exit = s5p_usb_phy_exit,
 500 };
 501
 502 struct exynos_gpio_cfg {
 503         unsigned int    addr;
 504         unsigned int    num;
 505         unsigned int    bit;
 506 };
 507
 508 static const char *rclksrc[] = {
 509         [0] = "busclk",
 510         [1] = "i2sclk",
 511 };
 512
 513 static struct video_info smdk5250_dp_config = {
 514         .name                   = "eDP-LVDS NXP PTN3460",
 515
 516         .h_sync_polarity        = 0,
 517         .v_sync_polarity        = 0,
 518         .interlaced             = 0,
 519
 520         .color_space            = COLOR_RGB,
 521         .dynamic_range          = VESA,
 522         .ycbcr_coeff            = COLOR_YCBCR601,
 523         .color_depth            = COLOR_8,
 524
 525         .link_rate              = LINK_RATE_2_70GBPS,
 526         .lane_count             = LANE_COUNT2,
 527 };
 528
 529 static struct exynos_dp_platdata smdk5250_dp_data __initdata = {
 530         .video_info     = &smdk5250_dp_config,
 531         .training_type  = HW_LINK_TRAINING,
 532         .phy_init       = s5p_dp_phy_init,
 533         .phy_exit       = s5p_dp_phy_exit,
 534 };
 535
 536 #define S5P_PMU_DEBUG                           S5P_PMUREG(0x0A00)
 537 /* PMU_DEBUG bits [12:8] = 0x10000 selects XXTI clock source */
 538 #define PMU_DEBUG_XXTI                          (0x10 << 8)
 539 /* Mask bit[12:8] for xxti clock selection */
 540 #define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
 541
 542 static void __init enable_xclkout(void)
 543 {
 544        unsigned int tmp;
 545
 546        tmp = readl(S5P_PMU_DEBUG);
 547        tmp &= ~PMU_DEBUG_CLKOUT_SEL_MASK;
 548        tmp |= PMU_DEBUG_XXTI;
 549        writel(tmp, S5P_PMU_DEBUG);
 550 }
 551
 552 static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
 553 {
 554         int id;
 555         /* configure GPIO for i2s port */
 556         struct exynos_gpio_cfg exynos5_cfg[3] = {
 557                 { EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },
 558                 { EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
 559                 { EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
 560         };
 561
 562         if (pdev->dev.of_node) {
 563                 id = of_alias_get_id(pdev->dev.of_node, "i2s");
 564                 if (id < 0)
 565                         dev_err(&pdev->dev, "failed to get alias id:%d\n", id);
 566         } else {
 567                 id = pdev->id;
 568         }
 569
 570         if (id < 0 || id > 2) {
 571                 printk(KERN_ERR "Invalid Device %d\n", id);
 572                 return -EINVAL;
 573         }
 574
 575         s3c_gpio_cfgpin_range(exynos5_cfg[id].addr,
 576                 exynos5_cfg[id].num, exynos5_cfg[id].bit);
 577
 578         return 0;
 579 }
 580
 581 static struct s3c_audio_pdata i2sv5_pdata = {
 582         .cfg_gpio = exynos_cfg_i2s_gpio,
 583         .type = {
 584                 .i2s = {
 585                         .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
 586                                          | QUIRK_NEED_RSTCLR,
 587                         .src_clk = rclksrc,
 588                         .idma_addr = EXYNOS4_AUDSS_INT_MEM,
 589                 },
 590         },
 591 };
 592 /*
 593  * The following lookup table is used to override device names when devices
 594  * are registered from device tree. This is temporarily added to enable
 595  * device tree support addition for the EXYNOS5 architecture.
 596  *
 597  * For drivers that require platform data to be provided from the machine
 598  * file, a platform data pointer can also be supplied along with the
 599  * devices names. Usually, the platform data elements that cannot be parsed
 600  * from the device tree by the drivers (example: function pointers) are
 601  * supplied. But it should be noted that this is a temporary mechanism and
 602  * at some point, the drivers should be capable of parsing all the platform
 603  * data from the device tree.
 604  */
 605 static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 606         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
 607                                 "exynos4210-uart.0", NULL),
 608         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
 609                                 "exynos4210-uart.1", NULL),
 610         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
 611                                 "exynos4210-uart.2", NULL),
 612         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 613                                 "exynos4210-uart.3", NULL),
 614         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
 615                                 "s3c2440-i2c.0", NULL),
 616         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 617                                 "s3c2440-i2c.1", NULL),
 618         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
 619                                 "s3c2440-i2c.2", NULL),
 620         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
 621                                 "s3c2440-i2c.3", NULL),
 622         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
 623                                 "s3c2440-i2c.4", NULL),
 624         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
 625                                 "s3c2440-i2c.5", NULL),
 626         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
 627                                 "s3c2440-i2c.6", NULL),
 628         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
 629                                 "s3c2440-i2c.7", NULL),
 630         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(8),
 631                                 "s3c2440-hdmiphy-i2c", NULL),
 632         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 633                                 "exynos4210-spi.0", NULL),
 634         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
 635                                 "exynos4210-spi.1", NULL),
 636         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
 637                                 "exynos4210-spi.2", NULL),
 638         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12200000,
 639                                 "dw_mmc.0", NULL),
 640         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12210000,
 641                                 "dw_mmc.1", NULL),
 642         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12220000,
 643                                 "dw_mmc.2", NULL),
 644         OF_DEV_AUXDATA("synopsis,dw-mshc-exynos5250", 0x12230000,
 645                                 "dw_mmc.3", NULL),
 646         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 647         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
 648         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
 649         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x10A60000,
 650                                 "s5p-sysmmu.2", &platdata_sysmmu_g2d),
 651         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11210000,
 652                                 "s5p-sysmmu.3", &platdata_sysmmu_mfc_l),
 653         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x11200000,
 654                                 "s5p-sysmmu.4", &platdata_sysmmu_mfc_r),
 655         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14640000,
 656                                 "s5p-sysmmu.27", &platdata_sysmmu_fimd),
 657         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x14650000,
 658                                 "s5p-sysmmu.28", &platdata_sysmmu_tv),
 659         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E80000,
 660                                 "s5p-sysmmu.23", &platdata_sysmmu_gsc),
 661         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13E90000,
 662                                 "s5p-sysmmu.24", &platdata_sysmmu_gsc),
 663         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EA0000,
 664                                 "s5p-sysmmu.25", &platdata_sysmmu_gsc),
 665         OF_DEV_AUXDATA("samsung,s5p-sysmmu", 0x13EB0000,
 666                                 "s5p-sysmmu.26", &platdata_sysmmu_gsc),
 667         OF_DEV_AUXDATA("samsung,exynos5-fb", 0x14400000,
 668                                 "exynos5-fb", &smdk5250_lcd1_pdata),
 669         OF_DEV_AUXDATA("samsung,exynos5-mipi", 0x14500000,
 670                                 "s5p-mipi-dsim", &dsim_platform_data),
 671         OF_DEV_AUXDATA("samsung,exynos5-dp", 0x145B0000,
 672                                 "s5p-dp", &smdk5250_dp_data),
 673         OF_DEV_AUXDATA("samsung,s5p-mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
 674         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E00000,
 675                                 "exynos-gsc.0", NULL),
 676         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E10000,
 677                                 "exynos-gsc.1", NULL),
 678         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E20000,
 679                                 "exynos-gsc.2", NULL),
 680         OF_DEV_AUXDATA("samsung,exynos-gsc", 0x13E30000,
 681                                 "exynos-gsc.3", NULL),
 682 #ifdef CONFIG_VIDEO_FIMG2D4X
 683         OF_DEV_AUXDATA("samsung,s5p-g2d", 0x10850000,
 684                                 "s5p-g2d", &fimg2d_data),
 685 #endif
 686         OF_DEV_AUXDATA("samsung,exynos-ohci", 0x12120000,
 687                                 "exynos-ohci", &smdk5250_ohci_pdata),
 688         OF_DEV_AUXDATA("samsung,exynos-ehci", 0x12110000,
 689                                 "s5p-ehci", &smdk5250_ehci_pdata),
 690         OF_DEV_AUXDATA("samsung,exynos-xhci", 0x12000000,
 691                                 "exynos-dwc3", &smdk5250_xhci_pdata),
 692         OF_DEV_AUXDATA("samsung,i2s", 0x03830000,
 693                                 "samsung-i2s.0", &i2sv5_pdata),
 694         OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
 695                                 "exynos5-hdmi", NULL),
 696         OF_DEV_AUXDATA("samsung,s5p-mixer", 0x14450000, "s5p-mixer", NULL),
 697         {},
 698 };
 699
 700 static struct platform_device *smdk5250_devices[] __initdata = {
 701         &smdk5250_lcd, /* for platform_lcd device */
 702         &exynos_device_md0, /* for media device framework */
 703         &exynos_device_md1, /* for media device framework */
 704         &exynos_device_md2, /* for media device framework */
 705         &samsung_asoc_dma,  /* for audio dma interface device */
 706         &exynos_drm_device,
 707 };
 708
 709 static struct regulator_consumer_supply dummy_supplies[] = {
 710         REGULATOR_SUPPLY("vddvario", "7000000.lan9215"),
 711         REGULATOR_SUPPLY("vdd33a", "7000000.lan9215"),
 712 };
 713
 714 static void __init exynos5250_dt_map_io(void)
 715 {
 716         exynos_init_io(NULL, 0);
 717         s3c24xx_init_clocks(24000000);
 718 }
 719
 720 static void __init exynos5_reserve(void)
 721 {
 722         /* required to have enough address range to remap the IOMMU
 723          * allocated buffers */
 724         init_consistent_dma_size(SZ_64M);
 725 }
 726
 727 static void s5p_tv_setup(void)
 728 {
 729         /* direct HPD to HDMI chip */
 730         gpio_request(EXYNOS5_GPX3(7), "hpd-plug");
 731
 732         gpio_direction_input(EXYNOS5_GPX3(7));
 733         s3c_gpio_cfgpin(EXYNOS5_GPX3(7), S3C_GPIO_SFN(0x3));
 734         s3c_gpio_setpull(EXYNOS5_GPX3(7), S3C_GPIO_PULL_NONE);
 735 }
 736
 737 static void exynos5_i2c_setup(void)
 738 {
 739         /* Setup the low-speed i2c controller interrupts */
 740         writel(0x0, EXYNOS5_SYS_I2C_CFG);
 741 }
 742
 743 static void __init exynos5250_dt_machine_init(void)
 744 {
 745         struct device_node *srom_np, *np;
 746         int ret;
 747
 748         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 749
 750         /* Setup pins for any SMSC 911x controller on the SROMC bus */
 751         srom_np = of_find_node_by_path("/sromc-bus");
 752         if (!srom_np) {
 753                 printk(KERN_ERR "No /sromc-bus property.\n");
 754                 goto out;
 755         }
 756         for_each_child_of_node(srom_np, np) {
 757                 if (of_device_is_compatible(np, "smsc,lan9115")) {
 758                         u32 reg;
 759                         of_property_read_u32(np, "reg", &reg);
 760                         smsc911x_init(reg);
 761                 }
 762         }
 763
 764         samsung_bl_set(&smdk5250_bl_gpio_info, &smdk5250_bl_data);
 765
 766         /*
 767          * HACK ALERT! TODO: FIXME!
 768          *
 769          * We're going to hack in Daisy LCD info here for bringup purposes.
 770          * Lots of things wrong with what we're doing here, but it works for
 771          * bringup purposes.
 772          */
 773
 774         if (of_machine_is_compatible("google,daisy")) {
 775 #ifdef CONFIG_DRM_EXYNOS_FIMD
 776                 smdk5250_lcd1_pdata.panel.timing.xres = 1366;
 777                 smdk5250_lcd1_pdata.panel.timing.yres = 768;
 778                 smdk5250_lcd1_pdata.panel_type = MIPI_LCD;
 779 #else
 780                 smdk5250_fb_win0.win_mode.xres = 1366;
 781                 smdk5250_fb_win0.win_mode.yres = 768;
 782                 smdk5250_fb_win0.virtual_x = 1366;
 783                 smdk5250_fb_win0.virtual_y = 768 * 2;
 784
 785                 smdk5250_fb_win1.win_mode.xres = 1366;
 786                 smdk5250_fb_win1.win_mode.yres = 768;
 787                 smdk5250_fb_win1.virtual_x = 1366;
 788                 smdk5250_fb_win1.virtual_y = 768 * 2;
 789
 790                 smdk5250_fb_win2.win_mode.xres = 1366;
 791                 smdk5250_fb_win2.win_mode.yres = 768;
 792                 smdk5250_fb_win2.virtual_x = 1366;
 793                 smdk5250_fb_win2.virtual_y = 768 * 2;
 794 #endif
 795                 dsim_lcd_info.lcd_size.width = 1366;
 796                 dsim_lcd_info.lcd_size.height = 768;
 797         } else if (of_machine_is_compatible("google,snow")) {
 798 #ifdef CONFIG_DRM_EXYNOS_FIMD
 799                 smdk5250_lcd1_pdata.panel.timing = snow_fb_window;
 800                 smdk5250_lcd1_pdata.panel_type = DP_LCD;
 801                 smdk5250_lcd1_pdata.clock_rate = 267 * 1000 * 1000;
 802                 smdk5250_lcd1_pdata.vidcon1 = 0;
 803 #endif
 804                 ret = gpio_request_one(EXYNOS5_GPX1(5), GPIOF_OUT_INIT_HIGH,
 805                                         "DP_PD_N");
 806                 WARN_ON(ret);
 807         }
 808
 809         if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
 810                 "HOST_VBUS_CONTROL")) {
 811                 printk(KERN_ERR "failed to request gpio_host_vbus\n");
 812         } else {
 813                 s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
 814                 gpio_free(EXYNOS5_GPX2(6));
 815         }
 816
 817         exynos5_i2c_setup();
 818
 819         /*
 820          * BIG HACK: The wm8994 is not device tree enabled apparently, so
 821          * needs to be added manually.  ...but it's only on SMDK5250.
 822          */
 823         if (of_machine_is_compatible("samsung,smdk5250")) {
 824                 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 825         }
 826
 827         /* XCLKOUT needs to be moved over to the clock interface, but enable it
 828          * here for now.
 829          */
 830         enable_xclkout();
 831
 832         if (gpio_request_one(EXYNOS5_GPA2(5), GPIOF_OUT_INIT_HIGH, "SPI1_CS")) {
 833                 printk(KERN_ERR "Spidev ChipSelect unavailable\n");
 834         } else {
 835                 s3c_gpio_cfgpin(EXYNOS5_GPA2(5), S3C_GPIO_SFN(0x1));
 836                 s3c_gpio_setpull(EXYNOS5_GPA2(5), S3C_GPIO_PULL_NONE);
 837                 s5p_gpio_set_drvstr(EXYNOS5_GPA2(5), S5P_GPIO_DRVSTR_LV4);
 838                 spi_register_board_info(spi1_board_info,
 839                                         ARRAY_SIZE(spi1_board_info));
 840         }
 841
 842         of_platform_populate(NULL, of_default_bus_match_table,
 843                                 exynos5250_auxdata_lookup, NULL);
 844
 845 #ifdef CONFIG_DRM_EXYNOS_FIMD
 846         if (of_machine_is_compatible("google,snow"))
 847                 exynos_dp_gpio_setup_24bpp();
 848         else
 849                 exynos_fimd_gpio_setup_24bpp();
 850 #endif
 851         s5p_tv_setup();
 852
 853         platform_add_devices(smdk5250_devices, ARRAY_SIZE(smdk5250_devices));
 854 out:
 855         of_node_put(srom_np);
 856         return;
 857 }
 858
 859 static char const *exynos5250_dt_compat[] __initdata = {
 860         "samsung,exynos5250",
 861         NULL
 862 };
 863
 864 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
 865         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 866         .init_irq       = exynos5_init_irq,
 867         .reserve        = exynos5_reserve,
 868         .map_io         = exynos5250_dt_map_io,
 869         .handle_irq     = gic_handle_irq,
 870         .init_machine   = exynos5250_dt_machine_init,
 871         .timer          = &exynos4_timer,
 872         .dt_compat      = exynos5250_dt_compat,
 873         .restart        = exynos5_restart,
 874 MACHINE_END