arch/arm/mach-exynos/suspend.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Suspend support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irqchip/arm-gic.h>
  22 #include <linux/err.h>
  23 #include <linux/regulator/machine.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27 #include <asm/firmware.h>
  28 #include <asm/mcpm.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/suspend.h>
  31
  32 #include <plat/pm-common.h>
  33 #include <plat/regs-srom.h>
  34
  35 #include "common.h"
  36 #include "regs-pmu.h"
  37 #include "regs-sys.h"
  38 #include "exynos-pmu.h"
  39
  40 #define S5P_CHECK_SLEEP 0x00000BAD
  41
  42 #define REG_TABLE_END (-1U)
  43
  44 #define EXYNOS5420_CPU_STATE    0x28
  45
  46 /**
  47  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  48  * @hwirq: Hardware IRQ signal of the GIC
  49  * @mask: Mask in PMU wake-up mask register
  50  */
  51 struct exynos_wkup_irq {
  52         unsigned int hwirq;
  53         u32 mask;
  54 };
  55
  56 static struct sleep_save exynos5_sys_save[] = {
  57         SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  58 };
  59
  60 static struct sleep_save exynos_core_save[] = {
  61         /* SROM side */
  62         SAVE_ITEM(S5P_SROM_BW),
  63         SAVE_ITEM(S5P_SROM_BC0),
  64         SAVE_ITEM(S5P_SROM_BC1),
  65         SAVE_ITEM(S5P_SROM_BC2),
  66         SAVE_ITEM(S5P_SROM_BC3),
  67 };
  68
  69 struct exynos_pm_data {
  70         const struct exynos_wkup_irq *wkup_irq;
  71         struct sleep_save *extra_save;
  72         int num_extra_save;
  73         unsigned int wake_disable_mask;
  74         unsigned int *release_ret_regs;
  75
  76         void (*pm_prepare)(void);
  77         void (*pm_resume_prepare)(void);
  78         void (*pm_resume)(void);
  79         int (*pm_suspend)(void);
  80         int (*cpu_suspend)(unsigned long);
  81 };
  82
  83 struct exynos_pm_data *pm_data;
  84
  85 static int exynos5420_cpu_state;
  86 static unsigned int exynos_pmu_spare3;
  87
  88 /*
  89  * GIC wake-up support
  90  */
  91
  92 static u32 exynos_irqwake_intmask = 0xffffffff;
  93
  94 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  95         { 73, BIT(1) }, /* RTC alarm */
  96         { 74, BIT(2) }, /* RTC tick */
  97         { /* sentinel */ },
  98 };
  99
 100 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
 101         { 76, BIT(1) }, /* RTC alarm */
 102         { 77, BIT(2) }, /* RTC tick */
 103         { /* sentinel */ },
 104 };
 105
 106 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
 107         { 75, BIT(1) }, /* RTC alarm */
 108         { 76, BIT(2) }, /* RTC tick */
 109         { /* sentinel */ },
 110 };
 111
 112 unsigned int exynos_release_ret_regs[] = {
 113         S5P_PAD_RET_MAUDIO_OPTION,
 114         S5P_PAD_RET_GPIO_OPTION,
 115         S5P_PAD_RET_UART_OPTION,
 116         S5P_PAD_RET_MMCA_OPTION,
 117         S5P_PAD_RET_MMCB_OPTION,
 118         S5P_PAD_RET_EBIA_OPTION,
 119         S5P_PAD_RET_EBIB_OPTION,
 120         REG_TABLE_END,
 121 };
 122
 123 unsigned int exynos3250_release_ret_regs[] = {
 124         S5P_PAD_RET_MAUDIO_OPTION,
 125         S5P_PAD_RET_GPIO_OPTION,
 126         S5P_PAD_RET_UART_OPTION,
 127         S5P_PAD_RET_MMCA_OPTION,
 128         S5P_PAD_RET_MMCB_OPTION,
 129         S5P_PAD_RET_EBIA_OPTION,
 130         S5P_PAD_RET_EBIB_OPTION,
 131         S5P_PAD_RET_MMC2_OPTION,
 132         S5P_PAD_RET_SPI_OPTION,
 133         REG_TABLE_END,
 134 };
 135
 136 unsigned int exynos5420_release_ret_regs[] = {
 137         EXYNOS_PAD_RET_DRAM_OPTION,
 138         EXYNOS_PAD_RET_MAUDIO_OPTION,
 139         EXYNOS_PAD_RET_JTAG_OPTION,
 140         EXYNOS5420_PAD_RET_GPIO_OPTION,
 141         EXYNOS5420_PAD_RET_UART_OPTION,
 142         EXYNOS5420_PAD_RET_MMCA_OPTION,
 143         EXYNOS5420_PAD_RET_MMCB_OPTION,
 144         EXYNOS5420_PAD_RET_MMCC_OPTION,
 145         EXYNOS5420_PAD_RET_HSI_OPTION,
 146         EXYNOS_PAD_RET_EBIA_OPTION,
 147         EXYNOS_PAD_RET_EBIB_OPTION,
 148         EXYNOS5420_PAD_RET_SPI_OPTION,
 149         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 150         REG_TABLE_END,
 151 };
 152
 153 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 154 {
 155         const struct exynos_wkup_irq *wkup_irq;
 156
 157         if (!pm_data->wkup_irq)
 158                 return -ENOENT;
 159         wkup_irq = pm_data->wkup_irq;
 160
 161         while (wkup_irq->mask) {
 162                 if (wkup_irq->hwirq == data->hwirq) {
 163                         if (!state)
 164                                 exynos_irqwake_intmask |= wkup_irq->mask;
 165                         else
 166                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 167                         return 0;
 168                 }
 169                 ++wkup_irq;
 170         }
 171
 172         return -ENOENT;
 173 }
 174
 175 static int exynos_cpu_do_idle(void)
 176 {
 177         /* issue the standby signal into the pm unit. */
 178         cpu_do_idle();
 179
 180         pr_info("Failed to suspend the system\n");
 181         return 1; /* Aborting suspend */
 182 }
 183 static void exynos_flush_cache_all(void)
 184 {
 185         flush_cache_all();
 186         outer_flush_all();
 187 }
 188
 189 static int exynos_cpu_suspend(unsigned long arg)
 190 {
 191         exynos_flush_cache_all();
 192         return exynos_cpu_do_idle();
 193 }
 194
 195 static int exynos3250_cpu_suspend(unsigned long arg)
 196 {
 197         flush_cache_all();
 198         return exynos_cpu_do_idle();
 199 }
 200
 201 static int exynos5420_cpu_suspend(unsigned long arg)
 202 {
 203         /* MCPM works with HW CPU identifiers */
 204         unsigned int mpidr = read_cpuid_mpidr();
 205         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 206         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 207
 208         __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 209
 210         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 211                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 212
 213                 /*
 214                  * Residency value passed to mcpm_cpu_suspend back-end
 215                  * has to be given clear semantics. Set to 0 as a
 216                  * temporary value.
 217                  */
 218                 mcpm_cpu_suspend(0);
 219         }
 220
 221         pr_info("Failed to suspend the system\n");
 222
 223         /* return value != 0 means failure */
 224         return 1;
 225 }
 226
 227 static void exynos_pm_set_wakeup_mask(void)
 228 {
 229         /* Set wake-up mask registers */
 230         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 231         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 232 }
 233
 234 static void exynos_pm_enter_sleep_mode(void)
 235 {
 236         /* Set value of power down register for sleep mode */
 237         exynos_sys_powerdown_conf(SYS_SLEEP);
 238         pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 239 }
 240
 241 static void exynos_pm_prepare(void)
 242 {
 243         /* Set wake-up mask registers */
 244         exynos_pm_set_wakeup_mask();
 245
 246         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 247
 248          if (pm_data->extra_save)
 249                 s3c_pm_do_save(pm_data->extra_save,
 250                                 pm_data->num_extra_save);
 251
 252         exynos_pm_enter_sleep_mode();
 253
 254         /* ensure at least INFORM0 has the resume address */
 255         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 256 }
 257
 258 static void exynos3250_pm_prepare(void)
 259 {
 260         unsigned int tmp;
 261
 262         /* Set wake-up mask registers */
 263         exynos_pm_set_wakeup_mask();
 264
 265         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 266         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 267         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 268
 269         exynos_pm_enter_sleep_mode();
 270
 271         /* ensure at least INFORM0 has the resume address */
 272         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 273 }
 274
 275 static void exynos5420_pm_prepare(void)
 276 {
 277         unsigned int tmp;
 278
 279         /* Set wake-up mask registers */
 280         exynos_pm_set_wakeup_mask();
 281
 282         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 283
 284         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 285         /*
 286          * The cpu state needs to be saved and restored so that the
 287          * secondary CPUs will enter low power start. Though the U-Boot
 288          * is setting the cpu state with low power flag, the kernel
 289          * needs to restore it back in case, the primary cpu fails to
 290          * suspend for any reason.
 291          */
 292         exynos5420_cpu_state = __raw_readl(sysram_base_addr +
 293                                                 EXYNOS5420_CPU_STATE);
 294
 295         exynos_pm_enter_sleep_mode();
 296
 297         /* ensure at least INFORM0 has the resume address */
 298         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 299                 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
 300
 301         tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 302         tmp &= ~EXYNOS5_USE_RETENTION;
 303         pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 304
 305         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 306         tmp |= EXYNOS5420_UFS;
 307         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 308
 309         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 310         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 311         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 312
 313         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 314         tmp |= EXYNOS5420_EMULATION;
 315         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 316
 317         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 318         tmp |= EXYNOS5420_EMULATION;
 319         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 320 }
 321
 322
 323 static int exynos_pm_suspend(void)
 324 {
 325         exynos_pm_central_suspend();
 326
 327         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 328                 exynos_cpu_save_register();
 329
 330         return 0;
 331 }
 332
 333 static int exynos5420_pm_suspend(void)
 334 {
 335         u32 this_cluster;
 336
 337         exynos_pm_central_suspend();
 338
 339         /* Setting SEQ_OPTION register */
 340
 341         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 342         if (!this_cluster)
 343                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 344                                 S5P_CENTRAL_SEQ_OPTION);
 345         else
 346                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 347                                 S5P_CENTRAL_SEQ_OPTION);
 348         return 0;
 349 }
 350
 351 static void exynos_pm_release_retention(void)
 352 {
 353         unsigned int i;
 354
 355         for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
 356                 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
 357                                 pm_data->release_ret_regs[i]);
 358 }
 359
 360 static void exynos_pm_resume(void)
 361 {
 362         u32 cpuid = read_cpuid_part();
 363
 364         if (exynos_pm_central_resume())
 365                 goto early_wakeup;
 366
 367         /* For release retention */
 368         exynos_pm_release_retention();
 369
 370         if (pm_data->extra_save)
 371                 s3c_pm_do_restore_core(pm_data->extra_save,
 372                                         pm_data->num_extra_save);
 373
 374         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 375
 376         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 377                 scu_enable(S5P_VA_SCU);
 378
 379         if (call_firmware_op(resume) == -ENOSYS
 380             && cpuid == ARM_CPU_PART_CORTEX_A9)
 381                 exynos_cpu_restore_register();
 382
 383 early_wakeup:
 384
 385         /* Clear SLEEP mode set in INFORM1 */
 386         pmu_raw_writel(0x0, S5P_INFORM1);
 387 }
 388
 389 static void exynos3250_pm_resume(void)
 390 {
 391         u32 cpuid = read_cpuid_part();
 392
 393         if (exynos_pm_central_resume())
 394                 goto early_wakeup;
 395
 396         /* For release retention */
 397         exynos_pm_release_retention();
 398
 399         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 400
 401         if (call_firmware_op(resume) == -ENOSYS
 402             && cpuid == ARM_CPU_PART_CORTEX_A9)
 403                 exynos_cpu_restore_register();
 404
 405 early_wakeup:
 406
 407         /* Clear SLEEP mode set in INFORM1 */
 408         pmu_raw_writel(0x0, S5P_INFORM1);
 409 }
 410
 411 static void exynos5420_prepare_pm_resume(void)
 412 {
 413         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 414                 WARN_ON(mcpm_cpu_powered_up());
 415 }
 416
 417 static void exynos5420_pm_resume(void)
 418 {
 419         unsigned long tmp;
 420
 421         /* Restore the CPU0 low power state register */
 422         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 423         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 424                 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 425
 426         /* Restore the sysram cpu state register */
 427         __raw_writel(exynos5420_cpu_state,
 428                 sysram_base_addr + EXYNOS5420_CPU_STATE);
 429
 430         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 431                         S5P_CENTRAL_SEQ_OPTION);
 432
 433         if (exynos_pm_central_resume())
 434                 goto early_wakeup;
 435
 436         /* For release retention */
 437         exynos_pm_release_retention();
 438
 439         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 440
 441         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 442
 443 early_wakeup:
 444
 445         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 446         tmp &= ~EXYNOS5420_UFS;
 447         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 448
 449         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 450         tmp &= ~EXYNOS5420_EMULATION;
 451         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 452
 453         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 454         tmp &= ~EXYNOS5420_EMULATION;
 455         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 456
 457         /* Clear SLEEP mode set in INFORM1 */
 458         pmu_raw_writel(0x0, S5P_INFORM1);
 459 }
 460
 461 /*
 462  * Suspend Ops
 463  */
 464
 465 static int exynos_suspend_enter(suspend_state_t state)
 466 {
 467         int ret;
 468
 469         s3c_pm_debug_init();
 470
 471         S3C_PMDBG("%s: suspending the system...\n", __func__);
 472
 473         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 474                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 475
 476         if (exynos_irqwake_intmask == -1U
 477             && exynos_get_eint_wake_mask() == -1U) {
 478                 pr_err("%s: No wake-up sources!\n", __func__);
 479                 pr_err("%s: Aborting sleep\n", __func__);
 480                 return -EINVAL;
 481         }
 482
 483         s3c_pm_save_uarts();
 484         if (pm_data->pm_prepare)
 485                 pm_data->pm_prepare();
 486         flush_cache_all();
 487         s3c_pm_check_store();
 488
 489         ret = call_firmware_op(suspend);
 490         if (ret == -ENOSYS)
 491                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 492         if (ret)
 493                 return ret;
 494
 495         if (pm_data->pm_resume_prepare)
 496                 pm_data->pm_resume_prepare();
 497         s3c_pm_restore_uarts();
 498
 499         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 500                         pmu_raw_readl(S5P_WAKEUP_STAT));
 501
 502         s3c_pm_check_restore();
 503
 504         S3C_PMDBG("%s: resuming the system...\n", __func__);
 505
 506         return 0;
 507 }
 508
 509 static int exynos_suspend_prepare(void)
 510 {
 511         int ret;
 512
 513         /*
 514          * REVISIT: It would be better if struct platform_suspend_ops
 515          * .prepare handler get the suspend_state_t as a parameter to
 516          * avoid hard-coding the suspend to mem state. It's safe to do
 517          * it now only because the suspend_valid_only_mem function is
 518          * used as the .valid callback used to check if a given state
 519          * is supported by the platform anyways.
 520          */
 521         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 522         if (ret) {
 523                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 524                 return ret;
 525         }
 526
 527         s3c_pm_check_prepare();
 528
 529         return 0;
 530 }
 531
 532 static void exynos_suspend_finish(void)
 533 {
 534         int ret;
 535
 536         s3c_pm_check_cleanup();
 537
 538         ret = regulator_suspend_finish();
 539         if (ret)
 540                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 541 }
 542
 543 static const struct platform_suspend_ops exynos_suspend_ops = {
 544         .enter          = exynos_suspend_enter,
 545         .prepare        = exynos_suspend_prepare,
 546         .finish         = exynos_suspend_finish,
 547         .valid          = suspend_valid_only_mem,
 548 };
 549
 550 static const struct exynos_pm_data exynos3250_pm_data = {
 551         .wkup_irq       = exynos3250_wkup_irq,
 552         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 553         .release_ret_regs = exynos3250_release_ret_regs,
 554         .pm_suspend     = exynos_pm_suspend,
 555         .pm_resume      = exynos3250_pm_resume,
 556         .pm_prepare     = exynos3250_pm_prepare,
 557         .cpu_suspend    = exynos3250_cpu_suspend,
 558 };
 559
 560 static const struct exynos_pm_data exynos4_pm_data = {
 561         .wkup_irq       = exynos4_wkup_irq,
 562         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 563         .release_ret_regs = exynos_release_ret_regs,
 564         .pm_suspend     = exynos_pm_suspend,
 565         .pm_resume      = exynos_pm_resume,
 566         .pm_prepare     = exynos_pm_prepare,
 567         .cpu_suspend    = exynos_cpu_suspend,
 568 };
 569
 570 static const struct exynos_pm_data exynos5250_pm_data = {
 571         .wkup_irq       = exynos5250_wkup_irq,
 572         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 573         .release_ret_regs = exynos_release_ret_regs,
 574         .extra_save     = exynos5_sys_save,
 575         .num_extra_save = ARRAY_SIZE(exynos5_sys_save),
 576         .pm_suspend     = exynos_pm_suspend,
 577         .pm_resume      = exynos_pm_resume,
 578         .pm_prepare     = exynos_pm_prepare,
 579         .cpu_suspend    = exynos_cpu_suspend,
 580 };
 581
 582 static struct exynos_pm_data exynos5420_pm_data = {
 583         .wkup_irq       = exynos5250_wkup_irq,
 584         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 585         .release_ret_regs = exynos5420_release_ret_regs,
 586         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 587         .pm_resume      = exynos5420_pm_resume,
 588         .pm_suspend     = exynos5420_pm_suspend,
 589         .pm_prepare     = exynos5420_pm_prepare,
 590         .cpu_suspend    = exynos5420_cpu_suspend,
 591 };
 592
 593 static struct of_device_id exynos_pmu_of_device_ids[] = {
 594         {
 595                 .compatible = "samsung,exynos3250-pmu",
 596                 .data = &exynos3250_pm_data,
 597         }, {
 598                 .compatible = "samsung,exynos4210-pmu",
 599                 .data = &exynos4_pm_data,
 600         }, {
 601                 .compatible = "samsung,exynos4212-pmu",
 602                 .data = &exynos4_pm_data,
 603         }, {
 604                 .compatible = "samsung,exynos4412-pmu",
 605                 .data = &exynos4_pm_data,
 606         }, {
 607                 .compatible = "samsung,exynos5250-pmu",
 608                 .data = &exynos5250_pm_data,
 609         }, {
 610                 .compatible = "samsung,exynos5420-pmu",
 611                 .data = &exynos5420_pm_data,
 612         },
 613         { /*sentinel*/ },
 614 };
 615
 616 static struct syscore_ops exynos_pm_syscore_ops;
 617
 618 void __init exynos_pm_init(void)
 619 {
 620         const struct of_device_id *match;
 621         u32 tmp;
 622
 623         of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 624         if (!match) {
 625                 pr_err("Failed to find PMU node\n");
 626                 return;
 627         }
 628         pm_data = (struct exynos_pm_data *) match->data;
 629
 630         /* Platform-specific GIC callback */
 631         gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 632
 633         /* All wakeup disable */
 634         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 635         tmp |= pm_data->wake_disable_mask;
 636         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 637
 638         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 639         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 640
 641         register_syscore_ops(&exynos_pm_syscore_ops);
 642         suspend_set_ops(&exynos_suspend_ops);
 643 }