2 * Symmetric Multi Processing (SMP) support for Armada XP
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Yehuda Yitschak <yehuday@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
16 * This file implements the routines for preparing the SMP infrastructure
17 * and waking up the secondary CPUs
20 #include <linux/init.h>
21 #include <linux/smp.h>
22 #include <linux/clk.h>
24 #include <linux/of_address.h>
25 #include <linux/mbus.h>
26 #include <asm/cacheflush.h>
27 #include <asm/smp_plat.h>
29 #include "armada-370-xp.h"
31 #include "coherency.h"
33 #define AXP_BOOTROM_BASE 0xfff00000
34 #define AXP_BOOTROM_SIZE 0x100000
36 void __init set_secondary_cpus_clock(void)
40 struct clk *cpu_clk = NULL;
41 struct device_node *np = NULL;
43 thiscpu = smp_processor_id();
44 for_each_node_by_type(np, "cpu") {
48 err = of_property_read_u32(np, "reg", &cpu);
53 cpu_clk = of_clk_get(np, 0);
57 if (WARN_ON(IS_ERR(cpu_clk)))
59 clk_prepare_enable(cpu_clk);
60 rate = clk_get_rate(cpu_clk);
62 /* set all the other CPU clk to the same rate than the boot CPU */
63 for_each_node_by_type(np, "cpu") {
67 err = of_property_read_u32(np, "reg", &cpu);
72 cpu_clk = of_clk_get(np, 0);
73 clk_set_rate(cpu_clk, rate);
78 static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
80 armada_xp_mpic_smp_cpu_init();
83 static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
84 struct task_struct *idle)
86 pr_info("Booting CPU %d\n", cpu);
88 armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
93 static void __init armada_xp_smp_init_cpus(void)
95 struct device_node *np;
96 unsigned int i, ncores;
98 np = of_find_node_by_name(NULL, "cpus");
100 panic("No 'cpus' node found\n");
102 ncores = of_get_child_count(np);
103 if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
104 panic("Invalid number of CPUs in DT\n");
106 /* Limit possible CPUs to defconfig */
107 if (ncores > nr_cpu_ids) {
108 pr_warn("SMP: %d CPUs physically present. Only %d configured.",
110 pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
114 for (i = 0; i < ncores; i++)
115 set_cpu_possible(i, true);
117 set_smp_cross_call(armada_mpic_send_doorbell);
120 void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
122 struct device_node *node;
126 set_secondary_cpus_clock();
128 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
131 * In order to boot the secondary CPUs we need to ensure
132 * the bootROM is mapped at the correct address.
134 node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
136 panic("Cannot find 'marvell,bootrom' compatible node");
138 err = of_address_to_resource(node, 0, &res);
140 panic("Cannot get 'bootrom' node address");
142 if (res.start != AXP_BOOTROM_BASE ||
143 resource_size(&res) != AXP_BOOTROM_SIZE)
144 panic("The address for the BootROM is incorrect");
147 struct smp_operations armada_xp_smp_ops __initdata = {
148 .smp_init_cpus = armada_xp_smp_init_cpus,
149 .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
150 .smp_secondary_init = armada_xp_secondary_init,
151 .smp_boot_secondary = armada_xp_boot_secondary,
152 #ifdef CONFIG_HOTPLUG_CPU
153 .cpu_die = armada_xp_cpu_die,