2 * OMAP2xxx APLL clock control functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
24 #include <plat/prcm.h>
27 #include "clock2xxx.h"
28 #include "cm2xxx_3xxx.h"
29 #include "cm-regbits-24xx.h"
31 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
32 #define EN_APLL_STOPPED 0
33 #define EN_APLL_LOCKED 3
35 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
36 #define APLLS_CLKIN_19_2MHZ 0
37 #define APLLS_CLKIN_13MHZ 2
38 #define APLLS_CLKIN_12MHZ 3
40 void __iomem *cm_idlest_pll;
42 /* Private functions */
44 /* Enable an APLL if off */
45 static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
49 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
51 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
53 if ((cval & apll_mask) == apll_mask)
54 return 0; /* apll already enabled */
58 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
60 omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
61 OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
64 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
70 static int omap2_clk_apll96_enable(struct clk *clk)
72 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
75 static int omap2_clk_apll54_enable(struct clk *clk)
77 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
80 static void _apll96_allow_idle(struct clk *clk)
82 omap2xxx_cm_set_apll96_auto_low_power_stop();
85 static void _apll96_deny_idle(struct clk *clk)
87 omap2xxx_cm_set_apll96_disable_autoidle();
90 static void _apll54_allow_idle(struct clk *clk)
92 omap2xxx_cm_set_apll54_auto_low_power_stop();
95 static void _apll54_deny_idle(struct clk *clk)
97 omap2xxx_cm_set_apll54_disable_autoidle();
101 static void omap2_clk_apll_disable(struct clk *clk)
105 cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
106 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
107 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
112 const struct clkops clkops_apll96 = {
113 .enable = omap2_clk_apll96_enable,
114 .disable = omap2_clk_apll_disable,
115 .allow_idle = _apll96_allow_idle,
116 .deny_idle = _apll96_deny_idle,
119 const struct clkops clkops_apll54 = {
120 .enable = omap2_clk_apll54_enable,
121 .disable = omap2_clk_apll_disable,
122 .allow_idle = _apll54_allow_idle,
123 .deny_idle = _apll54_deny_idle,
126 /* Public functions */
128 u32 omap2xxx_get_apll_clkin(void)
130 u32 aplls, srate = 0;
132 aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
133 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
134 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
136 if (aplls == APLLS_CLKIN_19_2MHZ)
138 else if (aplls == APLLS_CLKIN_13MHZ)
140 else if (aplls == APLLS_CLKIN_12MHZ)