arch/arm/mach-omap2/clock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/list.h>
  22 #include <linux/io.h>
  23
  24 #include <plat/hardware.h>
  25 #include <plat/clkdev_omap.h>
  26
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm2xxx_3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm2xxx_3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 /*
  51  * DPLL1 supplies clock to the MPU.
  52  * DPLL2 supplies clock to the IVA2.
  53  * DPLL3 supplies CORE domain clocks.
  54  * DPLL4 supplies peripheral clocks.
  55  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  56  */
  57
  58 /* Forward declarations for DPLL bypass clocks */
  59 static struct clk dpll1_fck;
  60 static struct clk dpll2_fck;
  61
  62 /* PRM CLOCKS */
  63
  64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  65 static struct clk omap_32k_fck = {
  66         .name           = "omap_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69 };
  70
  71 static struct clk secure_32k_fck = {
  72         .name           = "secure_32k_fck",
  73         .ops            = &clkops_null,
  74         .rate           = 32768,
  75 };
  76
  77 /* Virtual source clocks for osc_sys_ck */
  78 static struct clk virt_12m_ck = {
  79         .name           = "virt_12m_ck",
  80         .ops            = &clkops_null,
  81         .rate           = 12000000,
  82 };
  83
  84 static struct clk virt_13m_ck = {
  85         .name           = "virt_13m_ck",
  86         .ops            = &clkops_null,
  87         .rate           = 13000000,
  88 };
  89
  90 static struct clk virt_16_8m_ck = {
  91         .name           = "virt_16_8m_ck",
  92         .ops            = &clkops_null,
  93         .rate           = 16800000,
  94 };
  95
  96 static struct clk virt_19_2m_ck = {
  97         .name           = "virt_19_2m_ck",
  98         .ops            = &clkops_null,
  99         .rate           = 19200000,
 100 };
 101
 102 static struct clk virt_26m_ck = {
 103         .name           = "virt_26m_ck",
 104         .ops            = &clkops_null,
 105         .rate           = 26000000,
 106 };
 107
 108 static struct clk virt_38_4m_ck = {
 109         .name           = "virt_38_4m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 38400000,
 112 };
 113
 114 static const struct clksel_rate osc_sys_12m_rates[] = {
 115         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 116         { .div = 0 }
 117 };
 118
 119 static const struct clksel_rate osc_sys_13m_rates[] = {
 120         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 121         { .div = 0 }
 122 };
 123
 124 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 125         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 130         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel_rate osc_sys_26m_rates[] = {
 135         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 136         { .div = 0 }
 137 };
 138
 139 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 140         { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 141         { .div = 0 }
 142 };
 143
 144 static const struct clksel osc_sys_clksel[] = {
 145         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 146         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 147         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 148         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 149         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 150         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 151         { .parent = NULL },
 152 };
 153
 154 /* Oscillator clock */
 155 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 156 static struct clk osc_sys_ck = {
 157         .name           = "osc_sys_ck",
 158         .ops            = &clkops_null,
 159         .init           = &omap2_init_clksel_parent,
 160         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 161         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 162         .clksel         = osc_sys_clksel,
 163         /* REVISIT: deal with autoextclkmode? */
 164         .recalc         = &omap2_clksel_recalc,
 165 };
 166
 167 static const struct clksel_rate div2_rates[] = {
 168         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 169         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 170         { .div = 0 }
 171 };
 172
 173 static const struct clksel sys_clksel[] = {
 174         { .parent = &osc_sys_ck, .rates = div2_rates },
 175         { .parent = NULL }
 176 };
 177
 178 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 179 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 180 static struct clk sys_ck = {
 181         .name           = "sys_ck",
 182         .ops            = &clkops_null,
 183         .parent         = &osc_sys_ck,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 186         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 187         .clksel         = sys_clksel,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk sys_altclk = {
 192         .name           = "sys_altclk",
 193         .ops            = &clkops_null,
 194 };
 195
 196 /* Optional external clock input for some McBSPs */
 197 static struct clk mcbsp_clks = {
 198         .name           = "mcbsp_clks",
 199         .ops            = &clkops_null,
 200 };
 201
 202 /* PRM EXTERNAL CLOCK OUTPUT */
 203
 204 static struct clk sys_clkout1 = {
 205         .name           = "sys_clkout1",
 206         .ops            = &clkops_omap2_dflt,
 207         .parent         = &osc_sys_ck,
 208         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 209         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 210         .recalc         = &followparent_recalc,
 211 };
 212
 213 /* DPLLS */
 214
 215 /* CM CLOCKS */
 216
 217 static const struct clksel_rate div16_dpll_rates[] = {
 218         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 219         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 220         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 221         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 222         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 223         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 224         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 225         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 226         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 227         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 228         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 229         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 230         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 231         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 232         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 233         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 234         { .div = 0 }
 235 };
 236
 237 static const struct clksel_rate dpll4_rates[] = {
 238         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 239         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 240         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 241         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 242         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 243         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 244         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 245         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 246         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 247         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 248         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 249         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 250         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 251         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 252         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 253         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 254         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
 255         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
 256         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
 257         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
 258         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
 259         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
 260         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
 261         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
 262         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
 263         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
 264         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
 265         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
 266         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
 267         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
 268         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
 269         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
 270         { .div = 0 }
 271 };
 272
 273 /* DPLL1 */
 274 /* MPU clock source */
 275 /* Type: DPLL */
 276 static struct dpll_data dpll1_dd = {
 277         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 278         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 279         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 280         .clk_bypass     = &dpll1_fck,
 281         .clk_ref        = &sys_ck,
 282         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 283         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 284         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 285         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 286         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 287         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 288         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 289         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 290         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 291         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 292         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 293         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 294         .min_divider    = 1,
 295         .max_divider    = OMAP3_MAX_DPLL_DIV,
 296 };
 297
 298 static struct clk dpll1_ck = {
 299         .name           = "dpll1_ck",
 300         .ops            = &clkops_omap3_noncore_dpll_ops,
 301         .parent         = &sys_ck,
 302         .dpll_data      = &dpll1_dd,
 303         .round_rate     = &omap2_dpll_round_rate,
 304         .set_rate       = &omap3_noncore_dpll_set_rate,
 305         .clkdm_name     = "dpll1_clkdm",
 306         .recalc         = &omap3_dpll_recalc,
 307 };
 308
 309 /*
 310  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 311  * DPLL isn't bypassed.
 312  */
 313 static struct clk dpll1_x2_ck = {
 314         .name           = "dpll1_x2_ck",
 315         .ops            = &clkops_null,
 316         .parent         = &dpll1_ck,
 317         .clkdm_name     = "dpll1_clkdm",
 318         .recalc         = &omap3_clkoutx2_recalc,
 319 };
 320
 321 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 322 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 323         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 324         { .parent = NULL }
 325 };
 326
 327 /*
 328  * Does not exist in the TRM - needed to separate the M2 divider from
 329  * bypass selection in mpu_ck
 330  */
 331 static struct clk dpll1_x2m2_ck = {
 332         .name           = "dpll1_x2m2_ck",
 333         .ops            = &clkops_null,
 334         .parent         = &dpll1_x2_ck,
 335         .init           = &omap2_init_clksel_parent,
 336         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 337         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 338         .clksel         = div16_dpll1_x2m2_clksel,
 339         .clkdm_name     = "dpll1_clkdm",
 340         .recalc         = &omap2_clksel_recalc,
 341 };
 342
 343 /* DPLL2 */
 344 /* IVA2 clock source */
 345 /* Type: DPLL */
 346
 347 static struct dpll_data dpll2_dd = {
 348         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 349         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 350         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 351         .clk_bypass     = &dpll2_fck,
 352         .clk_ref        = &sys_ck,
 353         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 354         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 355         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 356         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 357                                 (1 << DPLL_LOW_POWER_BYPASS),
 358         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 359         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 360         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 361         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 362         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 363         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 364         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 365         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 366         .min_divider    = 1,
 367         .max_divider    = OMAP3_MAX_DPLL_DIV,
 368 };
 369
 370 static struct clk dpll2_ck = {
 371         .name           = "dpll2_ck",
 372         .ops            = &clkops_omap3_noncore_dpll_ops,
 373         .parent         = &sys_ck,
 374         .dpll_data      = &dpll2_dd,
 375         .round_rate     = &omap2_dpll_round_rate,
 376         .set_rate       = &omap3_noncore_dpll_set_rate,
 377         .clkdm_name     = "dpll2_clkdm",
 378         .recalc         = &omap3_dpll_recalc,
 379 };
 380
 381 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 382         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 383         { .parent = NULL }
 384 };
 385
 386 /*
 387  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 388  * or CLKOUTX2. CLKOUT seems most plausible.
 389  */
 390 static struct clk dpll2_m2_ck = {
 391         .name           = "dpll2_m2_ck",
 392         .ops            = &clkops_null,
 393         .parent         = &dpll2_ck,
 394         .init           = &omap2_init_clksel_parent,
 395         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 396                                           OMAP3430_CM_CLKSEL2_PLL),
 397         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 398         .clksel         = div16_dpll2_m2x2_clksel,
 399         .clkdm_name     = "dpll2_clkdm",
 400         .recalc         = &omap2_clksel_recalc,
 401 };
 402
 403 /*
 404  * DPLL3
 405  * Source clock for all interfaces and for some device fclks
 406  * REVISIT: Also supports fast relock bypass - not included below
 407  */
 408 static struct dpll_data dpll3_dd = {
 409         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 410         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 411         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 412         .clk_bypass     = &sys_ck,
 413         .clk_ref        = &sys_ck,
 414         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 415         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 417         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 418         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 419         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 420         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 421         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 422         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 423         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 424         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 425         .min_divider    = 1,
 426         .max_divider    = OMAP3_MAX_DPLL_DIV,
 427 };
 428
 429 static struct clk dpll3_ck = {
 430         .name           = "dpll3_ck",
 431         .ops            = &clkops_omap3_core_dpll_ops,
 432         .parent         = &sys_ck,
 433         .dpll_data      = &dpll3_dd,
 434         .round_rate     = &omap2_dpll_round_rate,
 435         .clkdm_name     = "dpll3_clkdm",
 436         .recalc         = &omap3_dpll_recalc,
 437 };
 438
 439 /*
 440  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 441  * DPLL isn't bypassed
 442  */
 443 static struct clk dpll3_x2_ck = {
 444         .name           = "dpll3_x2_ck",
 445         .ops            = &clkops_null,
 446         .parent         = &dpll3_ck,
 447         .clkdm_name     = "dpll3_clkdm",
 448         .recalc         = &omap3_clkoutx2_recalc,
 449 };
 450
 451 static const struct clksel_rate div31_dpll3_rates[] = {
 452         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 453         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 454         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
 455         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
 456         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 457         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
 458         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
 459         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
 460         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
 461         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
 462         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
 463         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
 464         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
 465         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
 466         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
 467         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
 468         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
 469         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
 470         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
 471         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
 472         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
 473         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
 474         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
 475         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
 476         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
 477         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
 478         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
 479         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
 480         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
 481         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
 482         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
 483         { .div = 0 },
 484 };
 485
 486 static const struct clksel div31_dpll3m2_clksel[] = {
 487         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 488         { .parent = NULL }
 489 };
 490
 491 /* DPLL3 output M2 - primary control point for CORE speed */
 492 static struct clk dpll3_m2_ck = {
 493         .name           = "dpll3_m2_ck",
 494         .ops            = &clkops_null,
 495         .parent         = &dpll3_ck,
 496         .init           = &omap2_init_clksel_parent,
 497         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 498         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 499         .clksel         = div31_dpll3m2_clksel,
 500         .clkdm_name     = "dpll3_clkdm",
 501         .round_rate     = &omap2_clksel_round_rate,
 502         .set_rate       = &omap3_core_dpll_m2_set_rate,
 503         .recalc         = &omap2_clksel_recalc,
 504 };
 505
 506 static struct clk core_ck = {
 507         .name           = "core_ck",
 508         .ops            = &clkops_null,
 509         .parent         = &dpll3_m2_ck,
 510         .recalc         = &followparent_recalc,
 511 };
 512
 513 static struct clk dpll3_m2x2_ck = {
 514         .name           = "dpll3_m2x2_ck",
 515         .ops            = &clkops_null,
 516         .parent         = &dpll3_m2_ck,
 517         .clkdm_name     = "dpll3_clkdm",
 518         .recalc         = &omap3_clkoutx2_recalc,
 519 };
 520
 521 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 522 static const struct clksel div16_dpll3_clksel[] = {
 523         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 524         { .parent = NULL }
 525 };
 526
 527 /* This virtual clock is the source for dpll3_m3x2_ck */
 528 static struct clk dpll3_m3_ck = {
 529         .name           = "dpll3_m3_ck",
 530         .ops            = &clkops_null,
 531         .parent         = &dpll3_ck,
 532         .init           = &omap2_init_clksel_parent,
 533         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 534         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 535         .clksel         = div16_dpll3_clksel,
 536         .clkdm_name     = "dpll3_clkdm",
 537         .recalc         = &omap2_clksel_recalc,
 538 };
 539
 540 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 541 static struct clk dpll3_m3x2_ck = {
 542         .name           = "dpll3_m3x2_ck",
 543         .ops            = &clkops_omap2_dflt_wait,
 544         .parent         = &dpll3_m3_ck,
 545         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 546         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 547         .flags          = INVERT_ENABLE,
 548         .clkdm_name     = "dpll3_clkdm",
 549         .recalc         = &omap3_clkoutx2_recalc,
 550 };
 551
 552 static struct clk emu_core_alwon_ck = {
 553         .name           = "emu_core_alwon_ck",
 554         .ops            = &clkops_null,
 555         .parent         = &dpll3_m3x2_ck,
 556         .clkdm_name     = "dpll3_clkdm",
 557         .recalc         = &followparent_recalc,
 558 };
 559
 560 /* DPLL4 */
 561 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 562 /* Type: DPLL */
 563 static struct dpll_data dpll4_dd;
 564
 565 static struct dpll_data dpll4_dd_34xx __initdata = {
 566         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 567         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 568         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 569         .clk_bypass     = &sys_ck,
 570         .clk_ref        = &sys_ck,
 571         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 572         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 573         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 574         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 575         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 576         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 577         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 578         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 579         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 580         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 581         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 582         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 583         .min_divider    = 1,
 584         .max_divider    = OMAP3_MAX_DPLL_DIV,
 585 };
 586
 587 static struct dpll_data dpll4_dd_3630 __initdata = {
 588         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 589         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 590         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 591         .clk_bypass     = &sys_ck,
 592         .clk_ref        = &sys_ck,
 593         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 594         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 595         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 596         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 597         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 598         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 599         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 600         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 601         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 602         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 603         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 604         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 605         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 606         .min_divider    = 1,
 607         .max_divider    = OMAP3_MAX_DPLL_DIV,
 608         .flags          = DPLL_J_TYPE
 609 };
 610
 611 static struct clk dpll4_ck = {
 612         .name           = "dpll4_ck",
 613         .ops            = &clkops_omap3_noncore_dpll_ops,
 614         .parent         = &sys_ck,
 615         .dpll_data      = &dpll4_dd,
 616         .round_rate     = &omap2_dpll_round_rate,
 617         .set_rate       = &omap3_dpll4_set_rate,
 618         .clkdm_name     = "dpll4_clkdm",
 619         .recalc         = &omap3_dpll_recalc,
 620 };
 621
 622 /*
 623  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 624  * DPLL isn't bypassed --
 625  * XXX does this serve any downstream clocks?
 626  */
 627 static struct clk dpll4_x2_ck = {
 628         .name           = "dpll4_x2_ck",
 629         .ops            = &clkops_null,
 630         .parent         = &dpll4_ck,
 631         .clkdm_name     = "dpll4_clkdm",
 632         .recalc         = &omap3_clkoutx2_recalc,
 633 };
 634
 635 static const struct clksel dpll4_clksel[] = {
 636         { .parent = &dpll4_ck, .rates = dpll4_rates },
 637         { .parent = NULL }
 638 };
 639
 640 /* This virtual clock is the source for dpll4_m2x2_ck */
 641 static struct clk dpll4_m2_ck = {
 642         .name           = "dpll4_m2_ck",
 643         .ops            = &clkops_null,
 644         .parent         = &dpll4_ck,
 645         .init           = &omap2_init_clksel_parent,
 646         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 647         .clksel_mask    = OMAP3630_DIV_96M_MASK,
 648         .clksel         = dpll4_clksel,
 649         .clkdm_name     = "dpll4_clkdm",
 650         .recalc         = &omap2_clksel_recalc,
 651 };
 652
 653 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 654 static struct clk dpll4_m2x2_ck = {
 655         .name           = "dpll4_m2x2_ck",
 656         .ops            = &clkops_omap2_dflt_wait,
 657         .parent         = &dpll4_m2_ck,
 658         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 659         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 660         .flags          = INVERT_ENABLE,
 661         .clkdm_name     = "dpll4_clkdm",
 662         .recalc         = &omap3_clkoutx2_recalc,
 663 };
 664
 665 /*
 666  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 667  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 668  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 669  * CM_96K_(F)CLK.
 670  */
 671
 672 /* Adding 192MHz Clock node needed by SGX */
 673 static struct clk omap_192m_alwon_fck = {
 674         .name           = "omap_192m_alwon_fck",
 675         .ops            = &clkops_null,
 676         .parent         = &dpll4_m2x2_ck,
 677         .recalc         = &followparent_recalc,
 678 };
 679
 680 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 681         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 682         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 683         { .div = 0 }
 684 };
 685
 686 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 687         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 688         { .parent = NULL }
 689 };
 690
 691 static const struct clksel_rate omap_96m_dpll_rates[] = {
 692         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 693         { .div = 0 }
 694 };
 695
 696 static const struct clksel_rate omap_96m_sys_rates[] = {
 697         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 698         { .div = 0 }
 699 };
 700
 701 static struct clk omap_96m_alwon_fck = {
 702         .name           = "omap_96m_alwon_fck",
 703         .ops            = &clkops_null,
 704         .parent         = &dpll4_m2x2_ck,
 705         .recalc         = &followparent_recalc,
 706 };
 707
 708 static struct clk omap_96m_alwon_fck_3630 = {
 709         .name           = "omap_96m_alwon_fck",
 710         .parent         = &omap_192m_alwon_fck,
 711         .init           = &omap2_init_clksel_parent,
 712         .ops            = &clkops_null,
 713         .recalc         = &omap2_clksel_recalc,
 714         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 715         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
 716         .clksel         = omap_96m_alwon_fck_clksel
 717 };
 718
 719 static struct clk cm_96m_fck = {
 720         .name           = "cm_96m_fck",
 721         .ops            = &clkops_null,
 722         .parent         = &omap_96m_alwon_fck,
 723         .recalc         = &followparent_recalc,
 724 };
 725
 726 static const struct clksel omap_96m_fck_clksel[] = {
 727         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 728         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 729         { .parent = NULL }
 730 };
 731
 732 static struct clk omap_96m_fck = {
 733         .name           = "omap_96m_fck",
 734         .ops            = &clkops_null,
 735         .parent         = &sys_ck,
 736         .init           = &omap2_init_clksel_parent,
 737         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 738         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 739         .clksel         = omap_96m_fck_clksel,
 740         .recalc         = &omap2_clksel_recalc,
 741 };
 742
 743 /* This virtual clock is the source for dpll4_m3x2_ck */
 744 static struct clk dpll4_m3_ck = {
 745         .name           = "dpll4_m3_ck",
 746         .ops            = &clkops_null,
 747         .parent         = &dpll4_ck,
 748         .init           = &omap2_init_clksel_parent,
 749         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 750         .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
 751         .clksel         = dpll4_clksel,
 752         .clkdm_name     = "dpll4_clkdm",
 753         .recalc         = &omap2_clksel_recalc,
 754 };
 755
 756 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 757 static struct clk dpll4_m3x2_ck = {
 758         .name           = "dpll4_m3x2_ck",
 759         .ops            = &clkops_omap2_dflt_wait,
 760         .parent         = &dpll4_m3_ck,
 761         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 762         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 763         .flags          = INVERT_ENABLE,
 764         .clkdm_name     = "dpll4_clkdm",
 765         .recalc         = &omap3_clkoutx2_recalc,
 766 };
 767
 768 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 769         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 770         { .div = 0 }
 771 };
 772
 773 static const struct clksel_rate omap_54m_alt_rates[] = {
 774         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 775         { .div = 0 }
 776 };
 777
 778 static const struct clksel omap_54m_clksel[] = {
 779         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 780         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 781         { .parent = NULL }
 782 };
 783
 784 static struct clk omap_54m_fck = {
 785         .name           = "omap_54m_fck",
 786         .ops            = &clkops_null,
 787         .init           = &omap2_init_clksel_parent,
 788         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 789         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 790         .clksel         = omap_54m_clksel,
 791         .recalc         = &omap2_clksel_recalc,
 792 };
 793
 794 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 795         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 796         { .div = 0 }
 797 };
 798
 799 static const struct clksel_rate omap_48m_alt_rates[] = {
 800         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 801         { .div = 0 }
 802 };
 803
 804 static const struct clksel omap_48m_clksel[] = {
 805         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 806         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 807         { .parent = NULL }
 808 };
 809
 810 static struct clk omap_48m_fck = {
 811         .name           = "omap_48m_fck",
 812         .ops            = &clkops_null,
 813         .init           = &omap2_init_clksel_parent,
 814         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 815         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 816         .clksel         = omap_48m_clksel,
 817         .recalc         = &omap2_clksel_recalc,
 818 };
 819
 820 static struct clk omap_12m_fck = {
 821         .name           = "omap_12m_fck",
 822         .ops            = &clkops_null,
 823         .parent         = &omap_48m_fck,
 824         .fixed_div      = 4,
 825         .recalc         = &omap_fixed_divisor_recalc,
 826 };
 827
 828 /* This virtual clock is the source for dpll4_m4x2_ck */
 829 static struct clk dpll4_m4_ck = {
 830         .name           = "dpll4_m4_ck",
 831         .ops            = &clkops_null,
 832         .parent         = &dpll4_ck,
 833         .init           = &omap2_init_clksel_parent,
 834         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 835         .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
 836         .clksel         = dpll4_clksel,
 837         .clkdm_name     = "dpll4_clkdm",
 838         .recalc         = &omap2_clksel_recalc,
 839         .set_rate       = &omap2_clksel_set_rate,
 840         .round_rate     = &omap2_clksel_round_rate,
 841 };
 842
 843 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 844 static struct clk dpll4_m4x2_ck = {
 845         .name           = "dpll4_m4x2_ck",
 846         .ops            = &clkops_omap2_dflt_wait,
 847         .parent         = &dpll4_m4_ck,
 848         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 849         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 850         .flags          = INVERT_ENABLE,
 851         .clkdm_name     = "dpll4_clkdm",
 852         .recalc         = &omap3_clkoutx2_recalc,
 853 };
 854
 855 /* This virtual clock is the source for dpll4_m5x2_ck */
 856 static struct clk dpll4_m5_ck = {
 857         .name           = "dpll4_m5_ck",
 858         .ops            = &clkops_null,
 859         .parent         = &dpll4_ck,
 860         .init           = &omap2_init_clksel_parent,
 861         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 862         .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
 863         .clksel         = dpll4_clksel,
 864         .clkdm_name     = "dpll4_clkdm",
 865         .set_rate       = &omap2_clksel_set_rate,
 866         .round_rate     = &omap2_clksel_round_rate,
 867         .recalc         = &omap2_clksel_recalc,
 868 };
 869
 870 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 871 static struct clk dpll4_m5x2_ck = {
 872         .name           = "dpll4_m5x2_ck",
 873         .ops            = &clkops_omap2_dflt_wait,
 874         .parent         = &dpll4_m5_ck,
 875         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 876         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 877         .flags          = INVERT_ENABLE,
 878         .clkdm_name     = "dpll4_clkdm",
 879         .recalc         = &omap3_clkoutx2_recalc,
 880 };
 881
 882 /* This virtual clock is the source for dpll4_m6x2_ck */
 883 static struct clk dpll4_m6_ck = {
 884         .name           = "dpll4_m6_ck",
 885         .ops            = &clkops_null,
 886         .parent         = &dpll4_ck,
 887         .init           = &omap2_init_clksel_parent,
 888         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 889         .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
 890         .clksel         = dpll4_clksel,
 891         .clkdm_name     = "dpll4_clkdm",
 892         .recalc         = &omap2_clksel_recalc,
 893 };
 894
 895 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 896 static struct clk dpll4_m6x2_ck = {
 897         .name           = "dpll4_m6x2_ck",
 898         .ops            = &clkops_omap2_dflt_wait,
 899         .parent         = &dpll4_m6_ck,
 900         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 901         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 902         .flags          = INVERT_ENABLE,
 903         .clkdm_name     = "dpll4_clkdm",
 904         .recalc         = &omap3_clkoutx2_recalc,
 905 };
 906
 907 static struct clk emu_per_alwon_ck = {
 908         .name           = "emu_per_alwon_ck",
 909         .ops            = &clkops_null,
 910         .parent         = &dpll4_m6x2_ck,
 911         .clkdm_name     = "dpll4_clkdm",
 912         .recalc         = &followparent_recalc,
 913 };
 914
 915 /* DPLL5 */
 916 /* Supplies 120MHz clock, USIM source clock */
 917 /* Type: DPLL */
 918 /* 3430ES2 only */
 919 static struct dpll_data dpll5_dd = {
 920         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 921         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 922         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 923         .clk_bypass     = &sys_ck,
 924         .clk_ref        = &sys_ck,
 925         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 926         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 927         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 928         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 929         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 930         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 931         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 932         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 933         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 934         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 935         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 936         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 937         .min_divider    = 1,
 938         .max_divider    = OMAP3_MAX_DPLL_DIV,
 939 };
 940
 941 static struct clk dpll5_ck = {
 942         .name           = "dpll5_ck",
 943         .ops            = &clkops_omap3_noncore_dpll_ops,
 944         .parent         = &sys_ck,
 945         .dpll_data      = &dpll5_dd,
 946         .round_rate     = &omap2_dpll_round_rate,
 947         .set_rate       = &omap3_noncore_dpll_set_rate,
 948         .clkdm_name     = "dpll5_clkdm",
 949         .recalc         = &omap3_dpll_recalc,
 950 };
 951
 952 static const struct clksel div16_dpll5_clksel[] = {
 953         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 954         { .parent = NULL }
 955 };
 956
 957 static struct clk dpll5_m2_ck = {
 958         .name           = "dpll5_m2_ck",
 959         .ops            = &clkops_null,
 960         .parent         = &dpll5_ck,
 961         .init           = &omap2_init_clksel_parent,
 962         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 963         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 964         .clksel         = div16_dpll5_clksel,
 965         .clkdm_name     = "dpll5_clkdm",
 966         .recalc         = &omap2_clksel_recalc,
 967 };
 968
 969 /* CM EXTERNAL CLOCK OUTPUTS */
 970
 971 static const struct clksel_rate clkout2_src_core_rates[] = {
 972         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 973         { .div = 0 }
 974 };
 975
 976 static const struct clksel_rate clkout2_src_sys_rates[] = {
 977         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 978         { .div = 0 }
 979 };
 980
 981 static const struct clksel_rate clkout2_src_96m_rates[] = {
 982         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 983         { .div = 0 }
 984 };
 985
 986 static const struct clksel_rate clkout2_src_54m_rates[] = {
 987         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 988         { .div = 0 }
 989 };
 990
 991 static const struct clksel clkout2_src_clksel[] = {
 992         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 993         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 994         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 995         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 996         { .parent = NULL }
 997 };
 998
 999 static struct clk clkout2_src_ck = {
1000         .name           = "clkout2_src_ck",
1001         .ops            = &clkops_omap2_dflt,
1002         .init           = &omap2_init_clksel_parent,
1003         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1004         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1005         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1006         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1007         .clksel         = clkout2_src_clksel,
1008         .clkdm_name     = "core_clkdm",
1009         .recalc         = &omap2_clksel_recalc,
1010 };
1011
1012 static const struct clksel_rate sys_clkout2_rates[] = {
1013         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1014         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1015         { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1016         { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1017         { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1018         { .div = 0 },
1019 };
1020
1021 static const struct clksel sys_clkout2_clksel[] = {
1022         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1023         { .parent = NULL },
1024 };
1025
1026 static struct clk sys_clkout2 = {
1027         .name           = "sys_clkout2",
1028         .ops            = &clkops_null,
1029         .init           = &omap2_init_clksel_parent,
1030         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1031         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1032         .clksel         = sys_clkout2_clksel,
1033         .recalc         = &omap2_clksel_recalc,
1034         .round_rate     = &omap2_clksel_round_rate,
1035         .set_rate       = &omap2_clksel_set_rate
1036 };
1037
1038 /* CM OUTPUT CLOCKS */
1039
1040 static struct clk corex2_fck = {
1041         .name           = "corex2_fck",
1042         .ops            = &clkops_null,
1043         .parent         = &dpll3_m2x2_ck,
1044         .recalc         = &followparent_recalc,
1045 };
1046
1047 /* DPLL power domain clock controls */
1048
1049 static const struct clksel_rate div4_rates[] = {
1050         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1051         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1052         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1053         { .div = 0 }
1054 };
1055
1056 static const struct clksel div4_core_clksel[] = {
1057         { .parent = &core_ck, .rates = div4_rates },
1058         { .parent = NULL }
1059 };
1060
1061 /*
1062  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1063  * may be inconsistent here?
1064  */
1065 static struct clk dpll1_fck = {
1066         .name           = "dpll1_fck",
1067         .ops            = &clkops_null,
1068         .parent         = &core_ck,
1069         .init           = &omap2_init_clksel_parent,
1070         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1071         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1072         .clksel         = div4_core_clksel,
1073         .recalc         = &omap2_clksel_recalc,
1074 };
1075
1076 static struct clk mpu_ck = {
1077         .name           = "mpu_ck",
1078         .ops            = &clkops_null,
1079         .parent         = &dpll1_x2m2_ck,
1080         .clkdm_name     = "mpu_clkdm",
1081         .recalc         = &followparent_recalc,
1082 };
1083
1084 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1085 static const struct clksel_rate arm_fck_rates[] = {
1086         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1087         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1088         { .div = 0 },
1089 };
1090
1091 static const struct clksel arm_fck_clksel[] = {
1092         { .parent = &mpu_ck, .rates = arm_fck_rates },
1093         { .parent = NULL }
1094 };
1095
1096 static struct clk arm_fck = {
1097         .name           = "arm_fck",
1098         .ops            = &clkops_null,
1099         .parent         = &mpu_ck,
1100         .init           = &omap2_init_clksel_parent,
1101         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1102         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1103         .clksel         = arm_fck_clksel,
1104         .clkdm_name     = "mpu_clkdm",
1105         .recalc         = &omap2_clksel_recalc,
1106 };
1107
1108 /* XXX What about neon_clkdm ? */
1109
1110 /*
1111  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1112  * although it is referenced - so this is a guess
1113  */
1114 static struct clk emu_mpu_alwon_ck = {
1115         .name           = "emu_mpu_alwon_ck",
1116         .ops            = &clkops_null,
1117         .parent         = &mpu_ck,
1118         .recalc         = &followparent_recalc,
1119 };
1120
1121 static struct clk dpll2_fck = {
1122         .name           = "dpll2_fck",
1123         .ops            = &clkops_null,
1124         .parent         = &core_ck,
1125         .init           = &omap2_init_clksel_parent,
1126         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1127         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1128         .clksel         = div4_core_clksel,
1129         .recalc         = &omap2_clksel_recalc,
1130 };
1131
1132 static struct clk iva2_ck = {
1133         .name           = "iva2_ck",
1134         .ops            = &clkops_omap2_dflt_wait,
1135         .parent         = &dpll2_m2_ck,
1136         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1137         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1138         .clkdm_name     = "iva2_clkdm",
1139         .recalc         = &followparent_recalc,
1140 };
1141
1142 /* Common interface clocks */
1143
1144 static const struct clksel div2_core_clksel[] = {
1145         { .parent = &core_ck, .rates = div2_rates },
1146         { .parent = NULL }
1147 };
1148
1149 static struct clk l3_ick = {
1150         .name           = "l3_ick",
1151         .ops            = &clkops_null,
1152         .parent         = &core_ck,
1153         .init           = &omap2_init_clksel_parent,
1154         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1155         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1156         .clksel         = div2_core_clksel,
1157         .clkdm_name     = "core_l3_clkdm",
1158         .recalc         = &omap2_clksel_recalc,
1159 };
1160
1161 static const struct clksel div2_l3_clksel[] = {
1162         { .parent = &l3_ick, .rates = div2_rates },
1163         { .parent = NULL }
1164 };
1165
1166 static struct clk l4_ick = {
1167         .name           = "l4_ick",
1168         .ops            = &clkops_null,
1169         .parent         = &l3_ick,
1170         .init           = &omap2_init_clksel_parent,
1171         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1172         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1173         .clksel         = div2_l3_clksel,
1174         .clkdm_name     = "core_l4_clkdm",
1175         .recalc         = &omap2_clksel_recalc,
1176
1177 };
1178
1179 static const struct clksel div2_l4_clksel[] = {
1180         { .parent = &l4_ick, .rates = div2_rates },
1181         { .parent = NULL }
1182 };
1183
1184 static struct clk rm_ick = {
1185         .name           = "rm_ick",
1186         .ops            = &clkops_null,
1187         .parent         = &l4_ick,
1188         .init           = &omap2_init_clksel_parent,
1189         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1190         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1191         .clksel         = div2_l4_clksel,
1192         .recalc         = &omap2_clksel_recalc,
1193 };
1194
1195 /* GFX power domain */
1196
1197 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1198
1199 static const struct clksel gfx_l3_clksel[] = {
1200         { .parent = &l3_ick, .rates = gfx_l3_rates },
1201         { .parent = NULL }
1202 };
1203
1204 /*
1205  * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1206  * This interface clock does not have a CM_AUTOIDLE bit
1207  */
1208 static struct clk gfx_l3_ck = {
1209         .name           = "gfx_l3_ck",
1210         .ops            = &clkops_omap2_dflt_wait,
1211         .parent         = &l3_ick,
1212         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1213         .enable_bit     = OMAP_EN_GFX_SHIFT,
1214         .recalc         = &followparent_recalc,
1215 };
1216
1217 static struct clk gfx_l3_fck = {
1218         .name           = "gfx_l3_fck",
1219         .ops            = &clkops_null,
1220         .parent         = &gfx_l3_ck,
1221         .init           = &omap2_init_clksel_parent,
1222         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1223         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1224         .clksel         = gfx_l3_clksel,
1225         .clkdm_name     = "gfx_3430es1_clkdm",
1226         .recalc         = &omap2_clksel_recalc,
1227 };
1228
1229 static struct clk gfx_l3_ick = {
1230         .name           = "gfx_l3_ick",
1231         .ops            = &clkops_null,
1232         .parent         = &gfx_l3_ck,
1233         .clkdm_name     = "gfx_3430es1_clkdm",
1234         .recalc         = &followparent_recalc,
1235 };
1236
1237 static struct clk gfx_cg1_ck = {
1238         .name           = "gfx_cg1_ck",
1239         .ops            = &clkops_omap2_dflt_wait,
1240         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1241         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1242         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1243         .clkdm_name     = "gfx_3430es1_clkdm",
1244         .recalc         = &followparent_recalc,
1245 };
1246
1247 static struct clk gfx_cg2_ck = {
1248         .name           = "gfx_cg2_ck",
1249         .ops            = &clkops_omap2_dflt_wait,
1250         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1251         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1252         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1253         .clkdm_name     = "gfx_3430es1_clkdm",
1254         .recalc         = &followparent_recalc,
1255 };
1256
1257 /* SGX power domain - 3430ES2 only */
1258
1259 static const struct clksel_rate sgx_core_rates[] = {
1260         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1261         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1262         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1263         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1264         { .div = 0 },
1265 };
1266
1267 static const struct clksel_rate sgx_192m_rates[] = {
1268         { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1269         { .div = 0 },
1270 };
1271
1272 static const struct clksel_rate sgx_corex2_rates[] = {
1273         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1274         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1275         { .div = 0 },
1276 };
1277
1278 static const struct clksel_rate sgx_96m_rates[] = {
1279         { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1280         { .div = 0 },
1281 };
1282
1283 static const struct clksel sgx_clksel[] = {
1284         { .parent = &core_ck,    .rates = sgx_core_rates },
1285         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1286         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1287         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1288         { .parent = NULL }
1289 };
1290
1291 static struct clk sgx_fck = {
1292         .name           = "sgx_fck",
1293         .ops            = &clkops_omap2_dflt_wait,
1294         .init           = &omap2_init_clksel_parent,
1295         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1296         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1297         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1298         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1299         .clksel         = sgx_clksel,
1300         .clkdm_name     = "sgx_clkdm",
1301         .recalc         = &omap2_clksel_recalc,
1302         .set_rate       = &omap2_clksel_set_rate,
1303         .round_rate     = &omap2_clksel_round_rate
1304 };
1305
1306 /* This interface clock does not have a CM_AUTOIDLE bit */
1307 static struct clk sgx_ick = {
1308         .name           = "sgx_ick",
1309         .ops            = &clkops_omap2_dflt_wait,
1310         .parent         = &l3_ick,
1311         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1312         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1313         .clkdm_name     = "sgx_clkdm",
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 /* CORE power domain */
1318
1319 static struct clk d2d_26m_fck = {
1320         .name           = "d2d_26m_fck",
1321         .ops            = &clkops_omap2_dflt_wait,
1322         .parent         = &sys_ck,
1323         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1324         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1325         .clkdm_name     = "d2d_clkdm",
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk modem_fck = {
1330         .name           = "modem_fck",
1331         .ops            = &clkops_omap2_mdmclk_dflt_wait,
1332         .parent         = &sys_ck,
1333         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1334         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1335         .clkdm_name     = "d2d_clkdm",
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 static struct clk sad2d_ick = {
1340         .name           = "sad2d_ick",
1341         .ops            = &clkops_omap2_iclk_dflt_wait,
1342         .parent         = &l3_ick,
1343         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1344         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1345         .clkdm_name     = "d2d_clkdm",
1346         .recalc         = &followparent_recalc,
1347 };
1348
1349 static struct clk mad2d_ick = {
1350         .name           = "mad2d_ick",
1351         .ops            = &clkops_omap2_iclk_dflt_wait,
1352         .parent         = &l3_ick,
1353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1354         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1355         .clkdm_name     = "d2d_clkdm",
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 static const struct clksel omap343x_gpt_clksel[] = {
1360         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1361         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1362         { .parent = NULL}
1363 };
1364
1365 static struct clk gpt10_fck = {
1366         .name           = "gpt10_fck",
1367         .ops            = &clkops_omap2_dflt_wait,
1368         .parent         = &sys_ck,
1369         .init           = &omap2_init_clksel_parent,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1372         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1373         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1374         .clksel         = omap343x_gpt_clksel,
1375         .clkdm_name     = "core_l4_clkdm",
1376         .recalc         = &omap2_clksel_recalc,
1377 };
1378
1379 static struct clk gpt11_fck = {
1380         .name           = "gpt11_fck",
1381         .ops            = &clkops_omap2_dflt_wait,
1382         .parent         = &sys_ck,
1383         .init           = &omap2_init_clksel_parent,
1384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1386         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1387         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1388         .clksel         = omap343x_gpt_clksel,
1389         .clkdm_name     = "core_l4_clkdm",
1390         .recalc         = &omap2_clksel_recalc,
1391 };
1392
1393 static struct clk cpefuse_fck = {
1394         .name           = "cpefuse_fck",
1395         .ops            = &clkops_omap2_dflt,
1396         .parent         = &sys_ck,
1397         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1398         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 static struct clk ts_fck = {
1403         .name           = "ts_fck",
1404         .ops            = &clkops_omap2_dflt,
1405         .parent         = &omap_32k_fck,
1406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1407         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk usbtll_fck = {
1412         .name           = "usbtll_fck",
1413         .ops            = &clkops_omap2_dflt_wait,
1414         .parent         = &dpll5_m2_ck,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1416         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 /* CORE 96M FCLK-derived clocks */
1421
1422 static struct clk core_96m_fck = {
1423         .name           = "core_96m_fck",
1424         .ops            = &clkops_null,
1425         .parent         = &omap_96m_fck,
1426         .clkdm_name     = "core_l4_clkdm",
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk mmchs3_fck = {
1431         .name           = "mmchs3_fck",
1432         .ops            = &clkops_omap2_dflt_wait,
1433         .parent         = &core_96m_fck,
1434         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1435         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1436         .clkdm_name     = "core_l4_clkdm",
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static struct clk mmchs2_fck = {
1441         .name           = "mmchs2_fck",
1442         .ops            = &clkops_omap2_dflt_wait,
1443         .parent         = &core_96m_fck,
1444         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1446         .clkdm_name     = "core_l4_clkdm",
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 static struct clk mspro_fck = {
1451         .name           = "mspro_fck",
1452         .ops            = &clkops_omap2_dflt_wait,
1453         .parent         = &core_96m_fck,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1456         .clkdm_name     = "core_l4_clkdm",
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 static struct clk mmchs1_fck = {
1461         .name           = "mmchs1_fck",
1462         .ops            = &clkops_omap2_dflt_wait,
1463         .parent         = &core_96m_fck,
1464         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1466         .clkdm_name     = "core_l4_clkdm",
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 static struct clk i2c3_fck = {
1471         .name           = "i2c3_fck",
1472         .ops            = &clkops_omap2_dflt_wait,
1473         .parent         = &core_96m_fck,
1474         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1476         .clkdm_name     = "core_l4_clkdm",
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk i2c2_fck = {
1481         .name           = "i2c2_fck",
1482         .ops            = &clkops_omap2_dflt_wait,
1483         .parent         = &core_96m_fck,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1485         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1486         .clkdm_name     = "core_l4_clkdm",
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk i2c1_fck = {
1491         .name           = "i2c1_fck",
1492         .ops            = &clkops_omap2_dflt_wait,
1493         .parent         = &core_96m_fck,
1494         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1495         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1496         .clkdm_name     = "core_l4_clkdm",
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 /*
1501  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1502  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1503  */
1504 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1505         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1506         { .div = 0 }
1507 };
1508
1509 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1510         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1511         { .div = 0 }
1512 };
1513
1514 static const struct clksel mcbsp_15_clksel[] = {
1515         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1516         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1517         { .parent = NULL }
1518 };
1519
1520 static struct clk mcbsp5_fck = {
1521         .name           = "mcbsp5_fck",
1522         .ops            = &clkops_omap2_dflt_wait,
1523         .init           = &omap2_init_clksel_parent,
1524         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1526         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1527         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1528         .clksel         = mcbsp_15_clksel,
1529         .clkdm_name     = "core_l4_clkdm",
1530         .recalc         = &omap2_clksel_recalc,
1531 };
1532
1533 static struct clk mcbsp1_fck = {
1534         .name           = "mcbsp1_fck",
1535         .ops            = &clkops_omap2_dflt_wait,
1536         .init           = &omap2_init_clksel_parent,
1537         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1538         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1539         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1540         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1541         .clksel         = mcbsp_15_clksel,
1542         .clkdm_name     = "core_l4_clkdm",
1543         .recalc         = &omap2_clksel_recalc,
1544 };
1545
1546 /* CORE_48M_FCK-derived clocks */
1547
1548 static struct clk core_48m_fck = {
1549         .name           = "core_48m_fck",
1550         .ops            = &clkops_null,
1551         .parent         = &omap_48m_fck,
1552         .clkdm_name     = "core_l4_clkdm",
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk mcspi4_fck = {
1557         .name           = "mcspi4_fck",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .parent         = &core_48m_fck,
1560         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1562         .recalc         = &followparent_recalc,
1563         .clkdm_name     = "core_l4_clkdm",
1564 };
1565
1566 static struct clk mcspi3_fck = {
1567         .name           = "mcspi3_fck",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .parent         = &core_48m_fck,
1570         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1572         .recalc         = &followparent_recalc,
1573         .clkdm_name     = "core_l4_clkdm",
1574 };
1575
1576 static struct clk mcspi2_fck = {
1577         .name           = "mcspi2_fck",
1578         .ops            = &clkops_omap2_dflt_wait,
1579         .parent         = &core_48m_fck,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1582         .recalc         = &followparent_recalc,
1583         .clkdm_name     = "core_l4_clkdm",
1584 };
1585
1586 static struct clk mcspi1_fck = {
1587         .name           = "mcspi1_fck",
1588         .ops            = &clkops_omap2_dflt_wait,
1589         .parent         = &core_48m_fck,
1590         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1592         .recalc         = &followparent_recalc,
1593         .clkdm_name     = "core_l4_clkdm",
1594 };
1595
1596 static struct clk uart2_fck = {
1597         .name           = "uart2_fck",
1598         .ops            = &clkops_omap2_dflt_wait,
1599         .parent         = &core_48m_fck,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1601         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1602         .clkdm_name     = "core_l4_clkdm",
1603         .recalc         = &followparent_recalc,
1604 };
1605
1606 static struct clk uart1_fck = {
1607         .name           = "uart1_fck",
1608         .ops            = &clkops_omap2_dflt_wait,
1609         .parent         = &core_48m_fck,
1610         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1611         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1612         .clkdm_name     = "core_l4_clkdm",
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk fshostusb_fck = {
1617         .name           = "fshostusb_fck",
1618         .ops            = &clkops_omap2_dflt_wait,
1619         .parent         = &core_48m_fck,
1620         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1622         .recalc         = &followparent_recalc,
1623 };
1624
1625 /* CORE_12M_FCK based clocks */
1626
1627 static struct clk core_12m_fck = {
1628         .name           = "core_12m_fck",
1629         .ops            = &clkops_null,
1630         .parent         = &omap_12m_fck,
1631         .clkdm_name     = "core_l4_clkdm",
1632         .recalc         = &followparent_recalc,
1633 };
1634
1635 static struct clk hdq_fck = {
1636         .name           = "hdq_fck",
1637         .ops            = &clkops_omap2_dflt_wait,
1638         .parent         = &core_12m_fck,
1639         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1640         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 /* DPLL3-derived clock */
1645
1646 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1647         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1648         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1649         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1650         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1651         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1652         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1653         { .div = 0 }
1654 };
1655
1656 static const struct clksel ssi_ssr_clksel[] = {
1657         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1658         { .parent = NULL }
1659 };
1660
1661 static struct clk ssi_ssr_fck_3430es1 = {
1662         .name           = "ssi_ssr_fck",
1663         .ops            = &clkops_omap2_dflt,
1664         .init           = &omap2_init_clksel_parent,
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1666         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1667         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1668         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1669         .clksel         = ssi_ssr_clksel,
1670         .clkdm_name     = "core_l4_clkdm",
1671         .recalc         = &omap2_clksel_recalc,
1672 };
1673
1674 static struct clk ssi_ssr_fck_3430es2 = {
1675         .name           = "ssi_ssr_fck",
1676         .ops            = &clkops_omap3430es2_ssi_wait,
1677         .init           = &omap2_init_clksel_parent,
1678         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1679         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1680         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1681         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1682         .clksel         = ssi_ssr_clksel,
1683         .clkdm_name     = "core_l4_clkdm",
1684         .recalc         = &omap2_clksel_recalc,
1685 };
1686
1687 static struct clk ssi_sst_fck_3430es1 = {
1688         .name           = "ssi_sst_fck",
1689         .ops            = &clkops_null,
1690         .parent         = &ssi_ssr_fck_3430es1,
1691         .fixed_div      = 2,
1692         .recalc         = &omap_fixed_divisor_recalc,
1693 };
1694
1695 static struct clk ssi_sst_fck_3430es2 = {
1696         .name           = "ssi_sst_fck",
1697         .ops            = &clkops_null,
1698         .parent         = &ssi_ssr_fck_3430es2,
1699         .fixed_div      = 2,
1700         .recalc         = &omap_fixed_divisor_recalc,
1701 };
1702
1703
1704
1705 /* CORE_L3_ICK based clocks */
1706
1707 /*
1708  * XXX must add clk_enable/clk_disable for these if standard code won't
1709  * handle it
1710  */
1711 static struct clk core_l3_ick = {
1712         .name           = "core_l3_ick",
1713         .ops            = &clkops_null,
1714         .parent         = &l3_ick,
1715         .clkdm_name     = "core_l3_clkdm",
1716         .recalc         = &followparent_recalc,
1717 };
1718
1719 static struct clk hsotgusb_ick_3430es1 = {
1720         .name           = "hsotgusb_ick",
1721         .ops            = &clkops_omap2_iclk_dflt,
1722         .parent         = &core_l3_ick,
1723         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1724         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1725         .clkdm_name     = "core_l3_clkdm",
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 static struct clk hsotgusb_ick_3430es2 = {
1730         .name           = "hsotgusb_ick",
1731         .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
1732         .parent         = &core_l3_ick,
1733         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1734         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1735         .clkdm_name     = "core_l3_clkdm",
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 /* This interface clock does not have a CM_AUTOIDLE bit */
1740 static struct clk sdrc_ick = {
1741         .name           = "sdrc_ick",
1742         .ops            = &clkops_omap2_dflt_wait,
1743         .parent         = &core_l3_ick,
1744         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1745         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1746         .flags          = ENABLE_ON_INIT,
1747         .clkdm_name     = "core_l3_clkdm",
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk gpmc_fck = {
1752         .name           = "gpmc_fck",
1753         .ops            = &clkops_null,
1754         .parent         = &core_l3_ick,
1755         .flags          = ENABLE_ON_INIT, /* huh? */
1756         .clkdm_name     = "core_l3_clkdm",
1757         .recalc         = &followparent_recalc,
1758 };
1759
1760 /* SECURITY_L3_ICK based clocks */
1761
1762 static struct clk security_l3_ick = {
1763         .name           = "security_l3_ick",
1764         .ops            = &clkops_null,
1765         .parent         = &l3_ick,
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk pka_ick = {
1770         .name           = "pka_ick",
1771         .ops            = &clkops_omap2_iclk_dflt_wait,
1772         .parent         = &security_l3_ick,
1773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1774         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 /* CORE_L4_ICK based clocks */
1779
1780 static struct clk core_l4_ick = {
1781         .name           = "core_l4_ick",
1782         .ops            = &clkops_null,
1783         .parent         = &l4_ick,
1784         .clkdm_name     = "core_l4_clkdm",
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk usbtll_ick = {
1789         .name           = "usbtll_ick",
1790         .ops            = &clkops_omap2_iclk_dflt_wait,
1791         .parent         = &core_l4_ick,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1793         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1794         .clkdm_name     = "core_l4_clkdm",
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk mmchs3_ick = {
1799         .name           = "mmchs3_ick",
1800         .ops            = &clkops_omap2_iclk_dflt_wait,
1801         .parent         = &core_l4_ick,
1802         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1804         .clkdm_name     = "core_l4_clkdm",
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 /* Intersystem Communication Registers - chassis mode only */
1809 static struct clk icr_ick = {
1810         .name           = "icr_ick",
1811         .ops            = &clkops_omap2_iclk_dflt_wait,
1812         .parent         = &core_l4_ick,
1813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1815         .clkdm_name     = "core_l4_clkdm",
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 static struct clk aes2_ick = {
1820         .name           = "aes2_ick",
1821         .ops            = &clkops_omap2_iclk_dflt_wait,
1822         .parent         = &core_l4_ick,
1823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1825         .clkdm_name     = "core_l4_clkdm",
1826         .recalc         = &followparent_recalc,
1827 };
1828
1829 static struct clk sha12_ick = {
1830         .name           = "sha12_ick",
1831         .ops            = &clkops_omap2_iclk_dflt_wait,
1832         .parent         = &core_l4_ick,
1833         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1834         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1835         .clkdm_name     = "core_l4_clkdm",
1836         .recalc         = &followparent_recalc,
1837 };
1838
1839 static struct clk des2_ick = {
1840         .name           = "des2_ick",
1841         .ops            = &clkops_omap2_iclk_dflt_wait,
1842         .parent         = &core_l4_ick,
1843         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1844         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1845         .clkdm_name     = "core_l4_clkdm",
1846         .recalc         = &followparent_recalc,
1847 };
1848
1849 static struct clk mmchs2_ick = {
1850         .name           = "mmchs2_ick",
1851         .ops            = &clkops_omap2_iclk_dflt_wait,
1852         .parent         = &core_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1855         .clkdm_name     = "core_l4_clkdm",
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mmchs1_ick = {
1860         .name           = "mmchs1_ick",
1861         .ops            = &clkops_omap2_iclk_dflt_wait,
1862         .parent         = &core_l4_ick,
1863         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1865         .clkdm_name     = "core_l4_clkdm",
1866         .recalc         = &followparent_recalc,
1867 };
1868
1869 static struct clk mspro_ick = {
1870         .name           = "mspro_ick",
1871         .ops            = &clkops_omap2_iclk_dflt_wait,
1872         .parent         = &core_l4_ick,
1873         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1874         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1875         .clkdm_name     = "core_l4_clkdm",
1876         .recalc         = &followparent_recalc,
1877 };
1878
1879 static struct clk hdq_ick = {
1880         .name           = "hdq_ick",
1881         .ops            = &clkops_omap2_iclk_dflt_wait,
1882         .parent         = &core_l4_ick,
1883         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1884         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1885         .clkdm_name     = "core_l4_clkdm",
1886         .recalc         = &followparent_recalc,
1887 };
1888
1889 static struct clk mcspi4_ick = {
1890         .name           = "mcspi4_ick",
1891         .ops            = &clkops_omap2_iclk_dflt_wait,
1892         .parent         = &core_l4_ick,
1893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1894         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1895         .clkdm_name     = "core_l4_clkdm",
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk mcspi3_ick = {
1900         .name           = "mcspi3_ick",
1901         .ops            = &clkops_omap2_iclk_dflt_wait,
1902         .parent         = &core_l4_ick,
1903         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1904         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1905         .clkdm_name     = "core_l4_clkdm",
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 static struct clk mcspi2_ick = {
1910         .name           = "mcspi2_ick",
1911         .ops            = &clkops_omap2_iclk_dflt_wait,
1912         .parent         = &core_l4_ick,
1913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1915         .clkdm_name     = "core_l4_clkdm",
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk mcspi1_ick = {
1920         .name           = "mcspi1_ick",
1921         .ops            = &clkops_omap2_iclk_dflt_wait,
1922         .parent         = &core_l4_ick,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1925         .clkdm_name     = "core_l4_clkdm",
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk i2c3_ick = {
1930         .name           = "i2c3_ick",
1931         .ops            = &clkops_omap2_iclk_dflt_wait,
1932         .parent         = &core_l4_ick,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1934         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1935         .clkdm_name     = "core_l4_clkdm",
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk i2c2_ick = {
1940         .name           = "i2c2_ick",
1941         .ops            = &clkops_omap2_iclk_dflt_wait,
1942         .parent         = &core_l4_ick,
1943         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1945         .clkdm_name     = "core_l4_clkdm",
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk i2c1_ick = {
1950         .name           = "i2c1_ick",
1951         .ops            = &clkops_omap2_iclk_dflt_wait,
1952         .parent         = &core_l4_ick,
1953         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1954         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1955         .clkdm_name     = "core_l4_clkdm",
1956         .recalc         = &followparent_recalc,
1957 };
1958
1959 static struct clk uart2_ick = {
1960         .name           = "uart2_ick",
1961         .ops            = &clkops_omap2_iclk_dflt_wait,
1962         .parent         = &core_l4_ick,
1963         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1964         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1965         .clkdm_name     = "core_l4_clkdm",
1966         .recalc         = &followparent_recalc,
1967 };
1968
1969 static struct clk uart1_ick = {
1970         .name           = "uart1_ick",
1971         .ops            = &clkops_omap2_iclk_dflt_wait,
1972         .parent         = &core_l4_ick,
1973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1974         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1975         .clkdm_name     = "core_l4_clkdm",
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk gpt11_ick = {
1980         .name           = "gpt11_ick",
1981         .ops            = &clkops_omap2_iclk_dflt_wait,
1982         .parent         = &core_l4_ick,
1983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1984         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1985         .clkdm_name     = "core_l4_clkdm",
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static struct clk gpt10_ick = {
1990         .name           = "gpt10_ick",
1991         .ops            = &clkops_omap2_iclk_dflt_wait,
1992         .parent         = &core_l4_ick,
1993         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1995         .clkdm_name     = "core_l4_clkdm",
1996         .recalc         = &followparent_recalc,
1997 };
1998
1999 static struct clk mcbsp5_ick = {
2000         .name           = "mcbsp5_ick",
2001         .ops            = &clkops_omap2_iclk_dflt_wait,
2002         .parent         = &core_l4_ick,
2003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2004         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2005         .clkdm_name     = "core_l4_clkdm",
2006         .recalc         = &followparent_recalc,
2007 };
2008
2009 static struct clk mcbsp1_ick = {
2010         .name           = "mcbsp1_ick",
2011         .ops            = &clkops_omap2_iclk_dflt_wait,
2012         .parent         = &core_l4_ick,
2013         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2015         .clkdm_name     = "core_l4_clkdm",
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk fac_ick = {
2020         .name           = "fac_ick",
2021         .ops            = &clkops_omap2_iclk_dflt_wait,
2022         .parent         = &core_l4_ick,
2023         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2024         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2025         .clkdm_name     = "core_l4_clkdm",
2026         .recalc         = &followparent_recalc,
2027 };
2028
2029 static struct clk mailboxes_ick = {
2030         .name           = "mailboxes_ick",
2031         .ops            = &clkops_omap2_iclk_dflt_wait,
2032         .parent         = &core_l4_ick,
2033         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2034         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2035         .clkdm_name     = "core_l4_clkdm",
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk omapctrl_ick = {
2040         .name           = "omapctrl_ick",
2041         .ops            = &clkops_omap2_iclk_dflt_wait,
2042         .parent         = &core_l4_ick,
2043         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2044         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2045         .flags          = ENABLE_ON_INIT,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 /* SSI_L4_ICK based clocks */
2050
2051 static struct clk ssi_l4_ick = {
2052         .name           = "ssi_l4_ick",
2053         .ops            = &clkops_null,
2054         .parent         = &l4_ick,
2055         .clkdm_name     = "core_l4_clkdm",
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk ssi_ick_3430es1 = {
2060         .name           = "ssi_ick",
2061         .ops            = &clkops_omap2_iclk_dflt,
2062         .parent         = &ssi_l4_ick,
2063         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2064         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2065         .clkdm_name     = "core_l4_clkdm",
2066         .recalc         = &followparent_recalc,
2067 };
2068
2069 static struct clk ssi_ick_3430es2 = {
2070         .name           = "ssi_ick",
2071         .ops            = &clkops_omap3430es2_iclk_ssi_wait,
2072         .parent         = &ssi_l4_ick,
2073         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2074         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2075         .clkdm_name     = "core_l4_clkdm",
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2080  * but l4_ick makes more sense to me */
2081
2082 static const struct clksel usb_l4_clksel[] = {
2083         { .parent = &l4_ick, .rates = div2_rates },
2084         { .parent = NULL },
2085 };
2086
2087 static struct clk usb_l4_ick = {
2088         .name           = "usb_l4_ick",
2089         .ops            = &clkops_omap2_iclk_dflt_wait,
2090         .parent         = &l4_ick,
2091         .init           = &omap2_init_clksel_parent,
2092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2093         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2094         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2095         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2096         .clksel         = usb_l4_clksel,
2097         .recalc         = &omap2_clksel_recalc,
2098 };
2099
2100 /* SECURITY_L4_ICK2 based clocks */
2101
2102 static struct clk security_l4_ick2 = {
2103         .name           = "security_l4_ick2",
2104         .ops            = &clkops_null,
2105         .parent         = &l4_ick,
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk aes1_ick = {
2110         .name           = "aes1_ick",
2111         .ops            = &clkops_omap2_iclk_dflt_wait,
2112         .parent         = &security_l4_ick2,
2113         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2114         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk rng_ick = {
2119         .name           = "rng_ick",
2120         .ops            = &clkops_omap2_iclk_dflt_wait,
2121         .parent         = &security_l4_ick2,
2122         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2123         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2124         .recalc         = &followparent_recalc,
2125 };
2126
2127 static struct clk sha11_ick = {
2128         .name           = "sha11_ick",
2129         .ops            = &clkops_omap2_iclk_dflt_wait,
2130         .parent         = &security_l4_ick2,
2131         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2132         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk des1_ick = {
2137         .name           = "des1_ick",
2138         .ops            = &clkops_omap2_iclk_dflt_wait,
2139         .parent         = &security_l4_ick2,
2140         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2141         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2142         .recalc         = &followparent_recalc,
2143 };
2144
2145 /* DSS */
2146 static struct clk dss1_alwon_fck_3430es1 = {
2147         .name           = "dss1_alwon_fck",
2148         .ops            = &clkops_omap2_dflt,
2149         .parent         = &dpll4_m4x2_ck,
2150         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2151         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2152         .clkdm_name     = "dss_clkdm",
2153         .recalc         = &followparent_recalc,
2154 };
2155
2156 static struct clk dss1_alwon_fck_3430es2 = {
2157         .name           = "dss1_alwon_fck",
2158         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2159         .parent         = &dpll4_m4x2_ck,
2160         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2161         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2162         .clkdm_name     = "dss_clkdm",
2163         .recalc         = &followparent_recalc,
2164 };
2165
2166 static struct clk dss_tv_fck = {
2167         .name           = "dss_tv_fck",
2168         .ops            = &clkops_omap2_dflt,
2169         .parent         = &omap_54m_fck,
2170         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2171         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2172         .clkdm_name     = "dss_clkdm",
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk dss_96m_fck = {
2177         .name           = "dss_96m_fck",
2178         .ops            = &clkops_omap2_dflt,
2179         .parent         = &omap_96m_fck,
2180         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2181         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2182         .clkdm_name     = "dss_clkdm",
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk dss2_alwon_fck = {
2187         .name           = "dss2_alwon_fck",
2188         .ops            = &clkops_omap2_dflt,
2189         .parent         = &sys_ck,
2190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2191         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2192         .clkdm_name     = "dss_clkdm",
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk dss_ick_3430es1 = {
2197         /* Handles both L3 and L4 clocks */
2198         .name           = "dss_ick",
2199         .ops            = &clkops_omap2_iclk_dflt,
2200         .parent         = &l4_ick,
2201         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2202         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2203         .clkdm_name     = "dss_clkdm",
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 static struct clk dss_ick_3430es2 = {
2208         /* Handles both L3 and L4 clocks */
2209         .name           = "dss_ick",
2210         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2211         .parent         = &l4_ick,
2212         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2213         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2214         .clkdm_name     = "dss_clkdm",
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 /* CAM */
2219
2220 static struct clk cam_mclk = {
2221         .name           = "cam_mclk",
2222         .ops            = &clkops_omap2_dflt,
2223         .parent         = &dpll4_m5x2_ck,
2224         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2225         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2226         .clkdm_name     = "cam_clkdm",
2227         .recalc         = &followparent_recalc,
2228 };
2229
2230 static struct clk cam_ick = {
2231         /* Handles both L3 and L4 clocks */
2232         .name           = "cam_ick",
2233         .ops            = &clkops_omap2_iclk_dflt,
2234         .parent         = &l4_ick,
2235         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2236         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2237         .clkdm_name     = "cam_clkdm",
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk csi2_96m_fck = {
2242         .name           = "csi2_96m_fck",
2243         .ops            = &clkops_omap2_dflt,
2244         .parent         = &core_96m_fck,
2245         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2246         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2247         .clkdm_name     = "cam_clkdm",
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 /* USBHOST - 3430ES2 only */
2252
2253 static struct clk usbhost_120m_fck = {
2254         .name           = "usbhost_120m_fck",
2255         .ops            = &clkops_omap2_dflt,
2256         .parent         = &dpll5_m2_ck,
2257         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2258         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2259         .clkdm_name     = "usbhost_clkdm",
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk usbhost_48m_fck = {
2264         .name           = "usbhost_48m_fck",
2265         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2266         .parent         = &omap_48m_fck,
2267         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2268         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2269         .clkdm_name     = "usbhost_clkdm",
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk usbhost_ick = {
2274         /* Handles both L3 and L4 clocks */
2275         .name           = "usbhost_ick",
2276         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2277         .parent         = &l4_ick,
2278         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2279         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2280         .clkdm_name     = "usbhost_clkdm",
2281         .recalc         = &followparent_recalc,
2282 };
2283
2284 /* WKUP */
2285
2286 static const struct clksel_rate usim_96m_rates[] = {
2287         { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
2288         { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
2289         { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
2290         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2291         { .div = 0 },
2292 };
2293
2294 static const struct clksel_rate usim_120m_rates[] = {
2295         { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
2296         { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
2297         { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
2298         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2299         { .div = 0 },
2300 };
2301
2302 static const struct clksel usim_clksel[] = {
2303         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2304         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2305         { .parent = &sys_ck,            .rates = div2_rates },
2306         { .parent = NULL },
2307 };
2308
2309 /* 3430ES2 only */
2310 static struct clk usim_fck = {
2311         .name           = "usim_fck",
2312         .ops            = &clkops_omap2_dflt_wait,
2313         .init           = &omap2_init_clksel_parent,
2314         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2315         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2316         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2317         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2318         .clksel         = usim_clksel,
2319         .recalc         = &omap2_clksel_recalc,
2320 };
2321
2322 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2323 static struct clk gpt1_fck = {
2324         .name           = "gpt1_fck",
2325         .ops            = &clkops_omap2_dflt_wait,
2326         .init           = &omap2_init_clksel_parent,
2327         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2328         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2329         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2330         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2331         .clksel         = omap343x_gpt_clksel,
2332         .clkdm_name     = "wkup_clkdm",
2333         .recalc         = &omap2_clksel_recalc,
2334 };
2335
2336 static struct clk wkup_32k_fck = {
2337         .name           = "wkup_32k_fck",
2338         .ops            = &clkops_null,
2339         .parent         = &omap_32k_fck,
2340         .clkdm_name     = "wkup_clkdm",
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk gpio1_dbck = {
2345         .name           = "gpio1_dbck",
2346         .ops            = &clkops_omap2_dflt,
2347         .parent         = &wkup_32k_fck,
2348         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2349         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2350         .clkdm_name     = "wkup_clkdm",
2351         .recalc         = &followparent_recalc,
2352 };
2353
2354 static struct clk wdt2_fck = {
2355         .name           = "wdt2_fck",
2356         .ops            = &clkops_omap2_dflt_wait,
2357         .parent         = &wkup_32k_fck,
2358         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2359         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2360         .clkdm_name     = "wkup_clkdm",
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk wkup_l4_ick = {
2365         .name           = "wkup_l4_ick",
2366         .ops            = &clkops_null,
2367         .parent         = &sys_ck,
2368         .clkdm_name     = "wkup_clkdm",
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 /* 3430ES2 only */
2373 /* Never specifically named in the TRM, so we have to infer a likely name */
2374 static struct clk usim_ick = {
2375         .name           = "usim_ick",
2376         .ops            = &clkops_omap2_iclk_dflt_wait,
2377         .parent         = &wkup_l4_ick,
2378         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2379         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 static struct clk wdt2_ick = {
2385         .name           = "wdt2_ick",
2386         .ops            = &clkops_omap2_iclk_dflt_wait,
2387         .parent         = &wkup_l4_ick,
2388         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2389         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2390         .clkdm_name     = "wkup_clkdm",
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk wdt1_ick = {
2395         .name           = "wdt1_ick",
2396         .ops            = &clkops_omap2_iclk_dflt_wait,
2397         .parent         = &wkup_l4_ick,
2398         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2399         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2400         .clkdm_name     = "wkup_clkdm",
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk gpio1_ick = {
2405         .name           = "gpio1_ick",
2406         .ops            = &clkops_omap2_iclk_dflt_wait,
2407         .parent         = &wkup_l4_ick,
2408         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2409         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2410         .clkdm_name     = "wkup_clkdm",
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk omap_32ksync_ick = {
2415         .name           = "omap_32ksync_ick",
2416         .ops            = &clkops_omap2_iclk_dflt_wait,
2417         .parent         = &wkup_l4_ick,
2418         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2419         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2420         .clkdm_name     = "wkup_clkdm",
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 /* XXX This clock no longer exists in 3430 TRM rev F */
2425 static struct clk gpt12_ick = {
2426         .name           = "gpt12_ick",
2427         .ops            = &clkops_omap2_iclk_dflt_wait,
2428         .parent         = &wkup_l4_ick,
2429         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2430         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2431         .clkdm_name     = "wkup_clkdm",
2432         .recalc         = &followparent_recalc,
2433 };
2434
2435 static struct clk gpt1_ick = {
2436         .name           = "gpt1_ick",
2437         .ops            = &clkops_omap2_iclk_dflt_wait,
2438         .parent         = &wkup_l4_ick,
2439         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2440         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2441         .clkdm_name     = "wkup_clkdm",
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445
2446
2447 /* PER clock domain */
2448
2449 static struct clk per_96m_fck = {
2450         .name           = "per_96m_fck",
2451         .ops            = &clkops_null,
2452         .parent         = &omap_96m_alwon_fck,
2453         .clkdm_name     = "per_clkdm",
2454         .recalc         = &followparent_recalc,
2455 };
2456
2457 static struct clk per_48m_fck = {
2458         .name           = "per_48m_fck",
2459         .ops            = &clkops_null,
2460         .parent         = &omap_48m_fck,
2461         .clkdm_name     = "per_clkdm",
2462         .recalc         = &followparent_recalc,
2463 };
2464
2465 static struct clk uart3_fck = {
2466         .name           = "uart3_fck",
2467         .ops            = &clkops_omap2_dflt_wait,
2468         .parent         = &per_48m_fck,
2469         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2470         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2471         .clkdm_name     = "per_clkdm",
2472         .recalc         = &followparent_recalc,
2473 };
2474
2475 static struct clk uart4_fck = {
2476         .name           = "uart4_fck",
2477         .ops            = &clkops_omap2_dflt_wait,
2478         .parent         = &per_48m_fck,
2479         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2480         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2481         .clkdm_name     = "per_clkdm",
2482         .recalc         = &followparent_recalc,
2483 };
2484
2485 static struct clk uart4_fck_am35xx = {
2486         .name           = "uart4_fck",
2487         .ops            = &clkops_omap2_dflt_wait,
2488         .parent         = &per_48m_fck,
2489         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2490         .enable_bit     = OMAP3430_EN_UART4_SHIFT,
2491         .clkdm_name     = "core_l4_clkdm",
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk gpt2_fck = {
2496         .name           = "gpt2_fck",
2497         .ops            = &clkops_omap2_dflt_wait,
2498         .init           = &omap2_init_clksel_parent,
2499         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2500         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2501         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2502         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2503         .clksel         = omap343x_gpt_clksel,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &omap2_clksel_recalc,
2506 };
2507
2508 static struct clk gpt3_fck = {
2509         .name           = "gpt3_fck",
2510         .ops            = &clkops_omap2_dflt_wait,
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .clkdm_name     = "per_clkdm",
2518         .recalc         = &omap2_clksel_recalc,
2519 };
2520
2521 static struct clk gpt4_fck = {
2522         .name           = "gpt4_fck",
2523         .ops            = &clkops_omap2_dflt_wait,
2524         .init           = &omap2_init_clksel_parent,
2525         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2526         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2527         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2528         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2529         .clksel         = omap343x_gpt_clksel,
2530         .clkdm_name     = "per_clkdm",
2531         .recalc         = &omap2_clksel_recalc,
2532 };
2533
2534 static struct clk gpt5_fck = {
2535         .name           = "gpt5_fck",
2536         .ops            = &clkops_omap2_dflt_wait,
2537         .init           = &omap2_init_clksel_parent,
2538         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2539         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2540         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2541         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2542         .clksel         = omap343x_gpt_clksel,
2543         .clkdm_name     = "per_clkdm",
2544         .recalc         = &omap2_clksel_recalc,
2545 };
2546
2547 static struct clk gpt6_fck = {
2548         .name           = "gpt6_fck",
2549         .ops            = &clkops_omap2_dflt_wait,
2550         .init           = &omap2_init_clksel_parent,
2551         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2552         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2553         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2554         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2555         .clksel         = omap343x_gpt_clksel,
2556         .clkdm_name     = "per_clkdm",
2557         .recalc         = &omap2_clksel_recalc,
2558 };
2559
2560 static struct clk gpt7_fck = {
2561         .name           = "gpt7_fck",
2562         .ops            = &clkops_omap2_dflt_wait,
2563         .init           = &omap2_init_clksel_parent,
2564         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2565         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2566         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2567         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2568         .clksel         = omap343x_gpt_clksel,
2569         .clkdm_name     = "per_clkdm",
2570         .recalc         = &omap2_clksel_recalc,
2571 };
2572
2573 static struct clk gpt8_fck = {
2574         .name           = "gpt8_fck",
2575         .ops            = &clkops_omap2_dflt_wait,
2576         .init           = &omap2_init_clksel_parent,
2577         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2579         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2580         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2581         .clksel         = omap343x_gpt_clksel,
2582         .clkdm_name     = "per_clkdm",
2583         .recalc         = &omap2_clksel_recalc,
2584 };
2585
2586 static struct clk gpt9_fck = {
2587         .name           = "gpt9_fck",
2588         .ops            = &clkops_omap2_dflt_wait,
2589         .init           = &omap2_init_clksel_parent,
2590         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2591         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2592         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2593         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2594         .clksel         = omap343x_gpt_clksel,
2595         .clkdm_name     = "per_clkdm",
2596         .recalc         = &omap2_clksel_recalc,
2597 };
2598
2599 static struct clk per_32k_alwon_fck = {
2600         .name           = "per_32k_alwon_fck",
2601         .ops            = &clkops_null,
2602         .parent         = &omap_32k_fck,
2603         .clkdm_name     = "per_clkdm",
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk gpio6_dbck = {
2608         .name           = "gpio6_dbck",
2609         .ops            = &clkops_omap2_dflt,
2610         .parent         = &per_32k_alwon_fck,
2611         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2612         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2613         .clkdm_name     = "per_clkdm",
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk gpio5_dbck = {
2618         .name           = "gpio5_dbck",
2619         .ops            = &clkops_omap2_dflt,
2620         .parent         = &per_32k_alwon_fck,
2621         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2622         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2623         .clkdm_name     = "per_clkdm",
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk gpio4_dbck = {
2628         .name           = "gpio4_dbck",
2629         .ops            = &clkops_omap2_dflt,
2630         .parent         = &per_32k_alwon_fck,
2631         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2632         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2633         .clkdm_name     = "per_clkdm",
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk gpio3_dbck = {
2638         .name           = "gpio3_dbck",
2639         .ops            = &clkops_omap2_dflt,
2640         .parent         = &per_32k_alwon_fck,
2641         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2642         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2643         .clkdm_name     = "per_clkdm",
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk gpio2_dbck = {
2648         .name           = "gpio2_dbck",
2649         .ops            = &clkops_omap2_dflt,
2650         .parent         = &per_32k_alwon_fck,
2651         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2652         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2653         .clkdm_name     = "per_clkdm",
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk wdt3_fck = {
2658         .name           = "wdt3_fck",
2659         .ops            = &clkops_omap2_dflt_wait,
2660         .parent         = &per_32k_alwon_fck,
2661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2662         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2663         .clkdm_name     = "per_clkdm",
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk per_l4_ick = {
2668         .name           = "per_l4_ick",
2669         .ops            = &clkops_null,
2670         .parent         = &l4_ick,
2671         .clkdm_name     = "per_clkdm",
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk gpio6_ick = {
2676         .name           = "gpio6_ick",
2677         .ops            = &clkops_omap2_iclk_dflt_wait,
2678         .parent         = &per_l4_ick,
2679         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2680         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2681         .clkdm_name     = "per_clkdm",
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk gpio5_ick = {
2686         .name           = "gpio5_ick",
2687         .ops            = &clkops_omap2_iclk_dflt_wait,
2688         .parent         = &per_l4_ick,
2689         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2690         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2691         .clkdm_name     = "per_clkdm",
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk gpio4_ick = {
2696         .name           = "gpio4_ick",
2697         .ops            = &clkops_omap2_iclk_dflt_wait,
2698         .parent         = &per_l4_ick,
2699         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2700         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2701         .clkdm_name     = "per_clkdm",
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk gpio3_ick = {
2706         .name           = "gpio3_ick",
2707         .ops            = &clkops_omap2_iclk_dflt_wait,
2708         .parent         = &per_l4_ick,
2709         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2710         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2711         .clkdm_name     = "per_clkdm",
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk gpio2_ick = {
2716         .name           = "gpio2_ick",
2717         .ops            = &clkops_omap2_iclk_dflt_wait,
2718         .parent         = &per_l4_ick,
2719         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2720         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2721         .clkdm_name     = "per_clkdm",
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk wdt3_ick = {
2726         .name           = "wdt3_ick",
2727         .ops            = &clkops_omap2_iclk_dflt_wait,
2728         .parent         = &per_l4_ick,
2729         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2730         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2731         .clkdm_name     = "per_clkdm",
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk uart3_ick = {
2736         .name           = "uart3_ick",
2737         .ops            = &clkops_omap2_iclk_dflt_wait,
2738         .parent         = &per_l4_ick,
2739         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2740         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2741         .clkdm_name     = "per_clkdm",
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static struct clk uart4_ick = {
2746         .name           = "uart4_ick",
2747         .ops            = &clkops_omap2_iclk_dflt_wait,
2748         .parent         = &per_l4_ick,
2749         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2750         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2751         .clkdm_name     = "per_clkdm",
2752         .recalc         = &followparent_recalc,
2753 };
2754
2755 static struct clk gpt9_ick = {
2756         .name           = "gpt9_ick",
2757         .ops            = &clkops_omap2_iclk_dflt_wait,
2758         .parent         = &per_l4_ick,
2759         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2760         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2761         .clkdm_name     = "per_clkdm",
2762         .recalc         = &followparent_recalc,
2763 };
2764
2765 static struct clk gpt8_ick = {
2766         .name           = "gpt8_ick",
2767         .ops            = &clkops_omap2_iclk_dflt_wait,
2768         .parent         = &per_l4_ick,
2769         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2770         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2771         .clkdm_name     = "per_clkdm",
2772         .recalc         = &followparent_recalc,
2773 };
2774
2775 static struct clk gpt7_ick = {
2776         .name           = "gpt7_ick",
2777         .ops            = &clkops_omap2_iclk_dflt_wait,
2778         .parent         = &per_l4_ick,
2779         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2780         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2781         .clkdm_name     = "per_clkdm",
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpt6_ick = {
2786         .name           = "gpt6_ick",
2787         .ops            = &clkops_omap2_iclk_dflt_wait,
2788         .parent         = &per_l4_ick,
2789         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2790         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2791         .clkdm_name     = "per_clkdm",
2792         .recalc         = &followparent_recalc,
2793 };
2794
2795 static struct clk gpt5_ick = {
2796         .name           = "gpt5_ick",
2797         .ops            = &clkops_omap2_iclk_dflt_wait,
2798         .parent         = &per_l4_ick,
2799         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2800         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2801         .clkdm_name     = "per_clkdm",
2802         .recalc         = &followparent_recalc,
2803 };
2804
2805 static struct clk gpt4_ick = {
2806         .name           = "gpt4_ick",
2807         .ops            = &clkops_omap2_iclk_dflt_wait,
2808         .parent         = &per_l4_ick,
2809         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2810         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2811         .clkdm_name     = "per_clkdm",
2812         .recalc         = &followparent_recalc,
2813 };
2814
2815 static struct clk gpt3_ick = {
2816         .name           = "gpt3_ick",
2817         .ops            = &clkops_omap2_iclk_dflt_wait,
2818         .parent         = &per_l4_ick,
2819         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2820         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2821         .clkdm_name     = "per_clkdm",
2822         .recalc         = &followparent_recalc,
2823 };
2824
2825 static struct clk gpt2_ick = {
2826         .name           = "gpt2_ick",
2827         .ops            = &clkops_omap2_iclk_dflt_wait,
2828         .parent         = &per_l4_ick,
2829         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2830         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2831         .clkdm_name     = "per_clkdm",
2832         .recalc         = &followparent_recalc,
2833 };
2834
2835 static struct clk mcbsp2_ick = {
2836         .name           = "mcbsp2_ick",
2837         .ops            = &clkops_omap2_iclk_dflt_wait,
2838         .parent         = &per_l4_ick,
2839         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2840         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2841         .clkdm_name     = "per_clkdm",
2842         .recalc         = &followparent_recalc,
2843 };
2844
2845 static struct clk mcbsp3_ick = {
2846         .name           = "mcbsp3_ick",
2847         .ops            = &clkops_omap2_iclk_dflt_wait,
2848         .parent         = &per_l4_ick,
2849         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2850         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2851         .clkdm_name     = "per_clkdm",
2852         .recalc         = &followparent_recalc,
2853 };
2854
2855 static struct clk mcbsp4_ick = {
2856         .name           = "mcbsp4_ick",
2857         .ops            = &clkops_omap2_iclk_dflt_wait,
2858         .parent         = &per_l4_ick,
2859         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2860         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2861         .clkdm_name     = "per_clkdm",
2862         .recalc         = &followparent_recalc,
2863 };
2864
2865 static const struct clksel mcbsp_234_clksel[] = {
2866         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2867         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2868         { .parent = NULL }
2869 };
2870
2871 static struct clk mcbsp2_fck = {
2872         .name           = "mcbsp2_fck",
2873         .ops            = &clkops_omap2_dflt_wait,
2874         .init           = &omap2_init_clksel_parent,
2875         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2876         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2877         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2878         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2879         .clksel         = mcbsp_234_clksel,
2880         .clkdm_name     = "per_clkdm",
2881         .recalc         = &omap2_clksel_recalc,
2882 };
2883
2884 static struct clk mcbsp3_fck = {
2885         .name           = "mcbsp3_fck",
2886         .ops            = &clkops_omap2_dflt_wait,
2887         .init           = &omap2_init_clksel_parent,
2888         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2889         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2890         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2891         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2892         .clksel         = mcbsp_234_clksel,
2893         .clkdm_name     = "per_clkdm",
2894         .recalc         = &omap2_clksel_recalc,
2895 };
2896
2897 static struct clk mcbsp4_fck = {
2898         .name           = "mcbsp4_fck",
2899         .ops            = &clkops_omap2_dflt_wait,
2900         .init           = &omap2_init_clksel_parent,
2901         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2902         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2903         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2904         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2905         .clksel         = mcbsp_234_clksel,
2906         .clkdm_name     = "per_clkdm",
2907         .recalc         = &omap2_clksel_recalc,
2908 };
2909
2910 /* EMU clocks */
2911
2912 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2913
2914 static const struct clksel_rate emu_src_sys_rates[] = {
2915         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2916         { .div = 0 },
2917 };
2918
2919 static const struct clksel_rate emu_src_core_rates[] = {
2920         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2921         { .div = 0 },
2922 };
2923
2924 static const struct clksel_rate emu_src_per_rates[] = {
2925         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2926         { .div = 0 },
2927 };
2928
2929 static const struct clksel_rate emu_src_mpu_rates[] = {
2930         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2931         { .div = 0 },
2932 };
2933
2934 static const struct clksel emu_src_clksel[] = {
2935         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2936         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2937         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2938         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2939         { .parent = NULL },
2940 };
2941
2942 /*
2943  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2944  * to switch the source of some of the EMU clocks.
2945  * XXX Are there CLKEN bits for these EMU clks?
2946  */
2947 static struct clk emu_src_ck = {
2948         .name           = "emu_src_ck",
2949         .ops            = &clkops_null,
2950         .init           = &omap2_init_clksel_parent,
2951         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2952         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2953         .clksel         = emu_src_clksel,
2954         .clkdm_name     = "emu_clkdm",
2955         .recalc         = &omap2_clksel_recalc,
2956 };
2957
2958 static const struct clksel_rate pclk_emu_rates[] = {
2959         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2960         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2961         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2962         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2963         { .div = 0 },
2964 };
2965
2966 static const struct clksel pclk_emu_clksel[] = {
2967         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2968         { .parent = NULL },
2969 };
2970
2971 static struct clk pclk_fck = {
2972         .name           = "pclk_fck",
2973         .ops            = &clkops_null,
2974         .init           = &omap2_init_clksel_parent,
2975         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2976         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2977         .clksel         = pclk_emu_clksel,
2978         .clkdm_name     = "emu_clkdm",
2979         .recalc         = &omap2_clksel_recalc,
2980 };
2981
2982 static const struct clksel_rate pclkx2_emu_rates[] = {
2983         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2984         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2985         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2986         { .div = 0 },
2987 };
2988
2989 static const struct clksel pclkx2_emu_clksel[] = {
2990         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2991         { .parent = NULL },
2992 };
2993
2994 static struct clk pclkx2_fck = {
2995         .name           = "pclkx2_fck",
2996         .ops            = &clkops_null,
2997         .init           = &omap2_init_clksel_parent,
2998         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2999         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3000         .clksel         = pclkx2_emu_clksel,
3001         .clkdm_name     = "emu_clkdm",
3002         .recalc         = &omap2_clksel_recalc,
3003 };
3004
3005 static const struct clksel atclk_emu_clksel[] = {
3006         { .parent = &emu_src_ck, .rates = div2_rates },
3007         { .parent = NULL },
3008 };
3009
3010 static struct clk atclk_fck = {
3011         .name           = "atclk_fck",
3012         .ops            = &clkops_null,
3013         .init           = &omap2_init_clksel_parent,
3014         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3015         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3016         .clksel         = atclk_emu_clksel,
3017         .clkdm_name     = "emu_clkdm",
3018         .recalc         = &omap2_clksel_recalc,
3019 };
3020
3021 static struct clk traceclk_src_fck = {
3022         .name           = "traceclk_src_fck",
3023         .ops            = &clkops_null,
3024         .init           = &omap2_init_clksel_parent,
3025         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3026         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3027         .clksel         = emu_src_clksel,
3028         .clkdm_name     = "emu_clkdm",
3029         .recalc         = &omap2_clksel_recalc,
3030 };
3031
3032 static const struct clksel_rate traceclk_rates[] = {
3033         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3034         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3035         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3036         { .div = 0 },
3037 };
3038
3039 static const struct clksel traceclk_clksel[] = {
3040         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3041         { .parent = NULL },
3042 };
3043
3044 static struct clk traceclk_fck = {
3045         .name           = "traceclk_fck",
3046         .ops            = &clkops_null,
3047         .init           = &omap2_init_clksel_parent,
3048         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3049         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3050         .clksel         = traceclk_clksel,
3051         .clkdm_name     = "emu_clkdm",
3052         .recalc         = &omap2_clksel_recalc,
3053 };
3054
3055 /* SR clocks */
3056
3057 /* SmartReflex fclk (VDD1) */
3058 static struct clk sr1_fck = {
3059         .name           = "sr1_fck",
3060         .ops            = &clkops_omap2_dflt_wait,
3061         .parent         = &sys_ck,
3062         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3063         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3064         .clkdm_name     = "wkup_clkdm",
3065         .recalc         = &followparent_recalc,
3066 };
3067
3068 /* SmartReflex fclk (VDD2) */
3069 static struct clk sr2_fck = {
3070         .name           = "sr2_fck",
3071         .ops            = &clkops_omap2_dflt_wait,
3072         .parent         = &sys_ck,
3073         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3074         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3075         .clkdm_name     = "wkup_clkdm",
3076         .recalc         = &followparent_recalc,
3077 };
3078
3079 static struct clk sr_l4_ick = {
3080         .name           = "sr_l4_ick",
3081         .ops            = &clkops_null, /* RMK: missing? */
3082         .parent         = &l4_ick,
3083         .clkdm_name     = "core_l4_clkdm",
3084         .recalc         = &followparent_recalc,
3085 };
3086
3087 /* SECURE_32K_FCK clocks */
3088
3089 static struct clk gpt12_fck = {
3090         .name           = "gpt12_fck",
3091         .ops            = &clkops_null,
3092         .parent         = &secure_32k_fck,
3093         .clkdm_name     = "wkup_clkdm",
3094         .recalc         = &followparent_recalc,
3095 };
3096
3097 static struct clk wdt1_fck = {
3098         .name           = "wdt1_fck",
3099         .ops            = &clkops_null,
3100         .parent         = &secure_32k_fck,
3101         .clkdm_name     = "wkup_clkdm",
3102         .recalc         = &followparent_recalc,
3103 };
3104
3105 /* Clocks for AM35XX */
3106 static struct clk ipss_ick = {
3107         .name           = "ipss_ick",
3108         .ops            = &clkops_am35xx_ipss_wait,
3109         .parent         = &core_l3_ick,
3110         .clkdm_name     = "core_l3_clkdm",
3111         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3112         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3113         .recalc         = &followparent_recalc,
3114 };
3115
3116 static struct clk emac_ick = {
3117         .name           = "emac_ick",
3118         .ops            = &clkops_am35xx_ipss_module_wait,
3119         .parent         = &ipss_ick,
3120         .clkdm_name     = "core_l3_clkdm",
3121         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3122         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3123         .recalc         = &followparent_recalc,
3124 };
3125
3126 static struct clk rmii_ck = {
3127         .name           = "rmii_ck",
3128         .ops            = &clkops_null,
3129         .rate           = 50000000,
3130 };
3131
3132 static struct clk emac_fck = {
3133         .name           = "emac_fck",
3134         .ops            = &clkops_omap2_dflt,
3135         .parent         = &rmii_ck,
3136         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3137         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3138         .recalc         = &followparent_recalc,
3139 };
3140
3141 static struct clk hsotgusb_ick_am35xx = {
3142         .name           = "hsotgusb_ick",
3143         .ops            = &clkops_am35xx_ipss_module_wait,
3144         .parent         = &ipss_ick,
3145         .clkdm_name     = "core_l3_clkdm",
3146         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3147         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3148         .recalc         = &followparent_recalc,
3149 };
3150
3151 static struct clk hsotgusb_fck_am35xx = {
3152         .name           = "hsotgusb_fck",
3153         .ops            = &clkops_omap2_dflt,
3154         .parent         = &sys_ck,
3155         .clkdm_name     = "core_l3_clkdm",
3156         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3157         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3158         .recalc         = &followparent_recalc,
3159 };
3160
3161 static struct clk hecc_ck = {
3162         .name           = "hecc_ck",
3163         .ops            = &clkops_am35xx_ipss_module_wait,
3164         .parent         = &sys_ck,
3165         .clkdm_name     = "core_l3_clkdm",
3166         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3167         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3168         .recalc         = &followparent_recalc,
3169 };
3170
3171 static struct clk vpfe_ick = {
3172         .name           = "vpfe_ick",
3173         .ops            = &clkops_am35xx_ipss_module_wait,
3174         .parent         = &ipss_ick,
3175         .clkdm_name     = "core_l3_clkdm",
3176         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3177         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3178         .recalc         = &followparent_recalc,
3179 };
3180
3181 static struct clk pclk_ck = {
3182         .name           = "pclk_ck",
3183         .ops            = &clkops_null,
3184         .rate           = 27000000,
3185 };
3186
3187 static struct clk vpfe_fck = {
3188         .name           = "vpfe_fck",
3189         .ops            = &clkops_omap2_dflt,
3190         .parent         = &pclk_ck,
3191         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3192         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3193         .recalc         = &followparent_recalc,
3194 };
3195
3196 /*
3197  * The UART1/2 functional clock acts as the functional
3198  * clock for UART4. No separate fclk control available.
3199  */
3200 static struct clk uart4_ick_am35xx = {
3201         .name           = "uart4_ick",
3202         .ops            = &clkops_omap2_iclk_dflt_wait,
3203         .parent         = &core_l4_ick,
3204         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3205         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3206         .clkdm_name     = "core_l4_clkdm",
3207         .recalc         = &followparent_recalc,
3208 };
3209
3210 static struct clk dummy_apb_pclk = {
3211         .name           = "apb_pclk",
3212         .ops            = &clkops_null,
3213 };
3214
3215 /*
3216  * clkdev
3217  */
3218
3219 /* XXX At some point we should rename this file to clock3xxx_data.c */
3220 static struct omap_clk omap3xxx_clks[] = {
3221         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
3222         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3223         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3224         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3225         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3226         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3227         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
3228         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3229         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3230         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3231         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3232         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3233         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3234         CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3235         CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3236         CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3237         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3238         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3239         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3240         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3241         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3242         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
3243         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
3244         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3245         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3246         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3247         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3248         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3249         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3250         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3251         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3252         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3253         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3254         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3255         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3256         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3257         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3258         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3259         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3260         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3261         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3262         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3263         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3264         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3265         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3266         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3267         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3268         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3269         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3270         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3271         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3272         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3273         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3274         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3275         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3276         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3277         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3278         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3279         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3280         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3281         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
3282         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
3283         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3284         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3285         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3286         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3287         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3288         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3289         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3290         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3291         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3292         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3293         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3294         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
3295         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
3296         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
3297         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3298         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3299         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3301         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3302         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3303         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3304         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3305         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3306         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3307         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
3308         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
3309         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
3310         CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
3311         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
3312         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
3313         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
3314         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
3315         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3316         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
3317         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
3318         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
3319         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
3320         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3321         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3322         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3323         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3324         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
3325         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3326         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3327         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3328         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3329         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3330         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3331         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3332         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3333         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3334         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3335         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
3336         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3337         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3338         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3339         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3340         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
3341         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
3342         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
3343         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
3344         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
3345         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
3346         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
3347         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3348         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3349         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3350         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3351         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3352         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
3353         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
3354         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
3355         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3356         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3357         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3358         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3359         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3360         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3361         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3362         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3363         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3364         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
3365         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3366         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
3367         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3368         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3369         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
3370         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
3371         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
3372         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
3373         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
3374         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3375         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
3376         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
3377         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
3378         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
3379         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3380         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
3381         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
3382         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
3383         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3384         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3385         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3386         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387         CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
3388         CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
3389         CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
3390         CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
3391         CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
3392         CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
3393         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3394         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3395         CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
3396         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
3397         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3398         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3399         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3400         CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
3401         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
3402         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
3403         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3404         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3405         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3406         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3407         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3408         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3409         CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3410         CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3411         CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3412         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3413         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3414         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3415         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
3416         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
3417         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3418         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3419         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3420         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3421         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3422         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3423         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3424         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3425         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3426         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3427         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3428         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3429         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3430         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3431         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3432         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3433         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3434         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3435         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3436         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3437         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3438         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3439         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3440         CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
3441         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3442         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3443         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3444         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3445         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3446         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3447         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3448         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3449         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3450         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3451         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3452         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
3453         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
3454         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
3455         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3456         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3457         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3458         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3459         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3460         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3461         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
3462         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
3463         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
3464         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3465         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3466         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3467         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3468         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3469         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3470         CLK("davinci_emac",     "emac_clk",     &emac_ick,      CK_AM35XX),
3471         CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
3472         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3473         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3474         CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
3475         CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
3476         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3477         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3478         CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3479         CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3480         CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3481         CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3482         CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3483         CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3484         CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3485         CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3486         CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3487         CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3488         CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3489         CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3490         CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
3491         CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
3492         CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
3493         CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
3494         CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
3495         CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
3496         CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
3497         CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
3498         CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
3499         CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
3500         CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
3501         CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
3502 };
3503
3504
3505 int __init omap3xxx_clk_init(void)
3506 {
3507         struct omap_clk *c;
3508         u32 cpu_clkflg = 0;
3509
3510         /*
3511          * 3505 must be tested before 3517, since 3517 returns true
3512          * for both AM3517 chips and AM3517 family chips, which
3513          * includes 3505.  Unfortunately there's no obvious family
3514          * test for 3517/3505 :-(
3515          */
3516         if (cpu_is_omap3505()) {
3517                 cpu_mask = RATE_IN_34XX;
3518                 cpu_clkflg = CK_3505;
3519         } else if (cpu_is_omap3517()) {
3520                 cpu_mask = RATE_IN_34XX;
3521                 cpu_clkflg = CK_3517;
3522         } else if (cpu_is_omap3505()) {
3523                 cpu_mask = RATE_IN_34XX;
3524                 cpu_clkflg = CK_3505;
3525         } else if (cpu_is_omap3630()) {
3526                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3527                 cpu_clkflg = CK_36XX;
3528         } else if (cpu_is_ti816x()) {
3529                 cpu_mask = RATE_IN_TI816X;
3530                 cpu_clkflg = CK_TI816X;
3531         } else if (cpu_is_am33xx()) {
3532                 cpu_mask = RATE_IN_AM33XX;
3533         } else if (cpu_is_ti814x()) {
3534                 cpu_mask = RATE_IN_TI814X;
3535         } else if (cpu_is_omap34xx()) {
3536                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3537                         cpu_mask = RATE_IN_3430ES1;
3538                         cpu_clkflg = CK_3430ES1;
3539                 } else {
3540                         /*
3541                          * Assume that anything that we haven't matched yet
3542                          * has 3430ES2-type clocks.
3543                          */
3544                         cpu_mask = RATE_IN_3430ES2PLUS;
3545                         cpu_clkflg = CK_3430ES2PLUS;
3546                 }
3547         } else {
3548                 WARN(1, "clock: could not identify OMAP3 variant\n");
3549         }
3550
3551         if (omap3_has_192mhz_clk())
3552                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3553
3554         if (cpu_is_omap3630()) {
3555                 /*
3556                  * XXX This type of dynamic rewriting of the clock tree is
3557                  * deprecated and should be revised soon.
3558                  *
3559                  * For 3630: override clkops_omap2_dflt_wait for the
3560                  * clocks affected from PWRDN reset Limitation
3561                  */
3562                 dpll3_m3x2_ck.ops =
3563                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3564                 dpll4_m2x2_ck.ops =
3565                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3566                 dpll4_m3x2_ck.ops =
3567                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3568                 dpll4_m4x2_ck.ops =
3569                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3570                 dpll4_m5x2_ck.ops =
3571                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3572                 dpll4_m6x2_ck.ops =
3573                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3574         }
3575
3576         /*
3577          * XXX This type of dynamic rewriting of the clock tree is
3578          * deprecated and should be revised soon.
3579          */
3580         if (cpu_is_omap3630())
3581                 dpll4_dd = dpll4_dd_3630;
3582         else
3583                 dpll4_dd = dpll4_dd_34xx;
3584
3585         clk_init(&omap2_clk_functions);
3586
3587         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3588              c++)
3589                 clk_preinit(c->lk.clk);
3590
3591         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3592              c++)
3593                 if (c->cpu & cpu_clkflg) {
3594                         clkdev_add(&c->lk);
3595                         clk_register(c->lk.clk);
3596                         omap2_init_clk_clkdm(c->lk.clk);
3597                 }
3598
3599         /* Disable autoidle on all clocks; let the PM code enable it later */
3600         omap_clk_disable_autoidle_all();
3601
3602         recalculate_root_clocks();
3603
3604         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3605                 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3606                 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3607
3608         /*
3609          * Only enable those clocks we will need, let the drivers
3610          * enable other clocks as necessary
3611          */
3612         clk_enable_init_clocks();
3613
3614         /*
3615          * Lock DPLL5 -- here only until other device init code can
3616          * handle this
3617          */
3618         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3619                 omap3_clk_lock_dpll5();
3620
3621         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3622         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3623         arm_fck_p = clk_get(NULL, "arm_fck");
3624
3625         return 0;
3626 }