arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c

   1 /*
   2  * OMAP2/3 clockdomains
   3  *
   4  * Copyright (C) 2008-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley, Jouni Högander
   8  *
   9  * This file contains clockdomains and clockdomain wakeup/sleep
  10  * dependencies for the OMAP2/3 chips.  Some notes:
  11  *
  12  * A useful validation rule for struct clockdomain: Any clockdomain
  13  * referenced by a wkdep_srcs or sleepdep_srcs array must have a
  14  * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
  15  * software-controllable dependencies.  Non-software-controllable
  16  * dependencies do exist, but they are not encoded below (yet).
  17  *
  18  * 24xx does not support programmable sleep dependencies (SLEEPDEP)
  19  *
  20  * The overly-specific dep_bit names are due to a bit name collision
  21  * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
  22  * value are the same for all powerdomains: 2
  23  *
  24  * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
  25  * sanity check?
  26  * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
  27  */
  28
  29 /*
  30  * To-Do List
  31  * -> Port the Sleep/Wakeup dependencies for the domains
  32  *    from the Power domain framework
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37
  38 #include <plat/clockdomain.h>
  39 #include "prm2xxx_3xxx.h"
  40 #include "cm2xxx_3xxx.h"
  41 #include "cm-regbits-24xx.h"
  42 #include "cm-regbits-34xx.h"
  43 #include "cm-regbits-44xx.h"
  44 #include "prm-regbits-24xx.h"
  45 #include "prm-regbits-34xx.h"
  46
  47 /*
  48  * Clockdomain dependencies for wkdeps/sleepdeps
  49  *
  50  * XXX Hardware dependencies (e.g., dependencies that cannot be
  51  * changed in software) are not included here yet, but should be.
  52  */
  53
  54 /* OMAP2/3-common wakeup dependencies */
  55
  56 /*
  57  * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
  58  * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
  59  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  60  * These can share data since they will never be present simultaneously
  61  * on the same device.
  62  */
  63 static struct clkdm_dep gfx_sgx_wkdeps[] = {
  64         {
  65                 .clkdm_name = "core_l3_clkdm",
  66                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  67         },
  68         {
  69                 .clkdm_name = "core_l4_clkdm",
  70                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  71         },
  72         {
  73                 .clkdm_name = "iva2_clkdm",
  74                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  75         },
  76         {
  77                 .clkdm_name = "mpu_clkdm",
  78                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  79                                             CHIP_IS_OMAP3430)
  80         },
  81         {
  82                 .clkdm_name = "wkup_clkdm",
  83                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  84                                             CHIP_IS_OMAP3430)
  85         },
  86         { NULL },
  87 };
  88
  89
  90 /* 24XX-specific possible dependencies */
  91
  92 /* Wakeup dependency source arrays */
  93
  94 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
  95 static struct clkdm_dep dsp_24xx_wkdeps[] = {
  96         {
  97                 .clkdm_name = "core_l3_clkdm",
  98                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  99         },
 100         {
 101                 .clkdm_name = "core_l4_clkdm",
 102                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 103         },
 104         {
 105                 .clkdm_name = "mpu_clkdm",
 106                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 107         },
 108         {
 109                 .clkdm_name = "wkup_clkdm",
 110                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 111         },
 112         { NULL },
 113 };
 114
 115 /*
 116  * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
 117  * 2430 adds MDM
 118  */
 119 static struct clkdm_dep mpu_24xx_wkdeps[] = {
 120         {
 121                 .clkdm_name = "core_l3_clkdm",
 122                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 123         },
 124         {
 125                 .clkdm_name = "core_l4_clkdm",
 126                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 127         },
 128         {
 129                 .clkdm_name = "dsp_clkdm",
 130                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 131         },
 132         {
 133                 .clkdm_name = "wkup_clkdm",
 134                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 135         },
 136         {
 137                 .clkdm_name = "mdm_clkdm",
 138                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 139         },
 140         { NULL },
 141 };
 142
 143 /*
 144  * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
 145  * 2430 adds MDM
 146  */
 147 static struct clkdm_dep core_24xx_wkdeps[] = {
 148         {
 149                 .clkdm_name = "dsp_clkdm",
 150                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 151         },
 152         {
 153                 .clkdm_name = "gfx_clkdm",
 154                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 155         },
 156         {
 157                 .clkdm_name = "mpu_clkdm",
 158                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 159         },
 160         {
 161                 .clkdm_name = "wkup_clkdm",
 162                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 163         },
 164         {
 165                 .clkdm_name = "mdm_clkdm",
 166                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 167         },
 168         { NULL },
 169 };
 170
 171
 172 /* 2430-specific possible wakeup dependencies */
 173
 174 #ifdef CONFIG_ARCH_OMAP2430
 175
 176 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
 177 static struct clkdm_dep mdm_2430_wkdeps[] = {
 178         {
 179                 .clkdm_name = "core_l3_clkdm",
 180                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 181         },
 182         {
 183                 .clkdm_name = "core_l4_clkdm",
 184                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 185         },
 186         {
 187                 .clkdm_name = "mpu_clkdm",
 188                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 189         },
 190         {
 191                 .clkdm_name = "wkup_clkdm",
 192                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 193         },
 194         { NULL },
 195 };
 196
 197 #endif /* CONFIG_ARCH_OMAP2430 */
 198
 199
 200 /* OMAP3-specific possible dependencies */
 201
 202 #ifdef CONFIG_ARCH_OMAP3
 203
 204 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 205 static struct clkdm_dep per_wkdeps[] = {
 206         {
 207                 .clkdm_name = "core_l3_clkdm",
 208                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 209         },
 210         {
 211                 .clkdm_name = "core_l4_clkdm",
 212                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 213         },
 214         {
 215                 .clkdm_name = "iva2_clkdm",
 216                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 217         },
 218         {
 219                 .clkdm_name = "mpu_clkdm",
 220                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 221         },
 222         {
 223                 .clkdm_name = "wkup_clkdm",
 224                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 225         },
 226         { NULL },
 227 };
 228
 229 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 230 static struct clkdm_dep usbhost_wkdeps[] = {
 231         {
 232                 .clkdm_name = "core_l3_clkdm",
 233                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 234         },
 235         {
 236                 .clkdm_name = "core_l4_clkdm",
 237                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 238         },
 239         {
 240                 .clkdm_name = "iva2_clkdm",
 241                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 242         },
 243         {
 244                 .clkdm_name = "mpu_clkdm",
 245                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 246         },
 247         {
 248                 .clkdm_name = "wkup_clkdm",
 249                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 250         },
 251         { NULL },
 252 };
 253
 254 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 255 static struct clkdm_dep mpu_3xxx_wkdeps[] = {
 256         {
 257                 .clkdm_name = "core_l3_clkdm",
 258                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 259         },
 260         {
 261                 .clkdm_name = "core_l4_clkdm",
 262                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 263         },
 264         {
 265                 .clkdm_name = "iva2_clkdm",
 266                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 267         },
 268         {
 269                 .clkdm_name = "dss_clkdm",
 270                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 271         },
 272         {
 273                 .clkdm_name = "per_clkdm",
 274                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 275         },
 276         { NULL },
 277 };
 278
 279 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 280 static struct clkdm_dep iva2_wkdeps[] = {
 281         {
 282                 .clkdm_name = "core_l3_clkdm",
 283                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 284         },
 285         {
 286                 .clkdm_name = "core_l4_clkdm",
 287                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 288         },
 289         {
 290                 .clkdm_name = "mpu_clkdm",
 291                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 292         },
 293         {
 294                 .clkdm_name = "wkup_clkdm",
 295                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 296         },
 297         {
 298                 .clkdm_name = "dss_clkdm",
 299                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 300         },
 301         {
 302                 .clkdm_name = "per_clkdm",
 303                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 304         },
 305         { NULL },
 306 };
 307
 308
 309 /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
 310 static struct clkdm_dep cam_wkdeps[] = {
 311         {
 312                 .clkdm_name = "iva2_clkdm",
 313                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 314         },
 315         {
 316                 .clkdm_name = "mpu_clkdm",
 317                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 318         },
 319         {
 320                 .clkdm_name = "wkup_clkdm",
 321                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 322         },
 323         { NULL },
 324 };
 325
 326 /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
 327 static struct clkdm_dep dss_wkdeps[] = {
 328         {
 329                 .clkdm_name = "iva2_clkdm",
 330                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 331         },
 332         {
 333                 .clkdm_name = "mpu_clkdm",
 334                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 335         },
 336         {
 337                 .clkdm_name = "wkup_clkdm",
 338                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 339         },
 340         { NULL },
 341 };
 342
 343 /* 3430: PM_WKDEP_NEON: MPU */
 344 static struct clkdm_dep neon_wkdeps[] = {
 345         {
 346                 .clkdm_name = "mpu_clkdm",
 347                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 348         },
 349         { NULL },
 350 };
 351
 352
 353 /* Sleep dependency source arrays for OMAP3-specific clkdms */
 354
 355 /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
 356 static struct clkdm_dep dss_sleepdeps[] = {
 357         {
 358                 .clkdm_name = "mpu_clkdm",
 359                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 360         },
 361         {
 362                 .clkdm_name = "iva2_clkdm",
 363                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 364         },
 365         { NULL },
 366 };
 367
 368 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 369 static struct clkdm_dep per_sleepdeps[] = {
 370         {
 371                 .clkdm_name = "mpu_clkdm",
 372                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 373         },
 374         {
 375                 .clkdm_name = "iva2_clkdm",
 376                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 377         },
 378         { NULL },
 379 };
 380
 381 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 382 static struct clkdm_dep usbhost_sleepdeps[] = {
 383         {
 384                 .clkdm_name = "mpu_clkdm",
 385                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 386         },
 387         {
 388                 .clkdm_name = "iva2_clkdm",
 389                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 390         },
 391         { NULL },
 392 };
 393
 394 /* 3430: CM_SLEEPDEP_CAM: MPU */
 395 static struct clkdm_dep cam_sleepdeps[] = {
 396         {
 397                 .clkdm_name = "mpu_clkdm",
 398                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 399         },
 400         { NULL },
 401 };
 402
 403 /*
 404  * 3430ES1: CM_SLEEPDEP_GFX: MPU
 405  * 3430ES2: CM_SLEEPDEP_SGX: MPU
 406  * These can share data since they will never be present simultaneously
 407  * on the same device.
 408  */
 409 static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 410         {
 411                 .clkdm_name = "mpu_clkdm",
 412                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 413         },
 414         { NULL },
 415 };
 416
 417 #endif /* CONFIG_ARCH_OMAP3 */
 418
 419
 420 /*
 421  * OMAP2/3-common clockdomains
 422  *
 423  * Even though the 2420 has a single PRCM module from the
 424  * interconnect's perspective, internally it does appear to have
 425  * separate PRM and CM clockdomains.  The usual test case is
 426  * sys_clkout/sys_clkout2.
 427  */
 428
 429 /* This is an implicit clockdomain - it is never defined as such in TRM */
 430 static struct clockdomain wkup_clkdm = {
 431         .name           = "wkup_clkdm",
 432         .pwrdm          = { .name = "wkup_pwrdm" },
 433         .dep_bit        = OMAP_EN_WKUP_SHIFT,
 434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 435 };
 436
 437 static struct clockdomain prm_clkdm = {
 438         .name           = "prm_clkdm",
 439         .pwrdm          = { .name = "wkup_pwrdm" },
 440         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 441 };
 442
 443 static struct clockdomain cm_clkdm = {
 444         .name           = "cm_clkdm",
 445         .pwrdm          = { .name = "core_pwrdm" },
 446         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 447 };
 448
 449 /*
 450  * 2420-only clockdomains
 451  */
 452
 453 #if defined(CONFIG_ARCH_OMAP2420)
 454
 455 static struct clockdomain mpu_2420_clkdm = {
 456         .name           = "mpu_clkdm",
 457         .pwrdm          = { .name = "mpu_pwrdm" },
 458         .flags          = CLKDM_CAN_HWSUP,
 459         .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 460         .wkdep_srcs     = mpu_24xx_wkdeps,
 461         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 463 };
 464
 465 static struct clockdomain iva1_2420_clkdm = {
 466         .name           = "iva1_clkdm",
 467         .pwrdm          = { .name = "dsp_pwrdm" },
 468         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 469         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 470                                                  OMAP2_CM_CLKSTCTRL),
 471         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 472         .wkdep_srcs     = dsp_24xx_wkdeps,
 473         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
 474         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 475 };
 476
 477 static struct clockdomain dsp_2420_clkdm = {
 478         .name           = "dsp_clkdm",
 479         .pwrdm          = { .name = "dsp_pwrdm" },
 480         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 481         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 482                                                  OMAP2_CM_CLKSTCTRL),
 483         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 484         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 485 };
 486
 487 static struct clockdomain gfx_2420_clkdm = {
 488         .name           = "gfx_clkdm",
 489         .pwrdm          = { .name = "gfx_pwrdm" },
 490         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 491         .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 492         .wkdep_srcs     = gfx_sgx_wkdeps,
 493         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 495 };
 496
 497 static struct clockdomain core_l3_2420_clkdm = {
 498         .name           = "core_l3_clkdm",
 499         .pwrdm          = { .name = "core_pwrdm" },
 500         .flags          = CLKDM_CAN_HWSUP,
 501         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 502         .wkdep_srcs     = core_24xx_wkdeps,
 503         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 504         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 505 };
 506
 507 static struct clockdomain core_l4_2420_clkdm = {
 508         .name           = "core_l4_clkdm",
 509         .pwrdm          = { .name = "core_pwrdm" },
 510         .flags          = CLKDM_CAN_HWSUP,
 511         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 512         .wkdep_srcs     = core_24xx_wkdeps,
 513         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 514         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 515 };
 516
 517 static struct clockdomain dss_2420_clkdm = {
 518         .name           = "dss_clkdm",
 519         .pwrdm          = { .name = "core_pwrdm" },
 520         .flags          = CLKDM_CAN_HWSUP,
 521         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 522         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 523         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 524 };
 525
 526 #endif   /* CONFIG_ARCH_OMAP2420 */
 527
 528
 529 /*
 530  * 2430-only clockdomains
 531  */
 532
 533 #if defined(CONFIG_ARCH_OMAP2430)
 534
 535 static struct clockdomain mpu_2430_clkdm = {
 536         .name           = "mpu_clkdm",
 537         .pwrdm          = { .name = "mpu_pwrdm" },
 538         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 539         .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
 540                                                  OMAP2_CM_CLKSTCTRL),
 541         .wkdep_srcs     = mpu_24xx_wkdeps,
 542         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 543         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 544 };
 545
 546 /* Another case of bit name collisions between several registers: EN_MDM */
 547 static struct clockdomain mdm_clkdm = {
 548         .name           = "mdm_clkdm",
 549         .pwrdm          = { .name = "mdm_pwrdm" },
 550         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 551         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
 552                                                  OMAP2_CM_CLKSTCTRL),
 553         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
 554         .wkdep_srcs     = mdm_2430_wkdeps,
 555         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
 556         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 557 };
 558
 559 static struct clockdomain dsp_2430_clkdm = {
 560         .name           = "dsp_clkdm",
 561         .pwrdm          = { .name = "dsp_pwrdm" },
 562         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 563         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
 564                                                  OMAP2_CM_CLKSTCTRL),
 565         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 566         .wkdep_srcs     = dsp_24xx_wkdeps,
 567         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 569 };
 570
 571 static struct clockdomain gfx_2430_clkdm = {
 572         .name           = "gfx_clkdm",
 573         .pwrdm          = { .name = "gfx_pwrdm" },
 574         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 575         .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 576         .wkdep_srcs     = gfx_sgx_wkdeps,
 577         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 578         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 579 };
 580
 581 /*
 582  * XXX add usecounting for clkdm dependencies, otherwise the presence
 583  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 584  * could cause trouble
 585  */
 586 static struct clockdomain core_l3_2430_clkdm = {
 587         .name           = "core_l3_clkdm",
 588         .pwrdm          = { .name = "core_pwrdm" },
 589         .flags          = CLKDM_CAN_HWSUP,
 590         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 591         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 592         .wkdep_srcs     = core_24xx_wkdeps,
 593         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 594         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 595 };
 596
 597 /*
 598  * XXX add usecounting for clkdm dependencies, otherwise the presence
 599  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 600  * could cause trouble
 601  */
 602 static struct clockdomain core_l4_2430_clkdm = {
 603         .name           = "core_l4_clkdm",
 604         .pwrdm          = { .name = "core_pwrdm" },
 605         .flags          = CLKDM_CAN_HWSUP,
 606         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 607         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 608         .wkdep_srcs     = core_24xx_wkdeps,
 609         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 610         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 611 };
 612
 613 static struct clockdomain dss_2430_clkdm = {
 614         .name           = "dss_clkdm",
 615         .pwrdm          = { .name = "core_pwrdm" },
 616         .flags          = CLKDM_CAN_HWSUP,
 617         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 618         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 619         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 620 };
 621
 622 #endif    /* CONFIG_ARCH_OMAP2430 */
 623
 624
 625 /*
 626  * OMAP3 clockdomains
 627  */
 628
 629 #if defined(CONFIG_ARCH_OMAP3)
 630
 631 static struct clockdomain mpu_3xxx_clkdm = {
 632         .name           = "mpu_clkdm",
 633         .pwrdm          = { .name = "mpu_pwrdm" },
 634         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 635         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 636         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
 637         .wkdep_srcs     = mpu_3xxx_wkdeps,
 638         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 639         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 640 };
 641
 642 static struct clockdomain neon_clkdm = {
 643         .name           = "neon_clkdm",
 644         .pwrdm          = { .name = "neon_pwrdm" },
 645         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 646         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
 647                                                  OMAP2_CM_CLKSTCTRL),
 648         .wkdep_srcs     = neon_wkdeps,
 649         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 650         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 651 };
 652
 653 static struct clockdomain iva2_clkdm = {
 654         .name           = "iva2_clkdm",
 655         .pwrdm          = { .name = "iva2_pwrdm" },
 656         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 657         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 658                                                  OMAP2_CM_CLKSTCTRL),
 659         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 660         .wkdep_srcs     = iva2_wkdeps,
 661         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 663 };
 664
 665 static struct clockdomain gfx_3430es1_clkdm = {
 666         .name           = "gfx_clkdm",
 667         .pwrdm          = { .name = "gfx_pwrdm" },
 668         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 669         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 670         .wkdep_srcs     = gfx_sgx_wkdeps,
 671         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 672         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 673         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 674 };
 675
 676 static struct clockdomain sgx_clkdm = {
 677         .name           = "sgx_clkdm",
 678         .pwrdm          = { .name = "sgx_pwrdm" },
 679         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 680         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
 681                                                  OMAP2_CM_CLKSTCTRL),
 682         .wkdep_srcs     = gfx_sgx_wkdeps,
 683         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 684         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 685         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 686 };
 687
 688 /*
 689  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 690  * then that information was removed from the 34xx ES2+ TRM.  It is
 691  * unclear whether the core is still there, but the clockdomain logic
 692  * is there, and must be programmed to an appropriate state if the
 693  * CORE clockdomain is to become inactive.
 694  */
 695 static struct clockdomain d2d_clkdm = {
 696         .name           = "d2d_clkdm",
 697         .pwrdm          = { .name = "core_pwrdm" },
 698         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 699         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 700         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 701         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 702 };
 703
 704 /*
 705  * XXX add usecounting for clkdm dependencies, otherwise the presence
 706  * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
 707  * could cause trouble
 708  */
 709 static struct clockdomain core_l3_3xxx_clkdm = {
 710         .name           = "core_l3_clkdm",
 711         .pwrdm          = { .name = "core_pwrdm" },
 712         .flags          = CLKDM_CAN_HWSUP,
 713         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 714         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 715         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 716         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 717 };
 718
 719 /*
 720  * XXX add usecounting for clkdm dependencies, otherwise the presence
 721  * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
 722  * could cause trouble
 723  */
 724 static struct clockdomain core_l4_3xxx_clkdm = {
 725         .name           = "core_l4_clkdm",
 726         .pwrdm          = { .name = "core_pwrdm" },
 727         .flags          = CLKDM_CAN_HWSUP,
 728         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 729         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 730         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 731         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 732 };
 733
 734 /* Another case of bit name collisions between several registers: EN_DSS */
 735 static struct clockdomain dss_3xxx_clkdm = {
 736         .name           = "dss_clkdm",
 737         .pwrdm          = { .name = "dss_pwrdm" },
 738         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 739         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
 740                                                  OMAP2_CM_CLKSTCTRL),
 741         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 742         .wkdep_srcs     = dss_wkdeps,
 743         .sleepdep_srcs  = dss_sleepdeps,
 744         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 745         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 746 };
 747
 748 static struct clockdomain cam_clkdm = {
 749         .name           = "cam_clkdm",
 750         .pwrdm          = { .name = "cam_pwrdm" },
 751         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 752         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
 753                                                  OMAP2_CM_CLKSTCTRL),
 754         .wkdep_srcs     = cam_wkdeps,
 755         .sleepdep_srcs  = cam_sleepdeps,
 756         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 757         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 758 };
 759
 760 static struct clockdomain usbhost_clkdm = {
 761         .name           = "usbhost_clkdm",
 762         .pwrdm          = { .name = "usbhost_pwrdm" },
 763         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 764         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
 765                                                  OMAP2_CM_CLKSTCTRL),
 766         .wkdep_srcs     = usbhost_wkdeps,
 767         .sleepdep_srcs  = usbhost_sleepdeps,
 768         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 769         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 770 };
 771
 772 static struct clockdomain per_clkdm = {
 773         .name           = "per_clkdm",
 774         .pwrdm          = { .name = "per_pwrdm" },
 775         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 776         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
 777                                                  OMAP2_CM_CLKSTCTRL),
 778         .dep_bit        = OMAP3430_EN_PER_SHIFT,
 779         .wkdep_srcs     = per_wkdeps,
 780         .sleepdep_srcs  = per_sleepdeps,
 781         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 783 };
 784
 785 /*
 786  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 787  * switched of even if sdti is in use
 788  */
 789 static struct clockdomain emu_clkdm = {
 790         .name           = "emu_clkdm",
 791         .pwrdm          = { .name = "emu_pwrdm" },
 792         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
 793         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
 794                                                  OMAP2_CM_CLKSTCTRL),
 795         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 796         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 797 };
 798
 799 static struct clockdomain dpll1_clkdm = {
 800         .name           = "dpll1_clkdm",
 801         .pwrdm          = { .name = "dpll1_pwrdm" },
 802         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 803 };
 804
 805 static struct clockdomain dpll2_clkdm = {
 806         .name           = "dpll2_clkdm",
 807         .pwrdm          = { .name = "dpll2_pwrdm" },
 808         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 809 };
 810
 811 static struct clockdomain dpll3_clkdm = {
 812         .name           = "dpll3_clkdm",
 813         .pwrdm          = { .name = "dpll3_pwrdm" },
 814         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 815 };
 816
 817 static struct clockdomain dpll4_clkdm = {
 818         .name           = "dpll4_clkdm",
 819         .pwrdm          = { .name = "dpll4_pwrdm" },
 820         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 821 };
 822
 823 static struct clockdomain dpll5_clkdm = {
 824         .name           = "dpll5_clkdm",
 825         .pwrdm          = { .name = "dpll5_pwrdm" },
 826         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 827 };
 828
 829 #endif   /* CONFIG_ARCH_OMAP3 */
 830
 831 /*
 832  * Clockdomain hwsup dependencies (OMAP3 only)
 833  */
 834
 835 static struct clkdm_autodep clkdm_autodeps[] = {
 836         {
 837                 .clkdm     = { .name = "mpu_clkdm" },
 838                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 839         },
 840         {
 841                 .clkdm     = { .name = "iva2_clkdm" },
 842                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 843         },
 844         {
 845                 .clkdm     = { .name = NULL },
 846         }
 847 };
 848
 849 static struct clockdomain *clockdomains_omap2[] __initdata = {
 850         &wkup_clkdm,
 851         &cm_clkdm,
 852         &prm_clkdm,
 853
 854 #ifdef CONFIG_ARCH_OMAP2420
 855         &mpu_2420_clkdm,
 856         &iva1_2420_clkdm,
 857         &dsp_2420_clkdm,
 858         &gfx_2420_clkdm,
 859         &core_l3_2420_clkdm,
 860         &core_l4_2420_clkdm,
 861         &dss_2420_clkdm,
 862 #endif
 863
 864 #ifdef CONFIG_ARCH_OMAP2430
 865         &mpu_2430_clkdm,
 866         &mdm_clkdm,
 867         &dsp_2430_clkdm,
 868         &gfx_2430_clkdm,
 869         &core_l3_2430_clkdm,
 870         &core_l4_2430_clkdm,
 871         &dss_2430_clkdm,
 872 #endif
 873
 874 #ifdef CONFIG_ARCH_OMAP3
 875         &mpu_3xxx_clkdm,
 876         &neon_clkdm,
 877         &iva2_clkdm,
 878         &gfx_3430es1_clkdm,
 879         &sgx_clkdm,
 880         &d2d_clkdm,
 881         &core_l3_3xxx_clkdm,
 882         &core_l4_3xxx_clkdm,
 883         &dss_3xxx_clkdm,
 884         &cam_clkdm,
 885         &usbhost_clkdm,
 886         &per_clkdm,
 887         &emu_clkdm,
 888         &dpll1_clkdm,
 889         &dpll2_clkdm,
 890         &dpll3_clkdm,
 891         &dpll4_clkdm,
 892         &dpll5_clkdm,
 893 #endif
 894         NULL,
 895 };
 896
 897 void __init omap2_clockdomains_init(void)
 898 {
 899         clkdm_init(clockdomains_omap2, clkdm_autodeps);
 900 }