arch/arm/mach-omap2/io.c

   1 /*
   2  * linux/arch/arm/mach-omap2/io.c
   3  *
   4  * OMAP2 I/O mapping code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Copyright (C) 2007-2009 Texas Instruments
   8  *
   9  * Author:
  10  *      Juha Yrjola <juha.yrjola@nokia.com>
  11  *      Syed Khasim <x0khasim@ti.com>
  12  *
  13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/tlb.h>
  26 #include <asm/mach/map.h>
  27
  28 #include <linux/omap-dma.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "soc.h"
  32 #include "iomap.h"
  33 #include "voltage.h"
  34 #include "powerdomain.h"
  35 #include "clockdomain.h"
  36 #include "common.h"
  37 #include "clock.h"
  38 #include "clock2xxx.h"
  39 #include "clock3xxx.h"
  40 #include "omap-pm.h"
  41 #include "sdrc.h"
  42 #include "control.h"
  43 #include "serial.h"
  44 #include "sram.h"
  45 #include "cm2xxx.h"
  46 #include "cm3xxx.h"
  47 #include "cm33xx.h"
  48 #include "cm44xx.h"
  49 #include "prm.h"
  50 #include "cm.h"
  51 #include "prcm_mpu44xx.h"
  52 #include "prminst44xx.h"
  53 #include "prm2xxx.h"
  54 #include "prm3xxx.h"
  55 #include "prm33xx.h"
  56 #include "prm44xx.h"
  57 #include "opp2xxx.h"
  58
  59 /*
  60  * omap_clk_soc_init: points to a function that does the SoC-specific
  61  * clock initializations
  62  */
  63 static int (*omap_clk_soc_init)(void);
  64
  65 /*
  66  * The machine specific code may provide the extra mapping besides the
  67  * default mapping provided here.
  68  */
  69
  70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  71 static struct map_desc omap24xx_io_desc[] __initdata = {
  72         {
  73                 .virtual        = L3_24XX_VIRT,
  74                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  75                 .length         = L3_24XX_SIZE,
  76                 .type           = MT_DEVICE
  77         },
  78         {
  79                 .virtual        = L4_24XX_VIRT,
  80                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  81                 .length         = L4_24XX_SIZE,
  82                 .type           = MT_DEVICE
  83         },
  84 };
  85
  86 #ifdef CONFIG_SOC_OMAP2420
  87 static struct map_desc omap242x_io_desc[] __initdata = {
  88         {
  89                 .virtual        = DSP_MEM_2420_VIRT,
  90                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  91                 .length         = DSP_MEM_2420_SIZE,
  92                 .type           = MT_DEVICE
  93         },
  94         {
  95                 .virtual        = DSP_IPI_2420_VIRT,
  96                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  97                 .length         = DSP_IPI_2420_SIZE,
  98                 .type           = MT_DEVICE
  99         },
 100         {
 101                 .virtual        = DSP_MMU_2420_VIRT,
 102                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
 103                 .length         = DSP_MMU_2420_SIZE,
 104                 .type           = MT_DEVICE
 105         },
 106 };
 107
 108 #endif
 109
 110 #ifdef CONFIG_SOC_OMAP2430
 111 static struct map_desc omap243x_io_desc[] __initdata = {
 112         {
 113                 .virtual        = L4_WK_243X_VIRT,
 114                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
 115                 .length         = L4_WK_243X_SIZE,
 116                 .type           = MT_DEVICE
 117         },
 118         {
 119                 .virtual        = OMAP243X_GPMC_VIRT,
 120                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 121                 .length         = OMAP243X_GPMC_SIZE,
 122                 .type           = MT_DEVICE
 123         },
 124         {
 125                 .virtual        = OMAP243X_SDRC_VIRT,
 126                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 127                 .length         = OMAP243X_SDRC_SIZE,
 128                 .type           = MT_DEVICE
 129         },
 130         {
 131                 .virtual        = OMAP243X_SMS_VIRT,
 132                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 133                 .length         = OMAP243X_SMS_SIZE,
 134                 .type           = MT_DEVICE
 135         },
 136 };
 137 #endif
 138 #endif
 139
 140 #ifdef  CONFIG_ARCH_OMAP3
 141 static struct map_desc omap34xx_io_desc[] __initdata = {
 142         {
 143                 .virtual        = L3_34XX_VIRT,
 144                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 145                 .length         = L3_34XX_SIZE,
 146                 .type           = MT_DEVICE
 147         },
 148         {
 149                 .virtual        = L4_34XX_VIRT,
 150                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 151                 .length         = L4_34XX_SIZE,
 152                 .type           = MT_DEVICE
 153         },
 154         {
 155                 .virtual        = OMAP34XX_GPMC_VIRT,
 156                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 157                 .length         = OMAP34XX_GPMC_SIZE,
 158                 .type           = MT_DEVICE
 159         },
 160         {
 161                 .virtual        = OMAP343X_SMS_VIRT,
 162                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 163                 .length         = OMAP343X_SMS_SIZE,
 164                 .type           = MT_DEVICE
 165         },
 166         {
 167                 .virtual        = OMAP343X_SDRC_VIRT,
 168                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 169                 .length         = OMAP343X_SDRC_SIZE,
 170                 .type           = MT_DEVICE
 171         },
 172         {
 173                 .virtual        = L4_PER_34XX_VIRT,
 174                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 175                 .length         = L4_PER_34XX_SIZE,
 176                 .type           = MT_DEVICE
 177         },
 178         {
 179                 .virtual        = L4_EMU_34XX_VIRT,
 180                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 181                 .length         = L4_EMU_34XX_SIZE,
 182                 .type           = MT_DEVICE
 183         },
 184 };
 185 #endif
 186
 187 #ifdef CONFIG_SOC_TI81XX
 188 static struct map_desc omapti81xx_io_desc[] __initdata = {
 189         {
 190                 .virtual        = L4_34XX_VIRT,
 191                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 192                 .length         = L4_34XX_SIZE,
 193                 .type           = MT_DEVICE
 194         }
 195 };
 196 #endif
 197
 198 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 199 static struct map_desc omapam33xx_io_desc[] __initdata = {
 200         {
 201                 .virtual        = L4_34XX_VIRT,
 202                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 203                 .length         = L4_34XX_SIZE,
 204                 .type           = MT_DEVICE
 205         },
 206         {
 207                 .virtual        = L4_WK_AM33XX_VIRT,
 208                 .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
 209                 .length         = L4_WK_AM33XX_SIZE,
 210                 .type           = MT_DEVICE
 211         }
 212 };
 213 #endif
 214
 215 #ifdef  CONFIG_ARCH_OMAP4
 216 static struct map_desc omap44xx_io_desc[] __initdata = {
 217         {
 218                 .virtual        = L3_44XX_VIRT,
 219                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 220                 .length         = L3_44XX_SIZE,
 221                 .type           = MT_DEVICE,
 222         },
 223         {
 224                 .virtual        = L4_44XX_VIRT,
 225                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 226                 .length         = L4_44XX_SIZE,
 227                 .type           = MT_DEVICE,
 228         },
 229         {
 230                 .virtual        = L4_PER_44XX_VIRT,
 231                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 232                 .length         = L4_PER_44XX_SIZE,
 233                 .type           = MT_DEVICE,
 234         },
 235 };
 236 #endif
 237
 238 #ifdef CONFIG_SOC_OMAP5
 239 static struct map_desc omap54xx_io_desc[] __initdata = {
 240         {
 241                 .virtual        = L3_54XX_VIRT,
 242                 .pfn            = __phys_to_pfn(L3_54XX_PHYS),
 243                 .length         = L3_54XX_SIZE,
 244                 .type           = MT_DEVICE,
 245         },
 246         {
 247                 .virtual        = L4_54XX_VIRT,
 248                 .pfn            = __phys_to_pfn(L4_54XX_PHYS),
 249                 .length         = L4_54XX_SIZE,
 250                 .type           = MT_DEVICE,
 251         },
 252         {
 253                 .virtual        = L4_WK_54XX_VIRT,
 254                 .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
 255                 .length         = L4_WK_54XX_SIZE,
 256                 .type           = MT_DEVICE,
 257         },
 258         {
 259                 .virtual        = L4_PER_54XX_VIRT,
 260                 .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
 261                 .length         = L4_PER_54XX_SIZE,
 262                 .type           = MT_DEVICE,
 263         },
 264 };
 265 #endif
 266
 267 #ifdef CONFIG_SOC_DRA7XX
 268 static struct map_desc dra7xx_io_desc[] __initdata = {
 269         {
 270                 .virtual        = L4_CFG_MPU_DRA7XX_VIRT,
 271                 .pfn            = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
 272                 .length         = L4_CFG_MPU_DRA7XX_SIZE,
 273                 .type           = MT_DEVICE,
 274         },
 275         {
 276                 .virtual        = L3_MAIN_SN_DRA7XX_VIRT,
 277                 .pfn            = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
 278                 .length         = L3_MAIN_SN_DRA7XX_SIZE,
 279                 .type           = MT_DEVICE,
 280         },
 281         {
 282                 .virtual        = L4_PER1_DRA7XX_VIRT,
 283                 .pfn            = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
 284                 .length         = L4_PER1_DRA7XX_SIZE,
 285                 .type           = MT_DEVICE,
 286         },
 287         {
 288                 .virtual        = L4_PER2_DRA7XX_VIRT,
 289                 .pfn            = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
 290                 .length         = L4_PER2_DRA7XX_SIZE,
 291                 .type           = MT_DEVICE,
 292         },
 293         {
 294                 .virtual        = L4_PER3_DRA7XX_VIRT,
 295                 .pfn            = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
 296                 .length         = L4_PER3_DRA7XX_SIZE,
 297                 .type           = MT_DEVICE,
 298         },
 299         {
 300                 .virtual        = L4_CFG_DRA7XX_VIRT,
 301                 .pfn            = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
 302                 .length         = L4_CFG_DRA7XX_SIZE,
 303                 .type           = MT_DEVICE,
 304         },
 305         {
 306                 .virtual        = L4_WKUP_DRA7XX_VIRT,
 307                 .pfn            = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
 308                 .length         = L4_WKUP_DRA7XX_SIZE,
 309                 .type           = MT_DEVICE,
 310         },
 311 };
 312 #endif
 313
 314 #ifdef CONFIG_SOC_OMAP2420
 315 void __init omap242x_map_io(void)
 316 {
 317         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 318         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 319 }
 320 #endif
 321
 322 #ifdef CONFIG_SOC_OMAP2430
 323 void __init omap243x_map_io(void)
 324 {
 325         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 326         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 327 }
 328 #endif
 329
 330 #ifdef CONFIG_ARCH_OMAP3
 331 void __init omap3_map_io(void)
 332 {
 333         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 334 }
 335 #endif
 336
 337 #ifdef CONFIG_SOC_TI81XX
 338 void __init ti81xx_map_io(void)
 339 {
 340         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 341 }
 342 #endif
 343
 344 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 345 void __init am33xx_map_io(void)
 346 {
 347         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 348 }
 349 #endif
 350
 351 #ifdef CONFIG_ARCH_OMAP4
 352 void __init omap4_map_io(void)
 353 {
 354         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 355 }
 356 #endif
 357
 358 #ifdef CONFIG_SOC_OMAP5
 359 void __init omap5_map_io(void)
 360 {
 361         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 362 }
 363 #endif
 364
 365 #ifdef CONFIG_SOC_DRA7XX
 366 void __init dra7xx_map_io(void)
 367 {
 368         iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
 369 }
 370 #endif
 371 /*
 372  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 373  *
 374  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 375  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 376  * registers to the values currently defined by the kernel.  Currently
 377  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 378  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 379  * or passes along the return value of clk_set_rate().
 380  */
 381 static int __init _omap2_init_reprogram_sdrc(void)
 382 {
 383         struct clk *dpll3_m2_ck;
 384         int v = -EINVAL;
 385         long rate;
 386
 387         if (!cpu_is_omap34xx())
 388                 return 0;
 389
 390         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 391         if (IS_ERR(dpll3_m2_ck))
 392                 return -EINVAL;
 393
 394         rate = clk_get_rate(dpll3_m2_ck);
 395         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 396         v = clk_set_rate(dpll3_m2_ck, rate);
 397         if (v)
 398                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 399
 400         clk_put(dpll3_m2_ck);
 401
 402         return v;
 403 }
 404
 405 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 406 {
 407         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 408 }
 409
 410 static void __init omap_hwmod_init_postsetup(void)
 411 {
 412         u8 postsetup_state;
 413
 414         /* Set the default postsetup state for all hwmods */
 415 #ifdef CONFIG_PM
 416         postsetup_state = _HWMOD_STATE_IDLE;
 417 #else
 418         postsetup_state = _HWMOD_STATE_ENABLED;
 419 #endif
 420         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 421
 422         omap_pm_if_early_init();
 423 }
 424
 425 static void __init __maybe_unused omap_common_late_init(void)
 426 {
 427         omap_mux_late_init();
 428         omap2_common_pm_late_init();
 429         omap_soc_device_init();
 430 }
 431
 432 #ifdef CONFIG_SOC_OMAP2420
 433 void __init omap2420_init_early(void)
 434 {
 435         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 436         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 437                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
 438         omap2_control_base_init();
 439         omap2xxx_check_revision();
 440         omap2_prcm_base_init();
 441         omap2xxx_voltagedomains_init();
 442         omap242x_powerdomains_init();
 443         omap242x_clockdomains_init();
 444         omap2420_hwmod_init();
 445         omap_hwmod_init_postsetup();
 446         omap_clk_soc_init = omap2420_dt_clk_init;
 447         rate_table = omap2420_rate_table;
 448 }
 449
 450 void __init omap2420_init_late(void)
 451 {
 452         omap_common_late_init();
 453         omap2_pm_init();
 454         omap2_clk_enable_autoidle_all();
 455 }
 456 #endif
 457
 458 #ifdef CONFIG_SOC_OMAP2430
 459 void __init omap2430_init_early(void)
 460 {
 461         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 462         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 463                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
 464         omap2_control_base_init();
 465         omap2xxx_check_revision();
 466         omap2_prcm_base_init();
 467         omap2xxx_voltagedomains_init();
 468         omap243x_powerdomains_init();
 469         omap243x_clockdomains_init();
 470         omap2430_hwmod_init();
 471         omap_hwmod_init_postsetup();
 472         omap_clk_soc_init = omap2430_dt_clk_init;
 473         rate_table = omap2430_rate_table;
 474 }
 475
 476 void __init omap2430_init_late(void)
 477 {
 478         omap_common_late_init();
 479         omap2_pm_init();
 480         omap2_clk_enable_autoidle_all();
 481 }
 482 #endif
 483
 484 /*
 485  * Currently only board-omap3beagle.c should call this because of the
 486  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 487  */
 488 #ifdef CONFIG_ARCH_OMAP3
 489 void __init omap3_init_early(void)
 490 {
 491         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 492         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 493                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
 494         /* XXX: remove these once OMAP3 is DT only */
 495         if (!of_have_populated_dt()) {
 496                 omap2_set_globals_control(
 497                         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
 498                 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
 499                 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 500                                      NULL);
 501         }
 502         omap2_control_base_init();
 503         omap3xxx_check_revision();
 504         omap3xxx_check_features();
 505         omap2_prcm_base_init();
 506         /* XXX: remove these once OMAP3 is DT only */
 507         if (!of_have_populated_dt()) {
 508                 omap3xxx_prm_init(NULL);
 509                 omap3xxx_cm_init(NULL);
 510         }
 511         omap3xxx_voltagedomains_init();
 512         omap3xxx_powerdomains_init();
 513         omap3xxx_clockdomains_init();
 514         omap3xxx_hwmod_init();
 515         omap_hwmod_init_postsetup();
 516         if (!of_have_populated_dt()) {
 517                 omap3_control_legacy_iomap_init();
 518                 if (soc_is_am35xx())
 519                         omap_clk_soc_init = am35xx_clk_legacy_init;
 520                 else if (cpu_is_omap3630())
 521                         omap_clk_soc_init = omap36xx_clk_legacy_init;
 522                 else if (omap_rev() == OMAP3430_REV_ES1_0)
 523                         omap_clk_soc_init = omap3430es1_clk_legacy_init;
 524                 else
 525                         omap_clk_soc_init = omap3430_clk_legacy_init;
 526         }
 527 }
 528
 529 void __init omap3430_init_early(void)
 530 {
 531         omap3_init_early();
 532         if (of_have_populated_dt())
 533                 omap_clk_soc_init = omap3430_dt_clk_init;
 534 }
 535
 536 void __init omap35xx_init_early(void)
 537 {
 538         omap3_init_early();
 539         if (of_have_populated_dt())
 540                 omap_clk_soc_init = omap3430_dt_clk_init;
 541 }
 542
 543 void __init omap3630_init_early(void)
 544 {
 545         omap3_init_early();
 546         if (of_have_populated_dt())
 547                 omap_clk_soc_init = omap3630_dt_clk_init;
 548 }
 549
 550 void __init am35xx_init_early(void)
 551 {
 552         omap3_init_early();
 553         if (of_have_populated_dt())
 554                 omap_clk_soc_init = am35xx_dt_clk_init;
 555 }
 556
 557 void __init omap3_init_late(void)
 558 {
 559         omap_common_late_init();
 560         omap3_pm_init();
 561         omap2_clk_enable_autoidle_all();
 562 }
 563
 564 void __init omap3430_init_late(void)
 565 {
 566         omap_common_late_init();
 567         omap3_pm_init();
 568         omap2_clk_enable_autoidle_all();
 569 }
 570
 571 void __init omap35xx_init_late(void)
 572 {
 573         omap_common_late_init();
 574         omap3_pm_init();
 575         omap2_clk_enable_autoidle_all();
 576 }
 577
 578 void __init omap3630_init_late(void)
 579 {
 580         omap_common_late_init();
 581         omap3_pm_init();
 582         omap2_clk_enable_autoidle_all();
 583 }
 584
 585 void __init am35xx_init_late(void)
 586 {
 587         omap_common_late_init();
 588         omap3_pm_init();
 589         omap2_clk_enable_autoidle_all();
 590 }
 591
 592 void __init ti81xx_init_late(void)
 593 {
 594         omap_common_late_init();
 595         omap2_clk_enable_autoidle_all();
 596 }
 597 #endif
 598
 599 #ifdef CONFIG_SOC_TI81XX
 600 void __init ti814x_init_early(void)
 601 {
 602         omap2_set_globals_tap(TI814X_CLASS,
 603                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 604         omap2_control_base_init();
 605         omap3xxx_check_revision();
 606         ti81xx_check_features();
 607         omap2_prcm_base_init();
 608         omap3xxx_voltagedomains_init();
 609         omap3xxx_powerdomains_init();
 610         ti814x_clockdomains_init();
 611         dm814x_hwmod_init();
 612         omap_hwmod_init_postsetup();
 613         if (of_have_populated_dt())
 614                 omap_clk_soc_init = dm814x_dt_clk_init;
 615 }
 616
 617 void __init ti816x_init_early(void)
 618 {
 619         omap2_set_globals_tap(TI816X_CLASS,
 620                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 621         omap2_control_base_init();
 622         omap3xxx_check_revision();
 623         ti81xx_check_features();
 624         omap2_prcm_base_init();
 625         omap3xxx_voltagedomains_init();
 626         omap3xxx_powerdomains_init();
 627         ti816x_clockdomains_init();
 628         dm816x_hwmod_init();
 629         omap_hwmod_init_postsetup();
 630         if (of_have_populated_dt())
 631                 omap_clk_soc_init = dm816x_dt_clk_init;
 632 }
 633 #endif
 634
 635 #ifdef CONFIG_SOC_AM33XX
 636 void __init am33xx_init_early(void)
 637 {
 638         omap2_set_globals_tap(AM335X_CLASS,
 639                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 640         omap2_control_base_init();
 641         omap3xxx_check_revision();
 642         am33xx_check_features();
 643         omap2_prcm_base_init();
 644         am33xx_powerdomains_init();
 645         am33xx_clockdomains_init();
 646         am33xx_hwmod_init();
 647         omap_hwmod_init_postsetup();
 648         omap_clk_soc_init = am33xx_dt_clk_init;
 649 }
 650
 651 void __init am33xx_init_late(void)
 652 {
 653         omap_common_late_init();
 654 }
 655 #endif
 656
 657 #ifdef CONFIG_SOC_AM43XX
 658 void __init am43xx_init_early(void)
 659 {
 660         omap2_set_globals_tap(AM335X_CLASS,
 661                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 662         omap2_control_base_init();
 663         omap3xxx_check_revision();
 664         am33xx_check_features();
 665         omap2_prcm_base_init();
 666         am43xx_powerdomains_init();
 667         am43xx_clockdomains_init();
 668         am43xx_hwmod_init();
 669         omap_hwmod_init_postsetup();
 670         omap_l2_cache_init();
 671         omap_clk_soc_init = am43xx_dt_clk_init;
 672 }
 673
 674 void __init am43xx_init_late(void)
 675 {
 676         omap_common_late_init();
 677 }
 678 #endif
 679
 680 #ifdef CONFIG_ARCH_OMAP4
 681 void __init omap4430_init_early(void)
 682 {
 683         omap2_set_globals_tap(OMAP443X_CLASS,
 684                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 685         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
 686         omap2_control_base_init();
 687         omap4xxx_check_revision();
 688         omap4xxx_check_features();
 689         omap2_prcm_base_init();
 690         omap4_pm_init_early();
 691         omap44xx_voltagedomains_init();
 692         omap44xx_powerdomains_init();
 693         omap44xx_clockdomains_init();
 694         omap44xx_hwmod_init();
 695         omap_hwmod_init_postsetup();
 696         omap_l2_cache_init();
 697         omap_clk_soc_init = omap4xxx_dt_clk_init;
 698 }
 699
 700 void __init omap4430_init_late(void)
 701 {
 702         omap_common_late_init();
 703         omap4_pm_init();
 704         omap2_clk_enable_autoidle_all();
 705 }
 706 #endif
 707
 708 #ifdef CONFIG_SOC_OMAP5
 709 void __init omap5_init_early(void)
 710 {
 711         omap2_set_globals_tap(OMAP54XX_CLASS,
 712                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 713         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 714         omap2_control_base_init();
 715         omap4_pm_init_early();
 716         omap2_prcm_base_init();
 717         omap5xxx_check_revision();
 718         omap54xx_voltagedomains_init();
 719         omap54xx_powerdomains_init();
 720         omap54xx_clockdomains_init();
 721         omap54xx_hwmod_init();
 722         omap_hwmod_init_postsetup();
 723         omap_clk_soc_init = omap5xxx_dt_clk_init;
 724 }
 725
 726 void __init omap5_init_late(void)
 727 {
 728         omap_common_late_init();
 729         omap4_pm_init();
 730         omap2_clk_enable_autoidle_all();
 731 }
 732 #endif
 733
 734 #ifdef CONFIG_SOC_DRA7XX
 735 void __init dra7xx_init_early(void)
 736 {
 737         omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 738         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 739         omap2_control_base_init();
 740         omap4_pm_init_early();
 741         omap2_prcm_base_init();
 742         dra7xxx_check_revision();
 743         dra7xx_powerdomains_init();
 744         dra7xx_clockdomains_init();
 745         dra7xx_hwmod_init();
 746         omap_hwmod_init_postsetup();
 747         omap_clk_soc_init = dra7xx_dt_clk_init;
 748 }
 749
 750 void __init dra7xx_init_late(void)
 751 {
 752         omap_common_late_init();
 753         omap4_pm_init();
 754         omap2_clk_enable_autoidle_all();
 755 }
 756 #endif
 757
 758
 759 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 760                                       struct omap_sdrc_params *sdrc_cs1)
 761 {
 762         omap_sram_init();
 763
 764         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 765                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 766                 _omap2_init_reprogram_sdrc();
 767         }
 768 }
 769
 770 int __init omap_clk_init(void)
 771 {
 772         int ret = 0;
 773
 774         if (!omap_clk_soc_init)
 775                 return 0;
 776
 777         ti_clk_init_features();
 778
 779         omap2_clk_setup_ll_ops();
 780
 781         if (of_have_populated_dt()) {
 782                 ret = omap_control_init();
 783                 if (ret)
 784                         return ret;
 785
 786                 ret = omap_prcm_init();
 787                 if (ret)
 788                         return ret;
 789
 790                 of_clk_init(NULL);
 791
 792                 ti_dt_clk_init_retry_clks();
 793
 794                 ti_dt_clockdomains_setup();
 795         }
 796
 797         ret = omap_clk_soc_init();
 798
 799         return ret;
 800 }