2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
18 #include <plat/mailbox.h>
19 #include <mach/irqs.h>
21 #define DRV_NAME "omap2-mailbox"
23 #define MAILBOX_REVISION 0x000
24 #define MAILBOX_SYSCONFIG 0x010
25 #define MAILBOX_SYSSTATUS 0x014
26 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
27 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
28 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
29 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
30 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
32 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
33 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
34 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
36 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
37 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
39 /* SYSCONFIG: register bit definition */
40 #define AUTOIDLE (1 << 0)
41 #define SOFTRESET (1 << 1)
42 #define SMARTIDLE (2 << 3)
43 #define OMAP4_SOFTRESET (1 << 0)
44 #define OMAP4_NOIDLE (1 << 2)
45 #define OMAP4_SMARTIDLE (2 << 2)
47 /* SYSSTATUS: register bit definition */
48 #define RESETDONE (1 << 0)
50 #define MBOX_REG_SIZE 0x120
52 #define OMAP4_MBOX_REG_SIZE 0x130
54 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
55 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
57 static void __iomem *mbox_base;
59 struct omap_mbox2_fifo {
61 unsigned long fifo_stat;
62 unsigned long msg_stat;
65 struct omap_mbox2_priv {
66 struct omap_mbox2_fifo tx_fifo;
67 struct omap_mbox2_fifo rx_fifo;
68 unsigned long irqenable;
69 unsigned long irqstatus;
72 u32 ctx[OMAP4_MBOX_NR_REGS];
73 unsigned long irqdisable;
76 static struct clk *mbox_ick_handle;
78 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
79 omap_mbox_type_t irq);
81 static inline unsigned int mbox_read_reg(size_t ofs)
83 return __raw_readl(mbox_base + ofs);
86 static inline void mbox_write_reg(u32 val, size_t ofs)
88 __raw_writel(val, mbox_base + ofs);
91 /* Mailbox H/W preparations */
92 static int omap2_mbox_startup(struct omap_mbox *mbox)
95 unsigned long timeout;
97 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
98 if (IS_ERR(mbox_ick_handle)) {
99 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
100 PTR_ERR(mbox_ick_handle));
101 return PTR_ERR(mbox_ick_handle);
103 clk_enable(mbox_ick_handle);
105 if (cpu_is_omap44xx()) {
106 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
107 timeout = jiffies + msecs_to_jiffies(20);
109 l = mbox_read_reg(MAILBOX_SYSCONFIG);
110 if (!(l & OMAP4_SOFTRESET))
112 } while (!time_after(jiffies, timeout));
114 if (l & OMAP4_SOFTRESET) {
115 pr_err("Can't take mailbox out of reset\n");
119 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
120 timeout = jiffies + msecs_to_jiffies(20);
122 l = mbox_read_reg(MAILBOX_SYSSTATUS);
125 } while (!time_after(jiffies, timeout));
127 if (!(l & RESETDONE)) {
128 pr_err("Can't take mailbox out of reset\n");
133 l = mbox_read_reg(MAILBOX_REVISION);
134 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
136 if (cpu_is_omap44xx())
139 l = SMARTIDLE | AUTOIDLE;
140 mbox_write_reg(l, MAILBOX_SYSCONFIG);
142 omap2_mbox_enable_irq(mbox, IRQ_RX);
147 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
149 clk_disable(mbox_ick_handle);
150 clk_put(mbox_ick_handle);
151 mbox_ick_handle = NULL;
154 /* Mailbox FIFO handle functions */
155 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
157 struct omap_mbox2_fifo *fifo =
158 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
159 return (mbox_msg_t) mbox_read_reg(fifo->msg);
162 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
164 struct omap_mbox2_fifo *fifo =
165 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
166 mbox_write_reg(msg, fifo->msg);
169 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
171 struct omap_mbox2_fifo *fifo =
172 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
173 return (mbox_read_reg(fifo->msg_stat) == 0);
176 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
178 struct omap_mbox2_fifo *fifo =
179 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
180 return mbox_read_reg(fifo->fifo_stat);
183 /* Mailbox IRQ handle functions */
184 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
185 omap_mbox_type_t irq)
187 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
188 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
190 l = mbox_read_reg(p->irqenable);
192 mbox_write_reg(l, p->irqenable);
195 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
196 omap_mbox_type_t irq)
198 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
199 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
200 l = mbox_read_reg(p->irqdisable);
202 mbox_write_reg(l, p->irqdisable);
205 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
206 omap_mbox_type_t irq)
208 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
209 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
211 mbox_write_reg(bit, p->irqstatus);
213 /* Flush posted write for irq status to avoid spurious interrupts */
214 mbox_read_reg(p->irqstatus);
217 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
218 omap_mbox_type_t irq)
220 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
221 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
222 u32 enable = mbox_read_reg(p->irqenable);
223 u32 status = mbox_read_reg(p->irqstatus);
225 return (int)(enable & status & bit);
228 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
231 struct omap_mbox2_priv *p = mbox->priv;
233 if (cpu_is_omap44xx())
234 nr_regs = OMAP4_MBOX_NR_REGS;
236 nr_regs = MBOX_NR_REGS;
237 for (i = 0; i < nr_regs; i++) {
238 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
240 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
245 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
248 struct omap_mbox2_priv *p = mbox->priv;
250 if (cpu_is_omap44xx())
251 nr_regs = OMAP4_MBOX_NR_REGS;
253 nr_regs = MBOX_NR_REGS;
254 for (i = 0; i < nr_regs; i++) {
255 mbox_write_reg(p->ctx[i], i * sizeof(u32));
257 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
262 static struct omap_mbox_ops omap2_mbox_ops = {
263 .type = OMAP_MBOX_TYPE2,
264 .startup = omap2_mbox_startup,
265 .shutdown = omap2_mbox_shutdown,
266 .fifo_read = omap2_mbox_fifo_read,
267 .fifo_write = omap2_mbox_fifo_write,
268 .fifo_empty = omap2_mbox_fifo_empty,
269 .fifo_full = omap2_mbox_fifo_full,
270 .enable_irq = omap2_mbox_enable_irq,
271 .disable_irq = omap2_mbox_disable_irq,
272 .ack_irq = omap2_mbox_ack_irq,
273 .is_irq = omap2_mbox_is_irq,
274 .save_ctx = omap2_mbox_save_ctx,
275 .restore_ctx = omap2_mbox_restore_ctx,
279 * MAILBOX 0: ARM -> DSP,
280 * MAILBOX 1: ARM <- DSP.
281 * MAILBOX 2: ARM -> IVA,
282 * MAILBOX 3: ARM <- IVA.
285 /* FIXME: the following structs should be filled automatically by the user id */
287 #if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
289 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
291 .msg = MAILBOX_MESSAGE(0),
292 .fifo_stat = MAILBOX_FIFOSTATUS(0),
295 .msg = MAILBOX_MESSAGE(1),
296 .msg_stat = MAILBOX_MSGSTATUS(1),
298 .irqenable = MAILBOX_IRQENABLE(0),
299 .irqstatus = MAILBOX_IRQSTATUS(0),
300 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
301 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
302 .irqdisable = MAILBOX_IRQENABLE(0),
305 struct omap_mbox mbox_dsp_info = {
307 .ops = &omap2_mbox_ops,
308 .priv = &omap2_mbox_dsp_priv,
312 #if defined(CONFIG_ARCH_OMAP3430)
313 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
316 #if defined(CONFIG_ARCH_OMAP2420)
318 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
320 .msg = MAILBOX_MESSAGE(2),
321 .fifo_stat = MAILBOX_FIFOSTATUS(2),
324 .msg = MAILBOX_MESSAGE(3),
325 .msg_stat = MAILBOX_MSGSTATUS(3),
327 .irqenable = MAILBOX_IRQENABLE(3),
328 .irqstatus = MAILBOX_IRQSTATUS(3),
329 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
330 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
331 .irqdisable = MAILBOX_IRQENABLE(3),
334 static struct omap_mbox mbox_iva_info = {
336 .ops = &omap2_mbox_ops,
337 .priv = &omap2_mbox_iva_priv,
340 struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
343 #if defined(CONFIG_ARCH_OMAP4)
345 static struct omap_mbox2_priv omap2_mbox_1_priv = {
347 .msg = MAILBOX_MESSAGE(0),
348 .fifo_stat = MAILBOX_FIFOSTATUS(0),
351 .msg = MAILBOX_MESSAGE(1),
352 .msg_stat = MAILBOX_MSGSTATUS(1),
354 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
355 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
356 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
357 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
358 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
361 struct omap_mbox mbox_1_info = {
363 .ops = &omap2_mbox_ops,
364 .priv = &omap2_mbox_1_priv,
367 static struct omap_mbox2_priv omap2_mbox_2_priv = {
369 .msg = MAILBOX_MESSAGE(3),
370 .fifo_stat = MAILBOX_FIFOSTATUS(3),
373 .msg = MAILBOX_MESSAGE(2),
374 .msg_stat = MAILBOX_MSGSTATUS(2),
376 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
377 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
378 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
379 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
380 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
383 struct omap_mbox mbox_2_info = {
385 .ops = &omap2_mbox_ops,
386 .priv = &omap2_mbox_2_priv,
389 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
392 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
394 struct resource *mem;
396 struct omap_mbox **list;
400 #if defined(CONFIG_ARCH_OMAP3430)
401 else if (cpu_is_omap3430()) {
404 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
407 #if defined(CONFIG_ARCH_OMAP2420)
408 else if (cpu_is_omap2420()) {
411 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
412 list[1]->irq = platform_get_irq_byname(pdev, "iva");
415 #if defined(CONFIG_ARCH_OMAP4)
416 else if (cpu_is_omap44xx()) {
419 list[0]->irq = list[1]->irq =
420 platform_get_irq_byname(pdev, "mbox");
424 pr_err("%s: platform not supported\n", __func__);
428 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429 mbox_base = ioremap(mem->start, resource_size(mem));
433 ret = omap_mbox_register(&pdev->dev, list);
443 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
445 omap_mbox_unregister();
450 static struct platform_driver omap2_mbox_driver = {
451 .probe = omap2_mbox_probe,
452 .remove = __devexit_p(omap2_mbox_remove),
458 static int __init omap2_mbox_init(void)
460 return platform_driver_register(&omap2_mbox_driver);
463 static void __exit omap2_mbox_exit(void)
465 platform_driver_unregister(&omap2_mbox_driver);
468 module_init(omap2_mbox_init);
469 module_exit(omap2_mbox_exit);
471 MODULE_LICENSE("GPL v2");
472 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
473 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
474 MODULE_AUTHOR("Paul Mundt");
475 MODULE_ALIAS("platform:"DRV_NAME);