arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21
  22 #include <plat-omap/dma-omap.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25 #include <linux/platform_data/asoc-ti-mcbsp.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/iommu-omap.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "am35xx.h"
  31
  32 #include "soc.h"
  33 #include "omap_hwmod.h"
  34 #include "omap_hwmod_common_data.h"
  35 #include "prm-regbits-34xx.h"
  36 #include "cm-regbits-34xx.h"
  37
  38 #include "dma.h"
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42 #include "serial.h"
  43
  44 /*
  45  * OMAP3xxx hardware module integration data
  46  *
  47  * All of the data in this section should be autogeneratable from the
  48  * TI hardware database or other technical documentation.  Data that
  49  * is driver-specific or driver-kernel integration-specific belongs
  50  * elsewhere.
  51  */
  52
  53 /*
  54  * IP blocks
  55  */
  56
  57 /* L3 */
  58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  59         { .irq = 9 + OMAP_INTC_START, },
  60         { .irq = 10 + OMAP_INTC_START, },
  61         { .irq = -1 },
  62 };
  63
  64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  65         .name           = "l3_main",
  66         .class          = &l3_hwmod_class,
  67         .mpu_irqs       = omap3xxx_l3_main_irqs,
  68         .flags          = HWMOD_NO_IDLEST,
  69 };
  70
  71 /* L4 CORE */
  72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  73         .name           = "l4_core",
  74         .class          = &l4_hwmod_class,
  75         .flags          = HWMOD_NO_IDLEST,
  76 };
  77
  78 /* L4 PER */
  79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  80         .name           = "l4_per",
  81         .class          = &l4_hwmod_class,
  82         .flags          = HWMOD_NO_IDLEST,
  83 };
  84
  85 /* L4 WKUP */
  86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  87         .name           = "l4_wkup",
  88         .class          = &l4_hwmod_class,
  89         .flags          = HWMOD_NO_IDLEST,
  90 };
  91
  92 /* L4 SEC */
  93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  94         .name           = "l4_sec",
  95         .class          = &l4_hwmod_class,
  96         .flags          = HWMOD_NO_IDLEST,
  97 };
  98
  99 /* MPU */
 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 101         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 102         { .irq = -1 }
 103 };
 104
 105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 106         .name           = "mpu",
 107         .mpu_irqs       = omap3xxx_mpu_irqs,
 108         .class          = &mpu_hwmod_class,
 109         .main_clk       = "arm_fck",
 110 };
 111
 112 /* IVA2 (IVA2) */
 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 114         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 115         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 116         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 117 };
 118
 119 static struct omap_hwmod omap3xxx_iva_hwmod = {
 120         .name           = "iva",
 121         .class          = &iva_hwmod_class,
 122         .clkdm_name     = "iva2_clkdm",
 123         .rst_lines      = omap3xxx_iva_resets,
 124         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 125         .main_clk       = "iva2_ck",
 126         .prcm = {
 127                 .omap2 = {
 128                         .module_offs = OMAP3430_IVA2_MOD,
 129                         .prcm_reg_id = 1,
 130                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 131                         .idlest_reg_id = 1,
 132                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 133                 }
 134         },
 135 };
 136
 137 /*
 138  * 'debugss' class
 139  * debug and emulation sub system
 140  */
 141
 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 143         .name   = "debugss",
 144 };
 145
 146 /* debugss */
 147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 148         .name           = "debugss",
 149         .class          = &omap3xxx_debugss_hwmod_class,
 150         .clkdm_name     = "emu_clkdm",
 151         .main_clk       = "emu_src_ck",
 152         .flags          = HWMOD_NO_IDLEST,
 153 };
 154
 155 /* timer class */
 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 157         .rev_offs       = 0x0000,
 158         .sysc_offs      = 0x0010,
 159         .syss_offs      = 0x0014,
 160         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 162                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 163                            SYSS_HAS_RESET_STATUS),
 164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 165         .clockact       = CLOCKACT_TEST_ICLK,
 166         .sysc_fields    = &omap_hwmod_sysc_type1,
 167 };
 168
 169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 170         .name = "timer",
 171         .sysc = &omap3xxx_timer_sysc,
 172 };
 173
 174 /* secure timers dev attribute */
 175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 176         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 177 };
 178
 179 /* always-on timers dev attribute */
 180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 181         .timer_capability       = OMAP_TIMER_ALWON,
 182 };
 183
 184 /* pwm timers dev attribute */
 185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 186         .timer_capability       = OMAP_TIMER_HAS_PWM,
 187 };
 188
 189 /* timers with DSP interrupt dev attribute */
 190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 191         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 192 };
 193
 194 /* pwm timers with DSP interrupt dev attribute */
 195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 196         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 197 };
 198
 199 /* timer1 */
 200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 201         .name           = "timer1",
 202         .mpu_irqs       = omap2_timer1_mpu_irqs,
 203         .main_clk       = "gpt1_fck",
 204         .prcm           = {
 205                 .omap2 = {
 206                         .prcm_reg_id = 1,
 207                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 208                         .module_offs = WKUP_MOD,
 209                         .idlest_reg_id = 1,
 210                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 211                 },
 212         },
 213         .dev_attr       = &capability_alwon_dev_attr,
 214         .class          = &omap3xxx_timer_hwmod_class,
 215         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 216 };
 217
 218 /* timer2 */
 219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 220         .name           = "timer2",
 221         .mpu_irqs       = omap2_timer2_mpu_irqs,
 222         .main_clk       = "gpt2_fck",
 223         .prcm           = {
 224                 .omap2 = {
 225                         .prcm_reg_id = 1,
 226                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 227                         .module_offs = OMAP3430_PER_MOD,
 228                         .idlest_reg_id = 1,
 229                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 230                 },
 231         },
 232         .class          = &omap3xxx_timer_hwmod_class,
 233         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 234 };
 235
 236 /* timer3 */
 237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 238         .name           = "timer3",
 239         .mpu_irqs       = omap2_timer3_mpu_irqs,
 240         .main_clk       = "gpt3_fck",
 241         .prcm           = {
 242                 .omap2 = {
 243                         .prcm_reg_id = 1,
 244                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 245                         .module_offs = OMAP3430_PER_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 248                 },
 249         },
 250         .class          = &omap3xxx_timer_hwmod_class,
 251         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 252 };
 253
 254 /* timer4 */
 255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 256         .name           = "timer4",
 257         .mpu_irqs       = omap2_timer4_mpu_irqs,
 258         .main_clk       = "gpt4_fck",
 259         .prcm           = {
 260                 .omap2 = {
 261                         .prcm_reg_id = 1,
 262                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 263                         .module_offs = OMAP3430_PER_MOD,
 264                         .idlest_reg_id = 1,
 265                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 266                 },
 267         },
 268         .class          = &omap3xxx_timer_hwmod_class,
 269         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 270 };
 271
 272 /* timer5 */
 273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 274         .name           = "timer5",
 275         .mpu_irqs       = omap2_timer5_mpu_irqs,
 276         .main_clk       = "gpt5_fck",
 277         .prcm           = {
 278                 .omap2 = {
 279                         .prcm_reg_id = 1,
 280                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 281                         .module_offs = OMAP3430_PER_MOD,
 282                         .idlest_reg_id = 1,
 283                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 284                 },
 285         },
 286         .dev_attr       = &capability_dsp_dev_attr,
 287         .class          = &omap3xxx_timer_hwmod_class,
 288         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 289 };
 290
 291 /* timer6 */
 292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 293         .name           = "timer6",
 294         .mpu_irqs       = omap2_timer6_mpu_irqs,
 295         .main_clk       = "gpt6_fck",
 296         .prcm           = {
 297                 .omap2 = {
 298                         .prcm_reg_id = 1,
 299                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 300                         .module_offs = OMAP3430_PER_MOD,
 301                         .idlest_reg_id = 1,
 302                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 303                 },
 304         },
 305         .dev_attr       = &capability_dsp_dev_attr,
 306         .class          = &omap3xxx_timer_hwmod_class,
 307         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 308 };
 309
 310 /* timer7 */
 311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 312         .name           = "timer7",
 313         .mpu_irqs       = omap2_timer7_mpu_irqs,
 314         .main_clk       = "gpt7_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 319                         .module_offs = OMAP3430_PER_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 322                 },
 323         },
 324         .dev_attr       = &capability_dsp_dev_attr,
 325         .class          = &omap3xxx_timer_hwmod_class,
 326         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 327 };
 328
 329 /* timer8 */
 330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 331         .name           = "timer8",
 332         .mpu_irqs       = omap2_timer8_mpu_irqs,
 333         .main_clk       = "gpt8_fck",
 334         .prcm           = {
 335                 .omap2 = {
 336                         .prcm_reg_id = 1,
 337                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 338                         .module_offs = OMAP3430_PER_MOD,
 339                         .idlest_reg_id = 1,
 340                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 341                 },
 342         },
 343         .dev_attr       = &capability_dsp_pwm_dev_attr,
 344         .class          = &omap3xxx_timer_hwmod_class,
 345         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 346 };
 347
 348 /* timer9 */
 349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 350         .name           = "timer9",
 351         .mpu_irqs       = omap2_timer9_mpu_irqs,
 352         .main_clk       = "gpt9_fck",
 353         .prcm           = {
 354                 .omap2 = {
 355                         .prcm_reg_id = 1,
 356                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 357                         .module_offs = OMAP3430_PER_MOD,
 358                         .idlest_reg_id = 1,
 359                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 360                 },
 361         },
 362         .dev_attr       = &capability_pwm_dev_attr,
 363         .class          = &omap3xxx_timer_hwmod_class,
 364         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 365 };
 366
 367 /* timer10 */
 368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 369         .name           = "timer10",
 370         .mpu_irqs       = omap2_timer10_mpu_irqs,
 371         .main_clk       = "gpt10_fck",
 372         .prcm           = {
 373                 .omap2 = {
 374                         .prcm_reg_id = 1,
 375                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 1,
 378                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 379                 },
 380         },
 381         .dev_attr       = &capability_pwm_dev_attr,
 382         .class          = &omap3xxx_timer_hwmod_class,
 383         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 384 };
 385
 386 /* timer11 */
 387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 388         .name           = "timer11",
 389         .mpu_irqs       = omap2_timer11_mpu_irqs,
 390         .main_clk       = "gpt11_fck",
 391         .prcm           = {
 392                 .omap2 = {
 393                         .prcm_reg_id = 1,
 394                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 395                         .module_offs = CORE_MOD,
 396                         .idlest_reg_id = 1,
 397                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 398                 },
 399         },
 400         .dev_attr       = &capability_pwm_dev_attr,
 401         .class          = &omap3xxx_timer_hwmod_class,
 402         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 403 };
 404
 405 /* timer12 */
 406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 407         { .irq = 95 + OMAP_INTC_START, },
 408         { .irq = -1 },
 409 };
 410
 411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 412         .name           = "timer12",
 413         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 414         .main_clk       = "gpt12_fck",
 415         .prcm           = {
 416                 .omap2 = {
 417                         .prcm_reg_id = 1,
 418                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 419                         .module_offs = WKUP_MOD,
 420                         .idlest_reg_id = 1,
 421                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 422                 },
 423         },
 424         .dev_attr       = &capability_secure_dev_attr,
 425         .class          = &omap3xxx_timer_hwmod_class,
 426         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 427 };
 428
 429 /*
 430  * 'wd_timer' class
 431  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 432  * overflow condition
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 440                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 441                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 442                            SYSS_HAS_RESET_STATUS),
 443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 444         .sysc_fields    = &omap_hwmod_sysc_type1,
 445 };
 446
 447 /* I2C common */
 448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 449         .rev_offs       = 0x00,
 450         .sysc_offs      = 0x20,
 451         .syss_offs      = 0x10,
 452         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 453                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 454                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 456         .clockact       = CLOCKACT_TEST_ICLK,
 457         .sysc_fields    = &omap_hwmod_sysc_type1,
 458 };
 459
 460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 461         .name           = "wd_timer",
 462         .sysc           = &omap3xxx_wd_timer_sysc,
 463         .pre_shutdown   = &omap2_wd_timer_disable,
 464         .reset          = &omap2_wd_timer_reset,
 465 };
 466
 467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 468         .name           = "wd_timer2",
 469         .class          = &omap3xxx_wd_timer_hwmod_class,
 470         .main_clk       = "wdt2_fck",
 471         .prcm           = {
 472                 .omap2 = {
 473                         .prcm_reg_id = 1,
 474                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 475                         .module_offs = WKUP_MOD,
 476                         .idlest_reg_id = 1,
 477                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 478                 },
 479         },
 480         /*
 481          * XXX: Use software supervised mode, HW supervised smartidle seems to
 482          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 483          */
 484         .flags          = HWMOD_SWSUP_SIDLE,
 485 };
 486
 487 /* UART1 */
 488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 489         .name           = "uart1",
 490         .mpu_irqs       = omap2_uart1_mpu_irqs,
 491         .sdma_reqs      = omap2_uart1_sdma_reqs,
 492         .main_clk       = "uart1_fck",
 493         .prcm           = {
 494                 .omap2 = {
 495                         .module_offs = CORE_MOD,
 496                         .prcm_reg_id = 1,
 497                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 498                         .idlest_reg_id = 1,
 499                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 500                 },
 501         },
 502         .class          = &omap2_uart_class,
 503 };
 504
 505 /* UART2 */
 506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 507         .name           = "uart2",
 508         .mpu_irqs       = omap2_uart2_mpu_irqs,
 509         .sdma_reqs      = omap2_uart2_sdma_reqs,
 510         .main_clk       = "uart2_fck",
 511         .prcm           = {
 512                 .omap2 = {
 513                         .module_offs = CORE_MOD,
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 516                         .idlest_reg_id = 1,
 517                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 518                 },
 519         },
 520         .class          = &omap2_uart_class,
 521 };
 522
 523 /* UART3 */
 524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 525         .name           = "uart3",
 526         .mpu_irqs       = omap2_uart3_mpu_irqs,
 527         .sdma_reqs      = omap2_uart3_sdma_reqs,
 528         .main_clk       = "uart3_fck",
 529         .prcm           = {
 530                 .omap2 = {
 531                         .module_offs = OMAP3430_PER_MOD,
 532                         .prcm_reg_id = 1,
 533                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 534                         .idlest_reg_id = 1,
 535                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 536                 },
 537         },
 538         .class          = &omap2_uart_class,
 539 };
 540
 541 /* UART4 */
 542 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 543         { .irq = 80 + OMAP_INTC_START, },
 544         { .irq = -1 },
 545 };
 546
 547 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 548         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 549         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 550         { .dma_req = -1 }
 551 };
 552
 553 static struct omap_hwmod omap36xx_uart4_hwmod = {
 554         .name           = "uart4",
 555         .mpu_irqs       = uart4_mpu_irqs,
 556         .sdma_reqs      = uart4_sdma_reqs,
 557         .main_clk       = "uart4_fck",
 558         .prcm           = {
 559                 .omap2 = {
 560                         .module_offs = OMAP3430_PER_MOD,
 561                         .prcm_reg_id = 1,
 562                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 563                         .idlest_reg_id = 1,
 564                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 565                 },
 566         },
 567         .class          = &omap2_uart_class,
 568 };
 569
 570 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 571         { .irq = 84 + OMAP_INTC_START, },
 572         { .irq = -1 },
 573 };
 574
 575 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 576         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 577         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 578         { .dma_req = -1 }
 579 };
 580
 581 /*
 582  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 583  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 584  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 585  * should not be needed.  The functional clock structure of the AM35xx
 586  * UART4 is extremely unclear and opaque; it is unclear what the role
 587  * of uart1/2_fck is for the UART4.  Any clarification from either
 588  * empirical testing or the AM3505/3517 hardware designers would be
 589  * most welcome.
 590  */
 591 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 592         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 593 };
 594
 595 static struct omap_hwmod am35xx_uart4_hwmod = {
 596         .name           = "uart4",
 597         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 598         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 599         .main_clk       = "uart4_fck",
 600         .prcm           = {
 601                 .omap2 = {
 602                         .module_offs = CORE_MOD,
 603                         .prcm_reg_id = 1,
 604                         .module_bit = AM35XX_EN_UART4_SHIFT,
 605                         .idlest_reg_id = 1,
 606                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 607                 },
 608         },
 609         .opt_clks       = am35xx_uart4_opt_clks,
 610         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 611         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 612         .class          = &omap2_uart_class,
 613 };
 614
 615 static struct omap_hwmod_class i2c_class = {
 616         .name   = "i2c",
 617         .sysc   = &i2c_sysc,
 618         .rev    = OMAP_I2C_IP_VERSION_1,
 619         .reset  = &omap_i2c_reset,
 620 };
 621
 622 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 623         { .name = "dispc", .dma_req = 5 },
 624         { .name = "dsi1", .dma_req = 74 },
 625         { .dma_req = -1 }
 626 };
 627
 628 /* dss */
 629 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 630         /*
 631          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 632          * driver does not use these clocks.
 633          */
 634         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 635         { .role = "tv_clk", .clk = "dss_tv_fck" },
 636         /* required only on OMAP3430 */
 637         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 638 };
 639
 640 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 641         .name           = "dss_core",
 642         .class          = &omap2_dss_hwmod_class,
 643         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 644         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 645         .prcm           = {
 646                 .omap2 = {
 647                         .prcm_reg_id = 1,
 648                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 649                         .module_offs = OMAP3430_DSS_MOD,
 650                         .idlest_reg_id = 1,
 651                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 652                 },
 653         },
 654         .opt_clks       = dss_opt_clks,
 655         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 656         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 657 };
 658
 659 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 660         .name           = "dss_core",
 661         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 662         .class          = &omap2_dss_hwmod_class,
 663         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 664         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 665         .prcm           = {
 666                 .omap2 = {
 667                         .prcm_reg_id = 1,
 668                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 669                         .module_offs = OMAP3430_DSS_MOD,
 670                         .idlest_reg_id = 1,
 671                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 672                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 673                 },
 674         },
 675         .opt_clks       = dss_opt_clks,
 676         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 677 };
 678
 679 /*
 680  * 'dispc' class
 681  * display controller
 682  */
 683
 684 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 685         .rev_offs       = 0x0000,
 686         .sysc_offs      = 0x0010,
 687         .syss_offs      = 0x0014,
 688         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 689                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 690                            SYSC_HAS_ENAWAKEUP),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 697         .name   = "dispc",
 698         .sysc   = &omap3_dispc_sysc,
 699 };
 700
 701 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 702         .name           = "dss_dispc",
 703         .class          = &omap3_dispc_hwmod_class,
 704         .mpu_irqs       = omap2_dispc_irqs,
 705         .main_clk       = "dss1_alwon_fck",
 706         .prcm           = {
 707                 .omap2 = {
 708                         .prcm_reg_id = 1,
 709                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 710                         .module_offs = OMAP3430_DSS_MOD,
 711                 },
 712         },
 713         .flags          = HWMOD_NO_IDLEST,
 714         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 715 };
 716
 717 /*
 718  * 'dsi' class
 719  * display serial interface controller
 720  */
 721
 722 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 723         .name = "dsi",
 724 };
 725
 726 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 727         { .irq = 25 + OMAP_INTC_START, },
 728         { .irq = -1 },
 729 };
 730
 731 /* dss_dsi1 */
 732 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 733         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 734 };
 735
 736 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 737         .name           = "dss_dsi1",
 738         .class          = &omap3xxx_dsi_hwmod_class,
 739         .mpu_irqs       = omap3xxx_dsi1_irqs,
 740         .main_clk       = "dss1_alwon_fck",
 741         .prcm           = {
 742                 .omap2 = {
 743                         .prcm_reg_id = 1,
 744                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 745                         .module_offs = OMAP3430_DSS_MOD,
 746                 },
 747         },
 748         .opt_clks       = dss_dsi1_opt_clks,
 749         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 750         .flags          = HWMOD_NO_IDLEST,
 751 };
 752
 753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 754         { .role = "ick", .clk = "dss_ick" },
 755 };
 756
 757 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 758         .name           = "dss_rfbi",
 759         .class          = &omap2_rfbi_hwmod_class,
 760         .main_clk       = "dss1_alwon_fck",
 761         .prcm           = {
 762                 .omap2 = {
 763                         .prcm_reg_id = 1,
 764                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 765                         .module_offs = OMAP3430_DSS_MOD,
 766                 },
 767         },
 768         .opt_clks       = dss_rfbi_opt_clks,
 769         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 770         .flags          = HWMOD_NO_IDLEST,
 771 };
 772
 773 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 774         /* required only on OMAP3430 */
 775         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 776 };
 777
 778 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 779         .name           = "dss_venc",
 780         .class          = &omap2_venc_hwmod_class,
 781         .main_clk       = "dss_tv_fck",
 782         .prcm           = {
 783                 .omap2 = {
 784                         .prcm_reg_id = 1,
 785                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 786                         .module_offs = OMAP3430_DSS_MOD,
 787                 },
 788         },
 789         .opt_clks       = dss_venc_opt_clks,
 790         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 791         .flags          = HWMOD_NO_IDLEST,
 792 };
 793
 794 /* I2C1 */
 795 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 796         .fifo_depth     = 8, /* bytes */
 797         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 798                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 799                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 800 };
 801
 802 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 803         .name           = "i2c1",
 804         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 805         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 806         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 807         .main_clk       = "i2c1_fck",
 808         .prcm           = {
 809                 .omap2 = {
 810                         .module_offs = CORE_MOD,
 811                         .prcm_reg_id = 1,
 812                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 813                         .idlest_reg_id = 1,
 814                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 815                 },
 816         },
 817         .class          = &i2c_class,
 818         .dev_attr       = &i2c1_dev_attr,
 819 };
 820
 821 /* I2C2 */
 822 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 823         .fifo_depth     = 8, /* bytes */
 824         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 825                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 826                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 827 };
 828
 829 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 830         .name           = "i2c2",
 831         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 832         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 833         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 834         .main_clk       = "i2c2_fck",
 835         .prcm           = {
 836                 .omap2 = {
 837                         .module_offs = CORE_MOD,
 838                         .prcm_reg_id = 1,
 839                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 840                         .idlest_reg_id = 1,
 841                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 842                 },
 843         },
 844         .class          = &i2c_class,
 845         .dev_attr       = &i2c2_dev_attr,
 846 };
 847
 848 /* I2C3 */
 849 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 850         .fifo_depth     = 64, /* bytes */
 851         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 852                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 853                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 854 };
 855
 856 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 857         { .irq = 61 + OMAP_INTC_START, },
 858         { .irq = -1 },
 859 };
 860
 861 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 862         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 863         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 864         { .dma_req = -1 }
 865 };
 866
 867 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 868         .name           = "i2c3",
 869         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 870         .mpu_irqs       = i2c3_mpu_irqs,
 871         .sdma_reqs      = i2c3_sdma_reqs,
 872         .main_clk       = "i2c3_fck",
 873         .prcm           = {
 874                 .omap2 = {
 875                         .module_offs = CORE_MOD,
 876                         .prcm_reg_id = 1,
 877                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 878                         .idlest_reg_id = 1,
 879                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 880                 },
 881         },
 882         .class          = &i2c_class,
 883         .dev_attr       = &i2c3_dev_attr,
 884 };
 885
 886 /*
 887  * 'gpio' class
 888  * general purpose io module
 889  */
 890
 891 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 892         .rev_offs       = 0x0000,
 893         .sysc_offs      = 0x0010,
 894         .syss_offs      = 0x0014,
 895         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 896                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 897                            SYSS_HAS_RESET_STATUS),
 898         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 899         .sysc_fields    = &omap_hwmod_sysc_type1,
 900 };
 901
 902 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 903         .name = "gpio",
 904         .sysc = &omap3xxx_gpio_sysc,
 905         .rev = 1,
 906 };
 907
 908 /* gpio_dev_attr */
 909 static struct omap_gpio_dev_attr gpio_dev_attr = {
 910         .bank_width = 32,
 911         .dbck_flag = true,
 912 };
 913
 914 /* gpio1 */
 915 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 916         { .role = "dbclk", .clk = "gpio1_dbck", },
 917 };
 918
 919 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 920         .name           = "gpio1",
 921         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 922         .mpu_irqs       = omap2_gpio1_irqs,
 923         .main_clk       = "gpio1_ick",
 924         .opt_clks       = gpio1_opt_clks,
 925         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 926         .prcm           = {
 927                 .omap2 = {
 928                         .prcm_reg_id = 1,
 929                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 930                         .module_offs = WKUP_MOD,
 931                         .idlest_reg_id = 1,
 932                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 933                 },
 934         },
 935         .class          = &omap3xxx_gpio_hwmod_class,
 936         .dev_attr       = &gpio_dev_attr,
 937 };
 938
 939 /* gpio2 */
 940 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 941         { .role = "dbclk", .clk = "gpio2_dbck", },
 942 };
 943
 944 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 945         .name           = "gpio2",
 946         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 947         .mpu_irqs       = omap2_gpio2_irqs,
 948         .main_clk       = "gpio2_ick",
 949         .opt_clks       = gpio2_opt_clks,
 950         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 951         .prcm           = {
 952                 .omap2 = {
 953                         .prcm_reg_id = 1,
 954                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 955                         .module_offs = OMAP3430_PER_MOD,
 956                         .idlest_reg_id = 1,
 957                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 958                 },
 959         },
 960         .class          = &omap3xxx_gpio_hwmod_class,
 961         .dev_attr       = &gpio_dev_attr,
 962 };
 963
 964 /* gpio3 */
 965 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 966         { .role = "dbclk", .clk = "gpio3_dbck", },
 967 };
 968
 969 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 970         .name           = "gpio3",
 971         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 972         .mpu_irqs       = omap2_gpio3_irqs,
 973         .main_clk       = "gpio3_ick",
 974         .opt_clks       = gpio3_opt_clks,
 975         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 976         .prcm           = {
 977                 .omap2 = {
 978                         .prcm_reg_id = 1,
 979                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 980                         .module_offs = OMAP3430_PER_MOD,
 981                         .idlest_reg_id = 1,
 982                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 983                 },
 984         },
 985         .class          = &omap3xxx_gpio_hwmod_class,
 986         .dev_attr       = &gpio_dev_attr,
 987 };
 988
 989 /* gpio4 */
 990 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 991         { .role = "dbclk", .clk = "gpio4_dbck", },
 992 };
 993
 994 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 995         .name           = "gpio4",
 996         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 997         .mpu_irqs       = omap2_gpio4_irqs,
 998         .main_clk       = "gpio4_ick",
 999         .opt_clks       = gpio4_opt_clks,
1000         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1001         .prcm           = {
1002                 .omap2 = {
1003                         .prcm_reg_id = 1,
1004                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1005                         .module_offs = OMAP3430_PER_MOD,
1006                         .idlest_reg_id = 1,
1007                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1008                 },
1009         },
1010         .class          = &omap3xxx_gpio_hwmod_class,
1011         .dev_attr       = &gpio_dev_attr,
1012 };
1013
1014 /* gpio5 */
1015 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1016         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1017         { .irq = -1 },
1018 };
1019
1020 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1021         { .role = "dbclk", .clk = "gpio5_dbck", },
1022 };
1023
1024 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1025         .name           = "gpio5",
1026         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1027         .mpu_irqs       = omap3xxx_gpio5_irqs,
1028         .main_clk       = "gpio5_ick",
1029         .opt_clks       = gpio5_opt_clks,
1030         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1031         .prcm           = {
1032                 .omap2 = {
1033                         .prcm_reg_id = 1,
1034                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1035                         .module_offs = OMAP3430_PER_MOD,
1036                         .idlest_reg_id = 1,
1037                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1038                 },
1039         },
1040         .class          = &omap3xxx_gpio_hwmod_class,
1041         .dev_attr       = &gpio_dev_attr,
1042 };
1043
1044 /* gpio6 */
1045 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1046         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1047         { .irq = -1 },
1048 };
1049
1050 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1051         { .role = "dbclk", .clk = "gpio6_dbck", },
1052 };
1053
1054 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1055         .name           = "gpio6",
1056         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1057         .mpu_irqs       = omap3xxx_gpio6_irqs,
1058         .main_clk       = "gpio6_ick",
1059         .opt_clks       = gpio6_opt_clks,
1060         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1061         .prcm           = {
1062                 .omap2 = {
1063                         .prcm_reg_id = 1,
1064                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1065                         .module_offs = OMAP3430_PER_MOD,
1066                         .idlest_reg_id = 1,
1067                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1068                 },
1069         },
1070         .class          = &omap3xxx_gpio_hwmod_class,
1071         .dev_attr       = &gpio_dev_attr,
1072 };
1073
1074 /* dma attributes */
1075 static struct omap_dma_dev_attr dma_dev_attr = {
1076         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1077                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1078         .lch_count = 32,
1079 };
1080
1081 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1082         .rev_offs       = 0x0000,
1083         .sysc_offs      = 0x002c,
1084         .syss_offs      = 0x0028,
1085         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1086                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1087                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1088                            SYSS_HAS_RESET_STATUS),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type1,
1092 };
1093
1094 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1095         .name = "dma",
1096         .sysc = &omap3xxx_dma_sysc,
1097 };
1098
1099 /* dma_system */
1100 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1101         .name           = "dma",
1102         .class          = &omap3xxx_dma_hwmod_class,
1103         .mpu_irqs       = omap2_dma_system_irqs,
1104         .main_clk       = "core_l3_ick",
1105         .prcm = {
1106                 .omap2 = {
1107                         .module_offs            = CORE_MOD,
1108                         .prcm_reg_id            = 1,
1109                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1110                         .idlest_reg_id          = 1,
1111                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1112                 },
1113         },
1114         .dev_attr       = &dma_dev_attr,
1115         .flags          = HWMOD_NO_IDLEST,
1116 };
1117
1118 /*
1119  * 'mcbsp' class
1120  * multi channel buffered serial port controller
1121  */
1122
1123 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1124         .sysc_offs      = 0x008c,
1125         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1126                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1128         .sysc_fields    = &omap_hwmod_sysc_type1,
1129         .clockact       = 0x2,
1130 };
1131
1132 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1133         .name = "mcbsp",
1134         .sysc = &omap3xxx_mcbsp_sysc,
1135         .rev  = MCBSP_CONFIG_TYPE3,
1136 };
1137
1138 /* McBSP functional clock mapping */
1139 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1140         { .role = "pad_fck", .clk = "mcbsp_clks" },
1141         { .role = "prcm_fck", .clk = "core_96m_fck" },
1142 };
1143
1144 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1145         { .role = "pad_fck", .clk = "mcbsp_clks" },
1146         { .role = "prcm_fck", .clk = "per_96m_fck" },
1147 };
1148
1149 /* mcbsp1 */
1150 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1151         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1152         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1153         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1154         { .irq = -1 },
1155 };
1156
1157 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1158         .name           = "mcbsp1",
1159         .class          = &omap3xxx_mcbsp_hwmod_class,
1160         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1161         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1162         .main_clk       = "mcbsp1_fck",
1163         .prcm           = {
1164                 .omap2 = {
1165                         .prcm_reg_id = 1,
1166                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1167                         .module_offs = CORE_MOD,
1168                         .idlest_reg_id = 1,
1169                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1170                 },
1171         },
1172         .opt_clks       = mcbsp15_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1174 };
1175
1176 /* mcbsp2 */
1177 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1178         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1179         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1180         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1181         { .irq = -1 },
1182 };
1183
1184 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1185         .sidetone       = "mcbsp2_sidetone",
1186 };
1187
1188 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1189         .name           = "mcbsp2",
1190         .class          = &omap3xxx_mcbsp_hwmod_class,
1191         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1192         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1193         .main_clk       = "mcbsp2_fck",
1194         .prcm           = {
1195                 .omap2 = {
1196                         .prcm_reg_id = 1,
1197                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1198                         .module_offs = OMAP3430_PER_MOD,
1199                         .idlest_reg_id = 1,
1200                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1201                 },
1202         },
1203         .opt_clks       = mcbsp234_opt_clks,
1204         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1205         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1206 };
1207
1208 /* mcbsp3 */
1209 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1210         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1211         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1212         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1213         { .irq = -1 },
1214 };
1215
1216 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1217         .sidetone       = "mcbsp3_sidetone",
1218 };
1219
1220 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1221         .name           = "mcbsp3",
1222         .class          = &omap3xxx_mcbsp_hwmod_class,
1223         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1224         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1225         .main_clk       = "mcbsp3_fck",
1226         .prcm           = {
1227                 .omap2 = {
1228                         .prcm_reg_id = 1,
1229                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1230                         .module_offs = OMAP3430_PER_MOD,
1231                         .idlest_reg_id = 1,
1232                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1233                 },
1234         },
1235         .opt_clks       = mcbsp234_opt_clks,
1236         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1237         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1238 };
1239
1240 /* mcbsp4 */
1241 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1242         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1243         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1244         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1245         { .irq = -1 },
1246 };
1247
1248 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1249         { .name = "rx", .dma_req = 20 },
1250         { .name = "tx", .dma_req = 19 },
1251         { .dma_req = -1 }
1252 };
1253
1254 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1255         .name           = "mcbsp4",
1256         .class          = &omap3xxx_mcbsp_hwmod_class,
1257         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1258         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1259         .main_clk       = "mcbsp4_fck",
1260         .prcm           = {
1261                 .omap2 = {
1262                         .prcm_reg_id = 1,
1263                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1264                         .module_offs = OMAP3430_PER_MOD,
1265                         .idlest_reg_id = 1,
1266                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1267                 },
1268         },
1269         .opt_clks       = mcbsp234_opt_clks,
1270         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1271 };
1272
1273 /* mcbsp5 */
1274 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1275         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1276         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1277         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1278         { .irq = -1 },
1279 };
1280
1281 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1282         { .name = "rx", .dma_req = 22 },
1283         { .name = "tx", .dma_req = 21 },
1284         { .dma_req = -1 }
1285 };
1286
1287 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1288         .name           = "mcbsp5",
1289         .class          = &omap3xxx_mcbsp_hwmod_class,
1290         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1291         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1292         .main_clk       = "mcbsp5_fck",
1293         .prcm           = {
1294                 .omap2 = {
1295                         .prcm_reg_id = 1,
1296                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1297                         .module_offs = CORE_MOD,
1298                         .idlest_reg_id = 1,
1299                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1300                 },
1301         },
1302         .opt_clks       = mcbsp15_opt_clks,
1303         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1304 };
1305
1306 /* 'mcbsp sidetone' class */
1307 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1308         .sysc_offs      = 0x0010,
1309         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1310         .sysc_fields    = &omap_hwmod_sysc_type1,
1311 };
1312
1313 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1314         .name = "mcbsp_sidetone",
1315         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1316 };
1317
1318 /* mcbsp2_sidetone */
1319 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1320         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1321         { .irq = -1 },
1322 };
1323
1324 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1325         .name           = "mcbsp2_sidetone",
1326         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1327         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1328         .main_clk       = "mcbsp2_fck",
1329         .prcm           = {
1330                 .omap2 = {
1331                         .prcm_reg_id = 1,
1332                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1333                         .module_offs = OMAP3430_PER_MOD,
1334                         .idlest_reg_id = 1,
1335                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1336                 },
1337         },
1338 };
1339
1340 /* mcbsp3_sidetone */
1341 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1342         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1343         { .irq = -1 },
1344 };
1345
1346 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1347         .name           = "mcbsp3_sidetone",
1348         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1349         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1350         .main_clk       = "mcbsp3_fck",
1351         .prcm           = {
1352                 .omap2 = {
1353                         .prcm_reg_id = 1,
1354                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1355                         .module_offs = OMAP3430_PER_MOD,
1356                         .idlest_reg_id = 1,
1357                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1358                 },
1359         },
1360 };
1361
1362 /* SR common */
1363 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1364         .clkact_shift   = 20,
1365 };
1366
1367 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1368         .sysc_offs      = 0x24,
1369         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1370         .clockact       = CLOCKACT_TEST_ICLK,
1371         .sysc_fields    = &omap34xx_sr_sysc_fields,
1372 };
1373
1374 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1375         .name = "smartreflex",
1376         .sysc = &omap34xx_sr_sysc,
1377         .rev  = 1,
1378 };
1379
1380 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1381         .sidle_shift    = 24,
1382         .enwkup_shift   = 26,
1383 };
1384
1385 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1386         .sysc_offs      = 0x38,
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1388         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1389                         SYSC_NO_CACHE),
1390         .sysc_fields    = &omap36xx_sr_sysc_fields,
1391 };
1392
1393 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1394         .name = "smartreflex",
1395         .sysc = &omap36xx_sr_sysc,
1396         .rev  = 2,
1397 };
1398
1399 /* SR1 */
1400 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1401         .sensor_voltdm_name   = "mpu_iva",
1402 };
1403
1404 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1405         { .irq = 18 + OMAP_INTC_START, },
1406         { .irq = -1 },
1407 };
1408
1409 static struct omap_hwmod omap34xx_sr1_hwmod = {
1410         .name           = "smartreflex_mpu_iva",
1411         .class          = &omap34xx_smartreflex_hwmod_class,
1412         .main_clk       = "sr1_fck",
1413         .prcm           = {
1414                 .omap2 = {
1415                         .prcm_reg_id = 1,
1416                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1417                         .module_offs = WKUP_MOD,
1418                         .idlest_reg_id = 1,
1419                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1420                 },
1421         },
1422         .dev_attr       = &sr1_dev_attr,
1423         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1424         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1425 };
1426
1427 static struct omap_hwmod omap36xx_sr1_hwmod = {
1428         .name           = "smartreflex_mpu_iva",
1429         .class          = &omap36xx_smartreflex_hwmod_class,
1430         .main_clk       = "sr1_fck",
1431         .prcm           = {
1432                 .omap2 = {
1433                         .prcm_reg_id = 1,
1434                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1435                         .module_offs = WKUP_MOD,
1436                         .idlest_reg_id = 1,
1437                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1438                 },
1439         },
1440         .dev_attr       = &sr1_dev_attr,
1441         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1442 };
1443
1444 /* SR2 */
1445 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1446         .sensor_voltdm_name     = "core",
1447 };
1448
1449 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1450         { .irq = 19 + OMAP_INTC_START, },
1451         { .irq = -1 },
1452 };
1453
1454 static struct omap_hwmod omap34xx_sr2_hwmod = {
1455         .name           = "smartreflex_core",
1456         .class          = &omap34xx_smartreflex_hwmod_class,
1457         .main_clk       = "sr2_fck",
1458         .prcm           = {
1459                 .omap2 = {
1460                         .prcm_reg_id = 1,
1461                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1462                         .module_offs = WKUP_MOD,
1463                         .idlest_reg_id = 1,
1464                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1465                 },
1466         },
1467         .dev_attr       = &sr2_dev_attr,
1468         .mpu_irqs       = omap3_smartreflex_core_irqs,
1469         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1470 };
1471
1472 static struct omap_hwmod omap36xx_sr2_hwmod = {
1473         .name           = "smartreflex_core",
1474         .class          = &omap36xx_smartreflex_hwmod_class,
1475         .main_clk       = "sr2_fck",
1476         .prcm           = {
1477                 .omap2 = {
1478                         .prcm_reg_id = 1,
1479                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1480                         .module_offs = WKUP_MOD,
1481                         .idlest_reg_id = 1,
1482                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1483                 },
1484         },
1485         .dev_attr       = &sr2_dev_attr,
1486         .mpu_irqs       = omap3_smartreflex_core_irqs,
1487 };
1488
1489 /*
1490  * 'mailbox' class
1491  * mailbox module allowing communication between the on-chip processors
1492  * using a queued mailbox-interrupt mechanism.
1493  */
1494
1495 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1496         .rev_offs       = 0x000,
1497         .sysc_offs      = 0x010,
1498         .syss_offs      = 0x014,
1499         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1500                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1502         .sysc_fields    = &omap_hwmod_sysc_type1,
1503 };
1504
1505 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1506         .name = "mailbox",
1507         .sysc = &omap3xxx_mailbox_sysc,
1508 };
1509
1510 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1511         { .irq = 26 + OMAP_INTC_START, },
1512         { .irq = -1 },
1513 };
1514
1515 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1516         .name           = "mailbox",
1517         .class          = &omap3xxx_mailbox_hwmod_class,
1518         .mpu_irqs       = omap3xxx_mailbox_irqs,
1519         .main_clk       = "mailboxes_ick",
1520         .prcm           = {
1521                 .omap2 = {
1522                         .prcm_reg_id = 1,
1523                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1524                         .module_offs = CORE_MOD,
1525                         .idlest_reg_id = 1,
1526                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1527                 },
1528         },
1529 };
1530
1531 /*
1532  * 'mcspi' class
1533  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1534  * bus
1535  */
1536
1537 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1538         .rev_offs       = 0x0000,
1539         .sysc_offs      = 0x0010,
1540         .syss_offs      = 0x0014,
1541         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1542                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1543                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1544         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1545         .sysc_fields    = &omap_hwmod_sysc_type1,
1546 };
1547
1548 static struct omap_hwmod_class omap34xx_mcspi_class = {
1549         .name = "mcspi",
1550         .sysc = &omap34xx_mcspi_sysc,
1551         .rev = OMAP3_MCSPI_REV,
1552 };
1553
1554 /* mcspi1 */
1555 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1556         .num_chipselect = 4,
1557 };
1558
1559 static struct omap_hwmod omap34xx_mcspi1 = {
1560         .name           = "mcspi1",
1561         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1562         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1563         .main_clk       = "mcspi1_fck",
1564         .prcm           = {
1565                 .omap2 = {
1566                         .module_offs = CORE_MOD,
1567                         .prcm_reg_id = 1,
1568                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1569                         .idlest_reg_id = 1,
1570                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1571                 },
1572         },
1573         .class          = &omap34xx_mcspi_class,
1574         .dev_attr       = &omap_mcspi1_dev_attr,
1575 };
1576
1577 /* mcspi2 */
1578 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1579         .num_chipselect = 2,
1580 };
1581
1582 static struct omap_hwmod omap34xx_mcspi2 = {
1583         .name           = "mcspi2",
1584         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1585         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1586         .main_clk       = "mcspi2_fck",
1587         .prcm           = {
1588                 .omap2 = {
1589                         .module_offs = CORE_MOD,
1590                         .prcm_reg_id = 1,
1591                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1592                         .idlest_reg_id = 1,
1593                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1594                 },
1595         },
1596         .class          = &omap34xx_mcspi_class,
1597         .dev_attr       = &omap_mcspi2_dev_attr,
1598 };
1599
1600 /* mcspi3 */
1601 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1602         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1603         { .irq = -1 },
1604 };
1605
1606 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1607         { .name = "tx0", .dma_req = 15 },
1608         { .name = "rx0", .dma_req = 16 },
1609         { .name = "tx1", .dma_req = 23 },
1610         { .name = "rx1", .dma_req = 24 },
1611         { .dma_req = -1 }
1612 };
1613
1614 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1615         .num_chipselect = 2,
1616 };
1617
1618 static struct omap_hwmod omap34xx_mcspi3 = {
1619         .name           = "mcspi3",
1620         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1621         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1622         .main_clk       = "mcspi3_fck",
1623         .prcm           = {
1624                 .omap2 = {
1625                         .module_offs = CORE_MOD,
1626                         .prcm_reg_id = 1,
1627                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1628                         .idlest_reg_id = 1,
1629                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1630                 },
1631         },
1632         .class          = &omap34xx_mcspi_class,
1633         .dev_attr       = &omap_mcspi3_dev_attr,
1634 };
1635
1636 /* mcspi4 */
1637 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1638         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1639         { .irq = -1 },
1640 };
1641
1642 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1643         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1644         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1645         { .dma_req = -1 }
1646 };
1647
1648 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1649         .num_chipselect = 1,
1650 };
1651
1652 static struct omap_hwmod omap34xx_mcspi4 = {
1653         .name           = "mcspi4",
1654         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1655         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1656         .main_clk       = "mcspi4_fck",
1657         .prcm           = {
1658                 .omap2 = {
1659                         .module_offs = CORE_MOD,
1660                         .prcm_reg_id = 1,
1661                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1662                         .idlest_reg_id = 1,
1663                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1664                 },
1665         },
1666         .class          = &omap34xx_mcspi_class,
1667         .dev_attr       = &omap_mcspi4_dev_attr,
1668 };
1669
1670 /* usbhsotg */
1671 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1672         .rev_offs       = 0x0400,
1673         .sysc_offs      = 0x0404,
1674         .syss_offs      = 0x0408,
1675         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1676                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1677                           SYSC_HAS_AUTOIDLE),
1678         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1679                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1680         .sysc_fields    = &omap_hwmod_sysc_type1,
1681 };
1682
1683 static struct omap_hwmod_class usbotg_class = {
1684         .name = "usbotg",
1685         .sysc = &omap3xxx_usbhsotg_sysc,
1686 };
1687
1688 /* usb_otg_hs */
1689 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1690
1691         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1692         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1693         { .irq = -1 },
1694 };
1695
1696 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1697         .name           = "usb_otg_hs",
1698         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1699         .main_clk       = "hsotgusb_ick",
1700         .prcm           = {
1701                 .omap2 = {
1702                         .prcm_reg_id = 1,
1703                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1704                         .module_offs = CORE_MOD,
1705                         .idlest_reg_id = 1,
1706                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1707                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1708                 },
1709         },
1710         .class          = &usbotg_class,
1711
1712         /*
1713          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1714          * broken when autoidle is enabled
1715          * workaround is to disable the autoidle bit at module level.
1716          */
1717         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1718                                 | HWMOD_SWSUP_MSTANDBY,
1719 };
1720
1721 /* usb_otg_hs */
1722 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1723         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1724         { .irq = -1 },
1725 };
1726
1727 static struct omap_hwmod_class am35xx_usbotg_class = {
1728         .name = "am35xx_usbotg",
1729 };
1730
1731 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1732         .name           = "am35x_otg_hs",
1733         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1734         .main_clk       = "hsotgusb_fck",
1735         .class          = &am35xx_usbotg_class,
1736         .flags          = HWMOD_NO_IDLEST,
1737 };
1738
1739 /* MMC/SD/SDIO common */
1740 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1741         .rev_offs       = 0x1fc,
1742         .sysc_offs      = 0x10,
1743         .syss_offs      = 0x14,
1744         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1745                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1746                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1747         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1748         .sysc_fields    = &omap_hwmod_sysc_type1,
1749 };
1750
1751 static struct omap_hwmod_class omap34xx_mmc_class = {
1752         .name = "mmc",
1753         .sysc = &omap34xx_mmc_sysc,
1754 };
1755
1756 /* MMC/SD/SDIO1 */
1757
1758 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1759         { .irq = 83 + OMAP_INTC_START, },
1760         { .irq = -1 },
1761 };
1762
1763 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1764         { .name = "tx", .dma_req = 61, },
1765         { .name = "rx", .dma_req = 62, },
1766         { .dma_req = -1 }
1767 };
1768
1769 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1770         { .role = "dbck", .clk = "omap_32k_fck", },
1771 };
1772
1773 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1774         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1775 };
1776
1777 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1778 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1779         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1780                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1781 };
1782
1783 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1784         .name           = "mmc1",
1785         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1786         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1787         .opt_clks       = omap34xx_mmc1_opt_clks,
1788         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1789         .main_clk       = "mmchs1_fck",
1790         .prcm           = {
1791                 .omap2 = {
1792                         .module_offs = CORE_MOD,
1793                         .prcm_reg_id = 1,
1794                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1795                         .idlest_reg_id = 1,
1796                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1797                 },
1798         },
1799         .dev_attr       = &mmc1_pre_es3_dev_attr,
1800         .class          = &omap34xx_mmc_class,
1801 };
1802
1803 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1804         .name           = "mmc1",
1805         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1806         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1807         .opt_clks       = omap34xx_mmc1_opt_clks,
1808         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1809         .main_clk       = "mmchs1_fck",
1810         .prcm           = {
1811                 .omap2 = {
1812                         .module_offs = CORE_MOD,
1813                         .prcm_reg_id = 1,
1814                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1815                         .idlest_reg_id = 1,
1816                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1817                 },
1818         },
1819         .dev_attr       = &mmc1_dev_attr,
1820         .class          = &omap34xx_mmc_class,
1821 };
1822
1823 /* MMC/SD/SDIO2 */
1824
1825 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1826         { .irq = 86 + OMAP_INTC_START, },
1827         { .irq = -1 },
1828 };
1829
1830 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1831         { .name = "tx", .dma_req = 47, },
1832         { .name = "rx", .dma_req = 48, },
1833         { .dma_req = -1 }
1834 };
1835
1836 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1837         { .role = "dbck", .clk = "omap_32k_fck", },
1838 };
1839
1840 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1841 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1842         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1843 };
1844
1845 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1846         .name           = "mmc2",
1847         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1848         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1849         .opt_clks       = omap34xx_mmc2_opt_clks,
1850         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1851         .main_clk       = "mmchs2_fck",
1852         .prcm           = {
1853                 .omap2 = {
1854                         .module_offs = CORE_MOD,
1855                         .prcm_reg_id = 1,
1856                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1857                         .idlest_reg_id = 1,
1858                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1859                 },
1860         },
1861         .dev_attr       = &mmc2_pre_es3_dev_attr,
1862         .class          = &omap34xx_mmc_class,
1863 };
1864
1865 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1866         .name           = "mmc2",
1867         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1868         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1869         .opt_clks       = omap34xx_mmc2_opt_clks,
1870         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1871         .main_clk       = "mmchs2_fck",
1872         .prcm           = {
1873                 .omap2 = {
1874                         .module_offs = CORE_MOD,
1875                         .prcm_reg_id = 1,
1876                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1877                         .idlest_reg_id = 1,
1878                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1879                 },
1880         },
1881         .class          = &omap34xx_mmc_class,
1882 };
1883
1884 /* MMC/SD/SDIO3 */
1885
1886 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1887         { .irq = 94 + OMAP_INTC_START, },
1888         { .irq = -1 },
1889 };
1890
1891 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1892         { .name = "tx", .dma_req = 77, },
1893         { .name = "rx", .dma_req = 78, },
1894         { .dma_req = -1 }
1895 };
1896
1897 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1898         { .role = "dbck", .clk = "omap_32k_fck", },
1899 };
1900
1901 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1902         .name           = "mmc3",
1903         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1904         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1905         .opt_clks       = omap34xx_mmc3_opt_clks,
1906         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1907         .main_clk       = "mmchs3_fck",
1908         .prcm           = {
1909                 .omap2 = {
1910                         .prcm_reg_id = 1,
1911                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1912                         .idlest_reg_id = 1,
1913                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1914                 },
1915         },
1916         .class          = &omap34xx_mmc_class,
1917 };
1918
1919 /*
1920  * 'usb_host_hs' class
1921  * high-speed multi-port usb host controller
1922  */
1923
1924 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1925         .rev_offs       = 0x0000,
1926         .sysc_offs      = 0x0010,
1927         .syss_offs      = 0x0014,
1928         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1929                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1930                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1932                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1933         .sysc_fields    = &omap_hwmod_sysc_type1,
1934 };
1935
1936 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1937         .name = "usb_host_hs",
1938         .sysc = &omap3xxx_usb_host_hs_sysc,
1939 };
1940
1941 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1942           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1943 };
1944
1945 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1946         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1947         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1948         { .irq = -1 },
1949 };
1950
1951 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1952         .name           = "usb_host_hs",
1953         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1954         .clkdm_name     = "l3_init_clkdm",
1955         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1956         .main_clk       = "usbhost_48m_fck",
1957         .prcm = {
1958                 .omap2 = {
1959                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1960                         .prcm_reg_id = 1,
1961                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1962                         .idlest_reg_id = 1,
1963                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1964                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1965                 },
1966         },
1967         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1968         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1969
1970         /*
1971          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1972          * id: i660
1973          *
1974          * Description:
1975          * In the following configuration :
1976          * - USBHOST module is set to smart-idle mode
1977          * - PRCM asserts idle_req to the USBHOST module ( This typically
1978          *   happens when the system is going to a low power mode : all ports
1979          *   have been suspended, the master part of the USBHOST module has
1980          *   entered the standby state, and SW has cut the functional clocks)
1981          * - an USBHOST interrupt occurs before the module is able to answer
1982          *   idle_ack, typically a remote wakeup IRQ.
1983          * Then the USB HOST module will enter a deadlock situation where it
1984          * is no more accessible nor functional.
1985          *
1986          * Workaround:
1987          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1988          */
1989
1990         /*
1991          * Errata: USB host EHCI may stall when entering smart-standby mode
1992          * Id: i571
1993          *
1994          * Description:
1995          * When the USBHOST module is set to smart-standby mode, and when it is
1996          * ready to enter the standby state (i.e. all ports are suspended and
1997          * all attached devices are in suspend mode), then it can wrongly assert
1998          * the Mstandby signal too early while there are still some residual OCP
1999          * transactions ongoing. If this condition occurs, the internal state
2000          * machine may go to an undefined state and the USB link may be stuck
2001          * upon the next resume.
2002          *
2003          * Workaround:
2004          * Don't use smart standby; use only force standby,
2005          * hence HWMOD_SWSUP_MSTANDBY
2006          */
2007
2008         /*
2009          * During system boot; If the hwmod framework resets the module
2010          * the module will have smart idle settings; which can lead to deadlock
2011          * (above Errata Id:i660); so, dont reset the module during boot;
2012          * Use HWMOD_INIT_NO_RESET.
2013          */
2014
2015         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2016                           HWMOD_INIT_NO_RESET,
2017 };
2018
2019 /*
2020  * 'usb_tll_hs' class
2021  * usb_tll_hs module is the adapter on the usb_host_hs ports
2022  */
2023 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2024         .rev_offs       = 0x0000,
2025         .sysc_offs      = 0x0010,
2026         .syss_offs      = 0x0014,
2027         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2028                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2029                            SYSC_HAS_AUTOIDLE),
2030         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2031         .sysc_fields    = &omap_hwmod_sysc_type1,
2032 };
2033
2034 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2035         .name = "usb_tll_hs",
2036         .sysc = &omap3xxx_usb_tll_hs_sysc,
2037 };
2038
2039 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2040         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2041         { .irq = -1 },
2042 };
2043
2044 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2045         .name           = "usb_tll_hs",
2046         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2047         .clkdm_name     = "l3_init_clkdm",
2048         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2049         .main_clk       = "usbtll_fck",
2050         .prcm = {
2051                 .omap2 = {
2052                         .module_offs = CORE_MOD,
2053                         .prcm_reg_id = 3,
2054                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2055                         .idlest_reg_id = 3,
2056                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2057                 },
2058         },
2059 };
2060
2061 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2062         .name           = "hdq1w",
2063         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2064         .main_clk       = "hdq_fck",
2065         .prcm           = {
2066                 .omap2 = {
2067                         .module_offs = CORE_MOD,
2068                         .prcm_reg_id = 1,
2069                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2070                         .idlest_reg_id = 1,
2071                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2072                 },
2073         },
2074         .class          = &omap2_hdq1w_class,
2075 };
2076
2077 /* SAD2D */
2078 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2079         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2080         { .name = "rst_modem_sw", .rst_shift = 1 },
2081 };
2082
2083 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2084         .name                   = "sad2d",
2085 };
2086
2087 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2088         .name           = "sad2d",
2089         .rst_lines      = omap3xxx_sad2d_resets,
2090         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2091         .main_clk       = "sad2d_ick",
2092         .prcm           = {
2093                 .omap2 = {
2094                         .module_offs = CORE_MOD,
2095                         .prcm_reg_id = 1,
2096                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2097                         .idlest_reg_id = 1,
2098                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2099                 },
2100         },
2101         .class          = &omap3xxx_sad2d_class,
2102 };
2103
2104 /*
2105  * '32K sync counter' class
2106  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2107  */
2108 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2109         .rev_offs       = 0x0000,
2110         .sysc_offs      = 0x0004,
2111         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2113         .sysc_fields    = &omap_hwmod_sysc_type1,
2114 };
2115
2116 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2117         .name   = "counter",
2118         .sysc   = &omap3xxx_counter_sysc,
2119 };
2120
2121 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2122         .name           = "counter_32k",
2123         .class          = &omap3xxx_counter_hwmod_class,
2124         .clkdm_name     = "wkup_clkdm",
2125         .flags          = HWMOD_SWSUP_SIDLE,
2126         .main_clk       = "wkup_32k_fck",
2127         .prcm           = {
2128                 .omap2  = {
2129                         .module_offs = WKUP_MOD,
2130                         .prcm_reg_id = 1,
2131                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2132                         .idlest_reg_id = 1,
2133                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2134                 },
2135         },
2136 };
2137
2138 /*
2139  * 'gpmc' class
2140  * general purpose memory controller
2141  */
2142
2143 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2144         .rev_offs       = 0x0000,
2145         .sysc_offs      = 0x0010,
2146         .syss_offs      = 0x0014,
2147         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2148                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2149         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2150         .sysc_fields    = &omap_hwmod_sysc_type1,
2151 };
2152
2153 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2154         .name   = "gpmc",
2155         .sysc   = &omap3xxx_gpmc_sysc,
2156 };
2157
2158 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2159         { .irq = 20 },
2160         { .irq = -1 }
2161 };
2162
2163 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2164         .name           = "gpmc",
2165         .class          = &omap3xxx_gpmc_hwmod_class,
2166         .clkdm_name     = "core_l3_clkdm",
2167         .mpu_irqs       = omap3xxx_gpmc_irqs,
2168         .main_clk       = "gpmc_fck",
2169         /*
2170          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2171          * block.  It is not being added due to any known bugs with
2172          * resetting the GPMC IP block, but rather because any timings
2173          * set by the bootloader are not being correctly programmed by
2174          * the kernel from the board file or DT data.
2175          * HWMOD_INIT_NO_RESET should be removed ASAP.
2176          */
2177         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2178                            HWMOD_NO_IDLEST),
2179 };
2180
2181 /*
2182  * interfaces
2183  */
2184
2185 /* L3 -> L4_CORE interface */
2186 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2187         .master = &omap3xxx_l3_main_hwmod,
2188         .slave  = &omap3xxx_l4_core_hwmod,
2189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192 /* L3 -> L4_PER interface */
2193 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2194         .master = &omap3xxx_l3_main_hwmod,
2195         .slave  = &omap3xxx_l4_per_hwmod,
2196         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2197 };
2198
2199 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2200         {
2201                 .pa_start       = 0x68000000,
2202                 .pa_end         = 0x6800ffff,
2203                 .flags          = ADDR_TYPE_RT,
2204         },
2205         { }
2206 };
2207
2208 /* MPU -> L3 interface */
2209 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2210         .master   = &omap3xxx_mpu_hwmod,
2211         .slave    = &omap3xxx_l3_main_hwmod,
2212         .addr     = omap3xxx_l3_main_addrs,
2213         .user   = OCP_USER_MPU,
2214 };
2215
2216 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2217         {
2218                 .pa_start       = 0x54000000,
2219                 .pa_end         = 0x547fffff,
2220                 .flags          = ADDR_TYPE_RT,
2221         },
2222         { }
2223 };
2224
2225 /* l3 -> debugss */
2226 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2227         .master         = &omap3xxx_l3_main_hwmod,
2228         .slave          = &omap3xxx_debugss_hwmod,
2229         .addr           = omap3xxx_l4_emu_addrs,
2230         .user           = OCP_USER_MPU,
2231 };
2232
2233 /* DSS -> l3 */
2234 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2235         .master         = &omap3430es1_dss_core_hwmod,
2236         .slave          = &omap3xxx_l3_main_hwmod,
2237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2241         .master         = &omap3xxx_dss_core_hwmod,
2242         .slave          = &omap3xxx_l3_main_hwmod,
2243         .fw = {
2244                 .omap2 = {
2245                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2246                         .flags  = OMAP_FIREWALL_L3,
2247                 }
2248         },
2249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2250 };
2251
2252 /* l3_core -> usbhsotg interface */
2253 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2254         .master         = &omap3xxx_usbhsotg_hwmod,
2255         .slave          = &omap3xxx_l3_main_hwmod,
2256         .clk            = "core_l3_ick",
2257         .user           = OCP_USER_MPU,
2258 };
2259
2260 /* l3_core -> am35xx_usbhsotg interface */
2261 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2262         .master         = &am35xx_usbhsotg_hwmod,
2263         .slave          = &omap3xxx_l3_main_hwmod,
2264         .clk            = "hsotgusb_ick",
2265         .user           = OCP_USER_MPU,
2266 };
2267
2268 /* l3_core -> sad2d interface */
2269 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2270         .master         = &omap3xxx_sad2d_hwmod,
2271         .slave          = &omap3xxx_l3_main_hwmod,
2272         .clk            = "core_l3_ick",
2273         .user           = OCP_USER_MPU,
2274 };
2275
2276 /* L4_CORE -> L4_WKUP interface */
2277 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2278         .master = &omap3xxx_l4_core_hwmod,
2279         .slave  = &omap3xxx_l4_wkup_hwmod,
2280         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2281 };
2282
2283 /* L4 CORE -> MMC1 interface */
2284 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2285         .master         = &omap3xxx_l4_core_hwmod,
2286         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2287         .clk            = "mmchs1_ick",
2288         .addr           = omap2430_mmc1_addr_space,
2289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2290         .flags          = OMAP_FIREWALL_L4
2291 };
2292
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2294         .master         = &omap3xxx_l4_core_hwmod,
2295         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2296         .clk            = "mmchs1_ick",
2297         .addr           = omap2430_mmc1_addr_space,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299         .flags          = OMAP_FIREWALL_L4
2300 };
2301
2302 /* L4 CORE -> MMC2 interface */
2303 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2304         .master         = &omap3xxx_l4_core_hwmod,
2305         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2306         .clk            = "mmchs2_ick",
2307         .addr           = omap2430_mmc2_addr_space,
2308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2309         .flags          = OMAP_FIREWALL_L4
2310 };
2311
2312 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2313         .master         = &omap3xxx_l4_core_hwmod,
2314         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2315         .clk            = "mmchs2_ick",
2316         .addr           = omap2430_mmc2_addr_space,
2317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2318         .flags          = OMAP_FIREWALL_L4
2319 };
2320
2321 /* L4 CORE -> MMC3 interface */
2322 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2323         {
2324                 .pa_start       = 0x480ad000,
2325                 .pa_end         = 0x480ad1ff,
2326                 .flags          = ADDR_TYPE_RT,
2327         },
2328         { }
2329 };
2330
2331 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2332         .master         = &omap3xxx_l4_core_hwmod,
2333         .slave          = &omap3xxx_mmc3_hwmod,
2334         .clk            = "mmchs3_ick",
2335         .addr           = omap3xxx_mmc3_addr_space,
2336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2337         .flags          = OMAP_FIREWALL_L4
2338 };
2339
2340 /* L4 CORE -> UART1 interface */
2341 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2342         {
2343                 .pa_start       = OMAP3_UART1_BASE,
2344                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2345                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2346         },
2347         { }
2348 };
2349
2350 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2351         .master         = &omap3xxx_l4_core_hwmod,
2352         .slave          = &omap3xxx_uart1_hwmod,
2353         .clk            = "uart1_ick",
2354         .addr           = omap3xxx_uart1_addr_space,
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 /* L4 CORE -> UART2 interface */
2359 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2360         {
2361                 .pa_start       = OMAP3_UART2_BASE,
2362                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2363                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2364         },
2365         { }
2366 };
2367
2368 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2369         .master         = &omap3xxx_l4_core_hwmod,
2370         .slave          = &omap3xxx_uart2_hwmod,
2371         .clk            = "uart2_ick",
2372         .addr           = omap3xxx_uart2_addr_space,
2373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2374 };
2375
2376 /* L4 PER -> UART3 interface */
2377 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2378         {
2379                 .pa_start       = OMAP3_UART3_BASE,
2380                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2381                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2382         },
2383         { }
2384 };
2385
2386 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2387         .master         = &omap3xxx_l4_per_hwmod,
2388         .slave          = &omap3xxx_uart3_hwmod,
2389         .clk            = "uart3_ick",
2390         .addr           = omap3xxx_uart3_addr_space,
2391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2392 };
2393
2394 /* L4 PER -> UART4 interface */
2395 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2396         {
2397                 .pa_start       = OMAP3_UART4_BASE,
2398                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2399                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2400         },
2401         { }
2402 };
2403
2404 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2405         .master         = &omap3xxx_l4_per_hwmod,
2406         .slave          = &omap36xx_uart4_hwmod,
2407         .clk            = "uart4_ick",
2408         .addr           = omap36xx_uart4_addr_space,
2409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* AM35xx: L4 CORE -> UART4 interface */
2413 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2414         {
2415                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2416                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2417                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2418         },
2419         { }
2420 };
2421
2422 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2423         .master         = &omap3xxx_l4_core_hwmod,
2424         .slave          = &am35xx_uart4_hwmod,
2425         .clk            = "uart4_ick",
2426         .addr           = am35xx_uart4_addr_space,
2427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2428 };
2429
2430 /* L4 CORE -> I2C1 interface */
2431 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2432         .master         = &omap3xxx_l4_core_hwmod,
2433         .slave          = &omap3xxx_i2c1_hwmod,
2434         .clk            = "i2c1_ick",
2435         .addr           = omap2_i2c1_addr_space,
2436         .fw = {
2437                 .omap2 = {
2438                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2439                         .l4_prot_group = 7,
2440                         .flags  = OMAP_FIREWALL_L4,
2441                 }
2442         },
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 /* L4 CORE -> I2C2 interface */
2447 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2448         .master         = &omap3xxx_l4_core_hwmod,
2449         .slave          = &omap3xxx_i2c2_hwmod,
2450         .clk            = "i2c2_ick",
2451         .addr           = omap2_i2c2_addr_space,
2452         .fw = {
2453                 .omap2 = {
2454                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2455                         .l4_prot_group = 7,
2456                         .flags = OMAP_FIREWALL_L4,
2457                 }
2458         },
2459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 /* L4 CORE -> I2C3 interface */
2463 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2464         {
2465                 .pa_start       = 0x48060000,
2466                 .pa_end         = 0x48060000 + SZ_128 - 1,
2467                 .flags          = ADDR_TYPE_RT,
2468         },
2469         { }
2470 };
2471
2472 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2473         .master         = &omap3xxx_l4_core_hwmod,
2474         .slave          = &omap3xxx_i2c3_hwmod,
2475         .clk            = "i2c3_ick",
2476         .addr           = omap3xxx_i2c3_addr_space,
2477         .fw = {
2478                 .omap2 = {
2479                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2480                         .l4_prot_group = 7,
2481                         .flags = OMAP_FIREWALL_L4,
2482                 }
2483         },
2484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2485 };
2486
2487 /* L4 CORE -> SR1 interface */
2488 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2489         {
2490                 .pa_start       = OMAP34XX_SR1_BASE,
2491                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2492                 .flags          = ADDR_TYPE_RT,
2493         },
2494         { }
2495 };
2496
2497 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2498         .master         = &omap3xxx_l4_core_hwmod,
2499         .slave          = &omap34xx_sr1_hwmod,
2500         .clk            = "sr_l4_ick",
2501         .addr           = omap3_sr1_addr_space,
2502         .user           = OCP_USER_MPU,
2503 };
2504
2505 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2506         .master         = &omap3xxx_l4_core_hwmod,
2507         .slave          = &omap36xx_sr1_hwmod,
2508         .clk            = "sr_l4_ick",
2509         .addr           = omap3_sr1_addr_space,
2510         .user           = OCP_USER_MPU,
2511 };
2512
2513 /* L4 CORE -> SR1 interface */
2514 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2515         {
2516                 .pa_start       = OMAP34XX_SR2_BASE,
2517                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2518                 .flags          = ADDR_TYPE_RT,
2519         },
2520         { }
2521 };
2522
2523 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2524         .master         = &omap3xxx_l4_core_hwmod,
2525         .slave          = &omap34xx_sr2_hwmod,
2526         .clk            = "sr_l4_ick",
2527         .addr           = omap3_sr2_addr_space,
2528         .user           = OCP_USER_MPU,
2529 };
2530
2531 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2532         .master         = &omap3xxx_l4_core_hwmod,
2533         .slave          = &omap36xx_sr2_hwmod,
2534         .clk            = "sr_l4_ick",
2535         .addr           = omap3_sr2_addr_space,
2536         .user           = OCP_USER_MPU,
2537 };
2538
2539 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2540         {
2541                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2542                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2543                 .flags          = ADDR_TYPE_RT
2544         },
2545         { }
2546 };
2547
2548 /* l4_core -> usbhsotg  */
2549 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2550         .master         = &omap3xxx_l4_core_hwmod,
2551         .slave          = &omap3xxx_usbhsotg_hwmod,
2552         .clk            = "l4_ick",
2553         .addr           = omap3xxx_usbhsotg_addrs,
2554         .user           = OCP_USER_MPU,
2555 };
2556
2557 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2558         {
2559                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2560                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2561                 .flags          = ADDR_TYPE_RT
2562         },
2563         { }
2564 };
2565
2566 /* l4_core -> usbhsotg  */
2567 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2568         .master         = &omap3xxx_l4_core_hwmod,
2569         .slave          = &am35xx_usbhsotg_hwmod,
2570         .clk            = "hsotgusb_ick",
2571         .addr           = am35xx_usbhsotg_addrs,
2572         .user           = OCP_USER_MPU,
2573 };
2574
2575 /* L4_WKUP -> L4_SEC interface */
2576 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2577         .master = &omap3xxx_l4_wkup_hwmod,
2578         .slave  = &omap3xxx_l4_sec_hwmod,
2579         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2580 };
2581
2582 /* IVA2 <- L3 interface */
2583 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2584         .master         = &omap3xxx_l3_main_hwmod,
2585         .slave          = &omap3xxx_iva_hwmod,
2586         .clk            = "core_l3_ick",
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2591         {
2592                 .pa_start       = 0x48318000,
2593                 .pa_end         = 0x48318000 + SZ_1K - 1,
2594                 .flags          = ADDR_TYPE_RT
2595         },
2596         { }
2597 };
2598
2599 /* l4_wkup -> timer1 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2601         .master         = &omap3xxx_l4_wkup_hwmod,
2602         .slave          = &omap3xxx_timer1_hwmod,
2603         .clk            = "gpt1_ick",
2604         .addr           = omap3xxx_timer1_addrs,
2605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2609         {
2610                 .pa_start       = 0x49032000,
2611                 .pa_end         = 0x49032000 + SZ_1K - 1,
2612                 .flags          = ADDR_TYPE_RT
2613         },
2614         { }
2615 };
2616
2617 /* l4_per -> timer2 */
2618 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2619         .master         = &omap3xxx_l4_per_hwmod,
2620         .slave          = &omap3xxx_timer2_hwmod,
2621         .clk            = "gpt2_ick",
2622         .addr           = omap3xxx_timer2_addrs,
2623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2624 };
2625
2626 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2627         {
2628                 .pa_start       = 0x49034000,
2629                 .pa_end         = 0x49034000 + SZ_1K - 1,
2630                 .flags          = ADDR_TYPE_RT
2631         },
2632         { }
2633 };
2634
2635 /* l4_per -> timer3 */
2636 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2637         .master         = &omap3xxx_l4_per_hwmod,
2638         .slave          = &omap3xxx_timer3_hwmod,
2639         .clk            = "gpt3_ick",
2640         .addr           = omap3xxx_timer3_addrs,
2641         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2642 };
2643
2644 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2645         {
2646                 .pa_start       = 0x49036000,
2647                 .pa_end         = 0x49036000 + SZ_1K - 1,
2648                 .flags          = ADDR_TYPE_RT
2649         },
2650         { }
2651 };
2652
2653 /* l4_per -> timer4 */
2654 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2655         .master         = &omap3xxx_l4_per_hwmod,
2656         .slave          = &omap3xxx_timer4_hwmod,
2657         .clk            = "gpt4_ick",
2658         .addr           = omap3xxx_timer4_addrs,
2659         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2660 };
2661
2662 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2663         {
2664                 .pa_start       = 0x49038000,
2665                 .pa_end         = 0x49038000 + SZ_1K - 1,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668         { }
2669 };
2670
2671 /* l4_per -> timer5 */
2672 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2673         .master         = &omap3xxx_l4_per_hwmod,
2674         .slave          = &omap3xxx_timer5_hwmod,
2675         .clk            = "gpt5_ick",
2676         .addr           = omap3xxx_timer5_addrs,
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2681         {
2682                 .pa_start       = 0x4903A000,
2683                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2684                 .flags          = ADDR_TYPE_RT
2685         },
2686         { }
2687 };
2688
2689 /* l4_per -> timer6 */
2690 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2691         .master         = &omap3xxx_l4_per_hwmod,
2692         .slave          = &omap3xxx_timer6_hwmod,
2693         .clk            = "gpt6_ick",
2694         .addr           = omap3xxx_timer6_addrs,
2695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2696 };
2697
2698 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2699         {
2700                 .pa_start       = 0x4903C000,
2701                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2702                 .flags          = ADDR_TYPE_RT
2703         },
2704         { }
2705 };
2706
2707 /* l4_per -> timer7 */
2708 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2709         .master         = &omap3xxx_l4_per_hwmod,
2710         .slave          = &omap3xxx_timer7_hwmod,
2711         .clk            = "gpt7_ick",
2712         .addr           = omap3xxx_timer7_addrs,
2713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2714 };
2715
2716 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2717         {
2718                 .pa_start       = 0x4903E000,
2719                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2720                 .flags          = ADDR_TYPE_RT
2721         },
2722         { }
2723 };
2724
2725 /* l4_per -> timer8 */
2726 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2727         .master         = &omap3xxx_l4_per_hwmod,
2728         .slave          = &omap3xxx_timer8_hwmod,
2729         .clk            = "gpt8_ick",
2730         .addr           = omap3xxx_timer8_addrs,
2731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2733
2734 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2735         {
2736                 .pa_start       = 0x49040000,
2737                 .pa_end         = 0x49040000 + SZ_1K - 1,
2738                 .flags          = ADDR_TYPE_RT
2739         },
2740         { }
2741 };
2742
2743 /* l4_per -> timer9 */
2744 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2745         .master         = &omap3xxx_l4_per_hwmod,
2746         .slave          = &omap3xxx_timer9_hwmod,
2747         .clk            = "gpt9_ick",
2748         .addr           = omap3xxx_timer9_addrs,
2749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2750 };
2751
2752 /* l4_core -> timer10 */
2753 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2754         .master         = &omap3xxx_l4_core_hwmod,
2755         .slave          = &omap3xxx_timer10_hwmod,
2756         .clk            = "gpt10_ick",
2757         .addr           = omap2_timer10_addrs,
2758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2759 };
2760
2761 /* l4_core -> timer11 */
2762 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2763         .master         = &omap3xxx_l4_core_hwmod,
2764         .slave          = &omap3xxx_timer11_hwmod,
2765         .clk            = "gpt11_ick",
2766         .addr           = omap2_timer11_addrs,
2767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2768 };
2769
2770 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2771         {
2772                 .pa_start       = 0x48304000,
2773                 .pa_end         = 0x48304000 + SZ_1K - 1,
2774                 .flags          = ADDR_TYPE_RT
2775         },
2776         { }
2777 };
2778
2779 /* l4_core -> timer12 */
2780 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2781         .master         = &omap3xxx_l4_sec_hwmod,
2782         .slave          = &omap3xxx_timer12_hwmod,
2783         .clk            = "gpt12_ick",
2784         .addr           = omap3xxx_timer12_addrs,
2785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2786 };
2787
2788 /* l4_wkup -> wd_timer2 */
2789 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2790         {
2791                 .pa_start       = 0x48314000,
2792                 .pa_end         = 0x4831407f,
2793                 .flags          = ADDR_TYPE_RT
2794         },
2795         { }
2796 };
2797
2798 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2799         .master         = &omap3xxx_l4_wkup_hwmod,
2800         .slave          = &omap3xxx_wd_timer2_hwmod,
2801         .clk            = "wdt2_ick",
2802         .addr           = omap3xxx_wd_timer2_addrs,
2803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2804 };
2805
2806 /* l4_core -> dss */
2807 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2808         .master         = &omap3xxx_l4_core_hwmod,
2809         .slave          = &omap3430es1_dss_core_hwmod,
2810         .clk            = "dss_ick",
2811         .addr           = omap2_dss_addrs,
2812         .fw = {
2813                 .omap2 = {
2814                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2815                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2816                         .flags  = OMAP_FIREWALL_L4,
2817                 }
2818         },
2819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2820 };
2821
2822 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2823         .master         = &omap3xxx_l4_core_hwmod,
2824         .slave          = &omap3xxx_dss_core_hwmod,
2825         .clk            = "dss_ick",
2826         .addr           = omap2_dss_addrs,
2827         .fw = {
2828                 .omap2 = {
2829                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2830                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2831                         .flags  = OMAP_FIREWALL_L4,
2832                 }
2833         },
2834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2835 };
2836
2837 /* l4_core -> dss_dispc */
2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2839         .master         = &omap3xxx_l4_core_hwmod,
2840         .slave          = &omap3xxx_dss_dispc_hwmod,
2841         .clk            = "dss_ick",
2842         .addr           = omap2_dss_dispc_addrs,
2843         .fw = {
2844                 .omap2 = {
2845                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2846                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2847                         .flags  = OMAP_FIREWALL_L4,
2848                 }
2849         },
2850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2851 };
2852
2853 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2854         {
2855                 .pa_start       = 0x4804FC00,
2856                 .pa_end         = 0x4804FFFF,
2857                 .flags          = ADDR_TYPE_RT
2858         },
2859         { }
2860 };
2861
2862 /* l4_core -> dss_dsi1 */
2863 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2864         .master         = &omap3xxx_l4_core_hwmod,
2865         .slave          = &omap3xxx_dss_dsi1_hwmod,
2866         .clk            = "dss_ick",
2867         .addr           = omap3xxx_dss_dsi1_addrs,
2868         .fw = {
2869                 .omap2 = {
2870                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2871                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2872                         .flags  = OMAP_FIREWALL_L4,
2873                 }
2874         },
2875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2876 };
2877
2878 /* l4_core -> dss_rfbi */
2879 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2880         .master         = &omap3xxx_l4_core_hwmod,
2881         .slave          = &omap3xxx_dss_rfbi_hwmod,
2882         .clk            = "dss_ick",
2883         .addr           = omap2_dss_rfbi_addrs,
2884         .fw = {
2885                 .omap2 = {
2886                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2887                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2888                         .flags  = OMAP_FIREWALL_L4,
2889                 }
2890         },
2891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893
2894 /* l4_core -> dss_venc */
2895 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2896         .master         = &omap3xxx_l4_core_hwmod,
2897         .slave          = &omap3xxx_dss_venc_hwmod,
2898         .clk            = "dss_ick",
2899         .addr           = omap2_dss_venc_addrs,
2900         .fw = {
2901                 .omap2 = {
2902                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2903                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2904                         .flags  = OMAP_FIREWALL_L4,
2905                 }
2906         },
2907         .flags          = OCPIF_SWSUP_IDLE,
2908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2909 };
2910
2911 /* l4_wkup -> gpio1 */
2912 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2913         {
2914                 .pa_start       = 0x48310000,
2915                 .pa_end         = 0x483101ff,
2916                 .flags          = ADDR_TYPE_RT
2917         },
2918         { }
2919 };
2920
2921 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2922         .master         = &omap3xxx_l4_wkup_hwmod,
2923         .slave          = &omap3xxx_gpio1_hwmod,
2924         .addr           = omap3xxx_gpio1_addrs,
2925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2926 };
2927
2928 /* l4_per -> gpio2 */
2929 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2930         {
2931                 .pa_start       = 0x49050000,
2932                 .pa_end         = 0x490501ff,
2933                 .flags          = ADDR_TYPE_RT
2934         },
2935         { }
2936 };
2937
2938 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2939         .master         = &omap3xxx_l4_per_hwmod,
2940         .slave          = &omap3xxx_gpio2_hwmod,
2941         .addr           = omap3xxx_gpio2_addrs,
2942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2943 };
2944
2945 /* l4_per -> gpio3 */
2946 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2947         {
2948                 .pa_start       = 0x49052000,
2949                 .pa_end         = 0x490521ff,
2950                 .flags          = ADDR_TYPE_RT
2951         },
2952         { }
2953 };
2954
2955 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2956         .master         = &omap3xxx_l4_per_hwmod,
2957         .slave          = &omap3xxx_gpio3_hwmod,
2958         .addr           = omap3xxx_gpio3_addrs,
2959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2960 };
2961
2962 /*
2963  * 'mmu' class
2964  * The memory management unit performs virtual to physical address translation
2965  * for its requestors.
2966  */
2967
2968 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2969         .rev_offs       = 0x000,
2970         .sysc_offs      = 0x010,
2971         .syss_offs      = 0x014,
2972         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2973                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2974         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2975         .sysc_fields    = &omap_hwmod_sysc_type1,
2976 };
2977
2978 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2979         .name = "mmu",
2980         .sysc = &mmu_sysc,
2981 };
2982
2983 /* mmu isp */
2984
2985 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2986         .da_start       = 0x0,
2987         .da_end         = 0xfffff000,
2988         .nr_tlb_entries = 8,
2989 };
2990
2991 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2992 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2993         { .irq = 24 },
2994         { .irq = -1 }
2995 };
2996
2997 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2998         {
2999                 .pa_start       = 0x480bd400,
3000                 .pa_end         = 0x480bd47f,
3001                 .flags          = ADDR_TYPE_RT,
3002         },
3003         { }
3004 };
3005
3006 /* l4_core -> mmu isp */
3007 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3008         .master         = &omap3xxx_l4_core_hwmod,
3009         .slave          = &omap3xxx_mmu_isp_hwmod,
3010         .addr           = omap3xxx_mmu_isp_addrs,
3011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3012 };
3013
3014 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3015         .name           = "mmu_isp",
3016         .class          = &omap3xxx_mmu_hwmod_class,
3017         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3018         .main_clk       = "cam_ick",
3019         .dev_attr       = &mmu_isp_dev_attr,
3020         .flags          = HWMOD_NO_IDLEST,
3021 };
3022
3023 #ifdef CONFIG_OMAP_IOMMU_IVA2
3024
3025 /* mmu iva */
3026
3027 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3028         .da_start       = 0x11000000,
3029         .da_end         = 0xfffff000,
3030         .nr_tlb_entries = 32,
3031 };
3032
3033 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3034 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3035         { .irq = 28 },
3036         { .irq = -1 }
3037 };
3038
3039 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3040         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3041 };
3042
3043 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3044         {
3045                 .pa_start       = 0x5d000000,
3046                 .pa_end         = 0x5d00007f,
3047                 .flags          = ADDR_TYPE_RT,
3048         },
3049         { }
3050 };
3051
3052 /* l3_main -> iva mmu */
3053 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3054         .master         = &omap3xxx_l3_main_hwmod,
3055         .slave          = &omap3xxx_mmu_iva_hwmod,
3056         .addr           = omap3xxx_mmu_iva_addrs,
3057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3058 };
3059
3060 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3061         .name           = "mmu_iva",
3062         .class          = &omap3xxx_mmu_hwmod_class,
3063         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3064         .rst_lines      = omap3xxx_mmu_iva_resets,
3065         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3066         .main_clk       = "iva2_ck",
3067         .prcm = {
3068                 .omap2 = {
3069                         .module_offs = OMAP3430_IVA2_MOD,
3070                 },
3071         },
3072         .dev_attr       = &mmu_iva_dev_attr,
3073         .flags          = HWMOD_NO_IDLEST,
3074 };
3075
3076 #endif
3077
3078 /* l4_per -> gpio4 */
3079 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3080         {
3081                 .pa_start       = 0x49054000,
3082                 .pa_end         = 0x490541ff,
3083                 .flags          = ADDR_TYPE_RT
3084         },
3085         { }
3086 };
3087
3088 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3089         .master         = &omap3xxx_l4_per_hwmod,
3090         .slave          = &omap3xxx_gpio4_hwmod,
3091         .addr           = omap3xxx_gpio4_addrs,
3092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3093 };
3094
3095 /* l4_per -> gpio5 */
3096 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3097         {
3098                 .pa_start       = 0x49056000,
3099                 .pa_end         = 0x490561ff,
3100                 .flags          = ADDR_TYPE_RT
3101         },
3102         { }
3103 };
3104
3105 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3106         .master         = &omap3xxx_l4_per_hwmod,
3107         .slave          = &omap3xxx_gpio5_hwmod,
3108         .addr           = omap3xxx_gpio5_addrs,
3109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3110 };
3111
3112 /* l4_per -> gpio6 */
3113 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3114         {
3115                 .pa_start       = 0x49058000,
3116                 .pa_end         = 0x490581ff,
3117                 .flags          = ADDR_TYPE_RT
3118         },
3119         { }
3120 };
3121
3122 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3123         .master         = &omap3xxx_l4_per_hwmod,
3124         .slave          = &omap3xxx_gpio6_hwmod,
3125         .addr           = omap3xxx_gpio6_addrs,
3126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3127 };
3128
3129 /* dma_system -> L3 */
3130 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3131         .master         = &omap3xxx_dma_system_hwmod,
3132         .slave          = &omap3xxx_l3_main_hwmod,
3133         .clk            = "core_l3_ick",
3134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3135 };
3136
3137 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3138         {
3139                 .pa_start       = 0x48056000,
3140                 .pa_end         = 0x48056fff,
3141                 .flags          = ADDR_TYPE_RT
3142         },
3143         { }
3144 };
3145
3146 /* l4_cfg -> dma_system */
3147 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3148         .master         = &omap3xxx_l4_core_hwmod,
3149         .slave          = &omap3xxx_dma_system_hwmod,
3150         .clk            = "core_l4_ick",
3151         .addr           = omap3xxx_dma_system_addrs,
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3156         {
3157                 .name           = "mpu",
3158                 .pa_start       = 0x48074000,
3159                 .pa_end         = 0x480740ff,
3160                 .flags          = ADDR_TYPE_RT
3161         },
3162         { }
3163 };
3164
3165 /* l4_core -> mcbsp1 */
3166 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3167         .master         = &omap3xxx_l4_core_hwmod,
3168         .slave          = &omap3xxx_mcbsp1_hwmod,
3169         .clk            = "mcbsp1_ick",
3170         .addr           = omap3xxx_mcbsp1_addrs,
3171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3172 };
3173
3174 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3175         {
3176                 .name           = "mpu",
3177                 .pa_start       = 0x49022000,
3178                 .pa_end         = 0x490220ff,
3179                 .flags          = ADDR_TYPE_RT
3180         },
3181         { }
3182 };
3183
3184 /* l4_per -> mcbsp2 */
3185 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3186         .master         = &omap3xxx_l4_per_hwmod,
3187         .slave          = &omap3xxx_mcbsp2_hwmod,
3188         .clk            = "mcbsp2_ick",
3189         .addr           = omap3xxx_mcbsp2_addrs,
3190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3194         {
3195                 .name           = "mpu",
3196                 .pa_start       = 0x49024000,
3197                 .pa_end         = 0x490240ff,
3198                 .flags          = ADDR_TYPE_RT
3199         },
3200         { }
3201 };
3202
3203 /* l4_per -> mcbsp3 */
3204 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3205         .master         = &omap3xxx_l4_per_hwmod,
3206         .slave          = &omap3xxx_mcbsp3_hwmod,
3207         .clk            = "mcbsp3_ick",
3208         .addr           = omap3xxx_mcbsp3_addrs,
3209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3211
3212 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3213         {
3214                 .name           = "mpu",
3215                 .pa_start       = 0x49026000,
3216                 .pa_end         = 0x490260ff,
3217                 .flags          = ADDR_TYPE_RT
3218         },
3219         { }
3220 };
3221
3222 /* l4_per -> mcbsp4 */
3223 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3224         .master         = &omap3xxx_l4_per_hwmod,
3225         .slave          = &omap3xxx_mcbsp4_hwmod,
3226         .clk            = "mcbsp4_ick",
3227         .addr           = omap3xxx_mcbsp4_addrs,
3228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3229 };
3230
3231 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3232         {
3233                 .name           = "mpu",
3234                 .pa_start       = 0x48096000,
3235                 .pa_end         = 0x480960ff,
3236                 .flags          = ADDR_TYPE_RT
3237         },
3238         { }
3239 };
3240
3241 /* l4_core -> mcbsp5 */
3242 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3243         .master         = &omap3xxx_l4_core_hwmod,
3244         .slave          = &omap3xxx_mcbsp5_hwmod,
3245         .clk            = "mcbsp5_ick",
3246         .addr           = omap3xxx_mcbsp5_addrs,
3247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3248 };
3249
3250 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3251         {
3252                 .name           = "sidetone",
3253                 .pa_start       = 0x49028000,
3254                 .pa_end         = 0x490280ff,
3255                 .flags          = ADDR_TYPE_RT
3256         },
3257         { }
3258 };
3259
3260 /* l4_per -> mcbsp2_sidetone */
3261 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3262         .master         = &omap3xxx_l4_per_hwmod,
3263         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3264         .clk            = "mcbsp2_ick",
3265         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3266         .user           = OCP_USER_MPU,
3267 };
3268
3269 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3270         {
3271                 .name           = "sidetone",
3272                 .pa_start       = 0x4902A000,
3273                 .pa_end         = 0x4902A0ff,
3274                 .flags          = ADDR_TYPE_RT
3275         },
3276         { }
3277 };
3278
3279 /* l4_per -> mcbsp3_sidetone */
3280 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3281         .master         = &omap3xxx_l4_per_hwmod,
3282         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3283         .clk            = "mcbsp3_ick",
3284         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3285         .user           = OCP_USER_MPU,
3286 };
3287
3288 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3289         {
3290                 .pa_start       = 0x48094000,
3291                 .pa_end         = 0x480941ff,
3292                 .flags          = ADDR_TYPE_RT,
3293         },
3294         { }
3295 };
3296
3297 /* l4_core -> mailbox */
3298 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3299         .master         = &omap3xxx_l4_core_hwmod,
3300         .slave          = &omap3xxx_mailbox_hwmod,
3301         .addr           = omap3xxx_mailbox_addrs,
3302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3303 };
3304
3305 /* l4 core -> mcspi1 interface */
3306 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3307         .master         = &omap3xxx_l4_core_hwmod,
3308         .slave          = &omap34xx_mcspi1,
3309         .clk            = "mcspi1_ick",
3310         .addr           = omap2_mcspi1_addr_space,
3311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4 core -> mcspi2 interface */
3315 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3316         .master         = &omap3xxx_l4_core_hwmod,
3317         .slave          = &omap34xx_mcspi2,
3318         .clk            = "mcspi2_ick",
3319         .addr           = omap2_mcspi2_addr_space,
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4 core -> mcspi3 interface */
3324 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3325         .master         = &omap3xxx_l4_core_hwmod,
3326         .slave          = &omap34xx_mcspi3,
3327         .clk            = "mcspi3_ick",
3328         .addr           = omap2430_mcspi3_addr_space,
3329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3330 };
3331
3332 /* l4 core -> mcspi4 interface */
3333 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3334         {
3335                 .pa_start       = 0x480ba000,
3336                 .pa_end         = 0x480ba0ff,
3337                 .flags          = ADDR_TYPE_RT,
3338         },
3339         { }
3340 };
3341
3342 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3343         .master         = &omap3xxx_l4_core_hwmod,
3344         .slave          = &omap34xx_mcspi4,
3345         .clk            = "mcspi4_ick",
3346         .addr           = omap34xx_mcspi4_addr_space,
3347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3348 };
3349
3350 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3351         .master         = &omap3xxx_usb_host_hs_hwmod,
3352         .slave          = &omap3xxx_l3_main_hwmod,
3353         .clk            = "core_l3_ick",
3354         .user           = OCP_USER_MPU,
3355 };
3356
3357 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3358         {
3359                 .name           = "uhh",
3360                 .pa_start       = 0x48064000,
3361                 .pa_end         = 0x480643ff,
3362                 .flags          = ADDR_TYPE_RT
3363         },
3364         {
3365                 .name           = "ohci",
3366                 .pa_start       = 0x48064400,
3367                 .pa_end         = 0x480647ff,
3368         },
3369         {
3370                 .name           = "ehci",
3371                 .pa_start       = 0x48064800,
3372                 .pa_end         = 0x48064cff,
3373         },
3374         {}
3375 };
3376
3377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3378         .master         = &omap3xxx_l4_core_hwmod,
3379         .slave          = &omap3xxx_usb_host_hs_hwmod,
3380         .clk            = "usbhost_ick",
3381         .addr           = omap3xxx_usb_host_hs_addrs,
3382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3383 };
3384
3385 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3386         {
3387                 .name           = "tll",
3388                 .pa_start       = 0x48062000,
3389                 .pa_end         = 0x48062fff,
3390                 .flags          = ADDR_TYPE_RT
3391         },
3392         {}
3393 };
3394
3395 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3396         .master         = &omap3xxx_l4_core_hwmod,
3397         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3398         .clk            = "usbtll_ick",
3399         .addr           = omap3xxx_usb_tll_hs_addrs,
3400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3401 };
3402
3403 /* l4_core -> hdq1w interface */
3404 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3405         .master         = &omap3xxx_l4_core_hwmod,
3406         .slave          = &omap3xxx_hdq1w_hwmod,
3407         .clk            = "hdq_ick",
3408         .addr           = omap2_hdq1w_addr_space,
3409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3410         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3411 };
3412
3413 /* l4_wkup -> 32ksync_counter */
3414 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3415         {
3416                 .pa_start       = 0x48320000,
3417                 .pa_end         = 0x4832001f,
3418                 .flags          = ADDR_TYPE_RT
3419         },
3420         { }
3421 };
3422
3423 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3424         {
3425                 .pa_start       = 0x6e000000,
3426                 .pa_end         = 0x6e000fff,
3427                 .flags          = ADDR_TYPE_RT
3428         },
3429         { }
3430 };
3431
3432 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3433         .master         = &omap3xxx_l4_wkup_hwmod,
3434         .slave          = &omap3xxx_counter_32k_hwmod,
3435         .clk            = "omap_32ksync_ick",
3436         .addr           = omap3xxx_counter_32k_addrs,
3437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3438 };
3439
3440 /* am35xx has Davinci MDIO & EMAC */
3441 static struct omap_hwmod_class am35xx_mdio_class = {
3442         .name = "davinci_mdio",
3443 };
3444
3445 static struct omap_hwmod am35xx_mdio_hwmod = {
3446         .name           = "davinci_mdio",
3447         .class          = &am35xx_mdio_class,
3448         .flags          = HWMOD_NO_IDLEST,
3449 };
3450
3451 /*
3452  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3453  * but this will probably require some additional hwmod core support,
3454  * so is left as a future to-do item.
3455  */
3456 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3457         .master         = &am35xx_mdio_hwmod,
3458         .slave          = &omap3xxx_l3_main_hwmod,
3459         .clk            = "emac_fck",
3460         .user           = OCP_USER_MPU,
3461 };
3462
3463 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3464         {
3465                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3466                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3467                 .flags          = ADDR_TYPE_RT,
3468         },
3469         { }
3470 };
3471
3472 /* l4_core -> davinci mdio  */
3473 /*
3474  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3475  * but this will probably require some additional hwmod core support,
3476  * so is left as a future to-do item.
3477  */
3478 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3479         .master         = &omap3xxx_l4_core_hwmod,
3480         .slave          = &am35xx_mdio_hwmod,
3481         .clk            = "emac_fck",
3482         .addr           = am35xx_mdio_addrs,
3483         .user           = OCP_USER_MPU,
3484 };
3485
3486 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3487         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3488         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3489         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3490         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3491         { .irq = -1 },
3492 };
3493
3494 static struct omap_hwmod_class am35xx_emac_class = {
3495         .name = "davinci_emac",
3496 };
3497
3498 static struct omap_hwmod am35xx_emac_hwmod = {
3499         .name           = "davinci_emac",
3500         .mpu_irqs       = am35xx_emac_mpu_irqs,
3501         .class          = &am35xx_emac_class,
3502         .flags          = HWMOD_NO_IDLEST,
3503 };
3504
3505 /* l3_core -> davinci emac interface */
3506 /*
3507  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3508  * but this will probably require some additional hwmod core support,
3509  * so is left as a future to-do item.
3510  */
3511 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3512         .master         = &am35xx_emac_hwmod,
3513         .slave          = &omap3xxx_l3_main_hwmod,
3514         .clk            = "emac_ick",
3515         .user           = OCP_USER_MPU,
3516 };
3517
3518 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3519         {
3520                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3521                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3522                 .flags          = ADDR_TYPE_RT,
3523         },
3524         { }
3525 };
3526
3527 /* l4_core -> davinci emac  */
3528 /*
3529  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3530  * but this will probably require some additional hwmod core support,
3531  * so is left as a future to-do item.
3532  */
3533 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3534         .master         = &omap3xxx_l4_core_hwmod,
3535         .slave          = &am35xx_emac_hwmod,
3536         .clk            = "emac_ick",
3537         .addr           = am35xx_emac_addrs,
3538         .user           = OCP_USER_MPU,
3539 };
3540
3541 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3542         .master         = &omap3xxx_l3_main_hwmod,
3543         .slave          = &omap3xxx_gpmc_hwmod,
3544         .clk            = "core_l3_ick",
3545         .addr           = omap3xxx_gpmc_addrs,
3546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3547 };
3548
3549 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3550         &omap3xxx_l3_main__l4_core,
3551         &omap3xxx_l3_main__l4_per,
3552         &omap3xxx_mpu__l3_main,
3553         &omap3xxx_l3_main__l4_debugss,
3554         &omap3xxx_l4_core__l4_wkup,
3555         &omap3xxx_l4_core__mmc3,
3556         &omap3_l4_core__uart1,
3557         &omap3_l4_core__uart2,
3558         &omap3_l4_per__uart3,
3559         &omap3_l4_core__i2c1,
3560         &omap3_l4_core__i2c2,
3561         &omap3_l4_core__i2c3,
3562         &omap3xxx_l4_wkup__l4_sec,
3563         &omap3xxx_l4_wkup__timer1,
3564         &omap3xxx_l4_per__timer2,
3565         &omap3xxx_l4_per__timer3,
3566         &omap3xxx_l4_per__timer4,
3567         &omap3xxx_l4_per__timer5,
3568         &omap3xxx_l4_per__timer6,
3569         &omap3xxx_l4_per__timer7,
3570         &omap3xxx_l4_per__timer8,
3571         &omap3xxx_l4_per__timer9,
3572         &omap3xxx_l4_core__timer10,
3573         &omap3xxx_l4_core__timer11,
3574         &omap3xxx_l4_wkup__wd_timer2,
3575         &omap3xxx_l4_wkup__gpio1,
3576         &omap3xxx_l4_per__gpio2,
3577         &omap3xxx_l4_per__gpio3,
3578         &omap3xxx_l4_per__gpio4,
3579         &omap3xxx_l4_per__gpio5,
3580         &omap3xxx_l4_per__gpio6,
3581         &omap3xxx_dma_system__l3,
3582         &omap3xxx_l4_core__dma_system,
3583         &omap3xxx_l4_core__mcbsp1,
3584         &omap3xxx_l4_per__mcbsp2,
3585         &omap3xxx_l4_per__mcbsp3,
3586         &omap3xxx_l4_per__mcbsp4,
3587         &omap3xxx_l4_core__mcbsp5,
3588         &omap3xxx_l4_per__mcbsp2_sidetone,
3589         &omap3xxx_l4_per__mcbsp3_sidetone,
3590         &omap34xx_l4_core__mcspi1,
3591         &omap34xx_l4_core__mcspi2,
3592         &omap34xx_l4_core__mcspi3,
3593         &omap34xx_l4_core__mcspi4,
3594         &omap3xxx_l4_wkup__counter_32k,
3595         &omap3xxx_l3_main__gpmc,
3596         NULL,
3597 };
3598
3599 /* GP-only hwmod links */
3600 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3601         &omap3xxx_l4_sec__timer12,
3602         NULL
3603 };
3604
3605 /* 3430ES1-only hwmod links */
3606 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3607         &omap3430es1_dss__l3,
3608         &omap3430es1_l4_core__dss,
3609         NULL
3610 };
3611
3612 /* 3430ES2+-only hwmod links */
3613 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3614         &omap3xxx_dss__l3,
3615         &omap3xxx_l4_core__dss,
3616         &omap3xxx_usbhsotg__l3,
3617         &omap3xxx_l4_core__usbhsotg,
3618         &omap3xxx_usb_host_hs__l3_main_2,
3619         &omap3xxx_l4_core__usb_host_hs,
3620         &omap3xxx_l4_core__usb_tll_hs,
3621         NULL
3622 };
3623
3624 /* <= 3430ES3-only hwmod links */
3625 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3626         &omap3xxx_l4_core__pre_es3_mmc1,
3627         &omap3xxx_l4_core__pre_es3_mmc2,
3628         NULL
3629 };
3630
3631 /* 3430ES3+-only hwmod links */
3632 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3633         &omap3xxx_l4_core__es3plus_mmc1,
3634         &omap3xxx_l4_core__es3plus_mmc2,
3635         NULL
3636 };
3637
3638 /* 34xx-only hwmod links (all ES revisions) */
3639 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3640         &omap3xxx_l3__iva,
3641         &omap34xx_l4_core__sr1,
3642         &omap34xx_l4_core__sr2,
3643         &omap3xxx_l4_core__mailbox,
3644         &omap3xxx_l4_core__hdq1w,
3645         &omap3xxx_sad2d__l3,
3646         &omap3xxx_l4_core__mmu_isp,
3647 #ifdef CONFIG_OMAP_IOMMU_IVA2
3648         &omap3xxx_l3_main__mmu_iva,
3649 #endif
3650         NULL
3651 };
3652
3653 /* 36xx-only hwmod links (all ES revisions) */
3654 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3655         &omap3xxx_l3__iva,
3656         &omap36xx_l4_per__uart4,
3657         &omap3xxx_dss__l3,
3658         &omap3xxx_l4_core__dss,
3659         &omap36xx_l4_core__sr1,
3660         &omap36xx_l4_core__sr2,
3661         &omap3xxx_usbhsotg__l3,
3662         &omap3xxx_l4_core__usbhsotg,
3663         &omap3xxx_l4_core__mailbox,
3664         &omap3xxx_usb_host_hs__l3_main_2,
3665         &omap3xxx_l4_core__usb_host_hs,
3666         &omap3xxx_l4_core__usb_tll_hs,
3667         &omap3xxx_l4_core__es3plus_mmc1,
3668         &omap3xxx_l4_core__es3plus_mmc2,
3669         &omap3xxx_l4_core__hdq1w,
3670         &omap3xxx_sad2d__l3,
3671         &omap3xxx_l4_core__mmu_isp,
3672 #ifdef CONFIG_OMAP_IOMMU_IVA2
3673         &omap3xxx_l3_main__mmu_iva,
3674 #endif
3675         NULL
3676 };
3677
3678 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3679         &omap3xxx_dss__l3,
3680         &omap3xxx_l4_core__dss,
3681         &am35xx_usbhsotg__l3,
3682         &am35xx_l4_core__usbhsotg,
3683         &am35xx_l4_core__uart4,
3684         &omap3xxx_usb_host_hs__l3_main_2,
3685         &omap3xxx_l4_core__usb_host_hs,
3686         &omap3xxx_l4_core__usb_tll_hs,
3687         &omap3xxx_l4_core__es3plus_mmc1,
3688         &omap3xxx_l4_core__es3plus_mmc2,
3689         &omap3xxx_l4_core__hdq1w,
3690         &am35xx_mdio__l3,
3691         &am35xx_l4_core__mdio,
3692         &am35xx_emac__l3,
3693         &am35xx_l4_core__emac,
3694         NULL
3695 };
3696
3697 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3698         &omap3xxx_l4_core__dss_dispc,
3699         &omap3xxx_l4_core__dss_dsi1,
3700         &omap3xxx_l4_core__dss_rfbi,
3701         &omap3xxx_l4_core__dss_venc,
3702         NULL
3703 };
3704
3705 int __init omap3xxx_hwmod_init(void)
3706 {
3707         int r;
3708         struct omap_hwmod_ocp_if **h = NULL;
3709         unsigned int rev;
3710
3711         omap_hwmod_init();
3712
3713         /* Register hwmod links common to all OMAP3 */
3714         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3715         if (r < 0)
3716                 return r;
3717
3718         /* Register GP-only hwmod links. */
3719         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3720                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3721                 if (r < 0)
3722                         return r;
3723         }
3724
3725         rev = omap_rev();
3726
3727         /*
3728          * Register hwmod links common to individual OMAP3 families, all
3729          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3730          * All possible revisions should be included in this conditional.
3731          */
3732         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3733             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3734             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3735                 h = omap34xx_hwmod_ocp_ifs;
3736         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3737                 h = am35xx_hwmod_ocp_ifs;
3738         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3739                    rev == OMAP3630_REV_ES1_2) {
3740                 h = omap36xx_hwmod_ocp_ifs;
3741         } else {
3742                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3743                 return -EINVAL;
3744         }
3745
3746         r = omap_hwmod_register_links(h);
3747         if (r < 0)
3748                 return r;
3749
3750         /*
3751          * Register hwmod links specific to certain ES levels of a
3752          * particular family of silicon (e.g., 34xx ES1.0)
3753          */
3754         h = NULL;
3755         if (rev == OMAP3430_REV_ES1_0) {
3756                 h = omap3430es1_hwmod_ocp_ifs;
3757         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3758                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3759                    rev == OMAP3430_REV_ES3_1_2) {
3760                 h = omap3430es2plus_hwmod_ocp_ifs;
3761         }
3762
3763         if (h) {
3764                 r = omap_hwmod_register_links(h);
3765                 if (r < 0)
3766                         return r;
3767         }
3768
3769         h = NULL;
3770         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3771             rev == OMAP3430_REV_ES2_1) {
3772                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3773         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3774                    rev == OMAP3430_REV_ES3_1_2) {
3775                 h = omap3430_es3plus_hwmod_ocp_ifs;
3776         }
3777
3778         if (h)
3779                 r = omap_hwmod_register_links(h);
3780         if (r < 0)
3781                 return r;
3782
3783         /*
3784          * DSS code presumes that dss_core hwmod is handled first,
3785          * _before_ any other DSS related hwmods so register common
3786          * DSS hwmod links last to ensure that dss_core is already
3787          * registered.  Otherwise some change things may happen, for
3788          * ex. if dispc is handled before dss_core and DSS is enabled
3789          * in bootloader DISPC will be reset with outputs enabled
3790          * which sometimes leads to unrecoverable L3 error.  XXX The
3791          * long-term fix to this is to ensure hwmods are set up in
3792          * dependency order in the hwmod core code.
3793          */
3794         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3795
3796         return r;
3797 }