arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'c2c_target_fw' class
  53  * instance(s): c2c_target_fw
  54  */
  55 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  56         .name   = "c2c_target_fw",
  57 };
  58
  59 /* c2c_target_fw */
  60 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  61         .name           = "c2c_target_fw",
  62         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  63         .clkdm_name     = "d2d_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'dmm' class
  74  * instance(s): dmm
  75  */
  76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  77         .name   = "dmm",
  78 };
  79
  80 /* dmm */
  81 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  82         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  83         { .irq = -1 }
  84 };
  85
  86 static struct omap_hwmod omap44xx_dmm_hwmod = {
  87         .name           = "dmm",
  88         .class          = &omap44xx_dmm_hwmod_class,
  89         .clkdm_name     = "l3_emif_clkdm",
  90         .mpu_irqs       = omap44xx_dmm_irqs,
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  94                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  95                 },
  96         },
  97 };
  98
  99 /*
 100  * 'emif_fw' class
 101  * instance(s): emif_fw
 102  */
 103 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 104         .name   = "emif_fw",
 105 };
 106
 107 /* emif_fw */
 108 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 109         .name           = "emif_fw",
 110         .class          = &omap44xx_emif_fw_hwmod_class,
 111         .clkdm_name     = "l3_emif_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /*
 121  * 'l3' class
 122  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 123  */
 124 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 125         .name   = "l3",
 126 };
 127
 128 /* l3_instr */
 129 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 130         .name           = "l3_instr",
 131         .class          = &omap44xx_l3_hwmod_class,
 132         .clkdm_name     = "l3_instr_clkdm",
 133         .prcm = {
 134                 .omap4 = {
 135                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 136                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 137                         .modulemode   = MODULEMODE_HWCTRL,
 138                 },
 139         },
 140 };
 141
 142 /* l3_main_1 */
 143 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 144         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 145         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 146         { .irq = -1 }
 147 };
 148
 149 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 150         .name           = "l3_main_1",
 151         .class          = &omap44xx_l3_hwmod_class,
 152         .clkdm_name     = "l3_1_clkdm",
 153         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 154         .prcm = {
 155                 .omap4 = {
 156                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 157                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 158                 },
 159         },
 160 };
 161
 162 /* l3_main_2 */
 163 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 164         .name           = "l3_main_2",
 165         .class          = &omap44xx_l3_hwmod_class,
 166         .clkdm_name     = "l3_2_clkdm",
 167         .prcm = {
 168                 .omap4 = {
 169                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 170                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 171                 },
 172         },
 173 };
 174
 175 /* l3_main_3 */
 176 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 177         .name           = "l3_main_3",
 178         .class          = &omap44xx_l3_hwmod_class,
 179         .clkdm_name     = "l3_instr_clkdm",
 180         .prcm = {
 181                 .omap4 = {
 182                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 183                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 184                         .modulemode   = MODULEMODE_HWCTRL,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'l4' class
 191  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 192  */
 193 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 194         .name   = "l4",
 195 };
 196
 197 /* l4_abe */
 198 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 199         .name           = "l4_abe",
 200         .class          = &omap44xx_l4_hwmod_class,
 201         .clkdm_name     = "abe_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 205                 },
 206         },
 207 };
 208
 209 /* l4_cfg */
 210 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 211         .name           = "l4_cfg",
 212         .class          = &omap44xx_l4_hwmod_class,
 213         .clkdm_name     = "l4_cfg_clkdm",
 214         .prcm = {
 215                 .omap4 = {
 216                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 217                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 218                 },
 219         },
 220 };
 221
 222 /* l4_per */
 223 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 224         .name           = "l4_per",
 225         .class          = &omap44xx_l4_hwmod_class,
 226         .clkdm_name     = "l4_per_clkdm",
 227         .prcm = {
 228                 .omap4 = {
 229                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 230                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 231                 },
 232         },
 233 };
 234
 235 /* l4_wkup */
 236 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 237         .name           = "l4_wkup",
 238         .class          = &omap44xx_l4_hwmod_class,
 239         .clkdm_name     = "l4_wkup_clkdm",
 240         .prcm = {
 241                 .omap4 = {
 242                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 243                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 244                 },
 245         },
 246 };
 247
 248 /*
 249  * 'mpu_bus' class
 250  * instance(s): mpu_private
 251  */
 252 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 253         .name   = "mpu_bus",
 254 };
 255
 256 /* mpu_private */
 257 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 258         .name           = "mpu_private",
 259         .class          = &omap44xx_mpu_bus_hwmod_class,
 260         .clkdm_name     = "mpuss_clkdm",
 261 };
 262
 263 /*
 264  * 'ocp_wp_noc' class
 265  * instance(s): ocp_wp_noc
 266  */
 267 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 268         .name   = "ocp_wp_noc",
 269 };
 270
 271 /* ocp_wp_noc */
 272 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 273         .name           = "ocp_wp_noc",
 274         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 275         .clkdm_name     = "l3_instr_clkdm",
 276         .prcm = {
 277                 .omap4 = {
 278                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 279                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 280                         .modulemode   = MODULEMODE_HWCTRL,
 281                 },
 282         },
 283 };
 284
 285 /*
 286  * Modules omap_hwmod structures
 287  *
 288  * The following IPs are excluded for the moment because:
 289  * - They do not need an explicit SW control using omap_hwmod API.
 290  * - They still need to be validated with the driver
 291  *   properly adapted to omap_hwmod / omap_device
 292  *
 293  * usim
 294  */
 295
 296 /*
 297  * 'aess' class
 298  * audio engine sub system
 299  */
 300
 301 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 302         .rev_offs       = 0x0000,
 303         .sysc_offs      = 0x0010,
 304         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 305         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 306                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 307                            MSTANDBY_SMART_WKUP),
 308         .sysc_fields    = &omap_hwmod_sysc_type2,
 309 };
 310
 311 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 312         .name   = "aess",
 313         .sysc   = &omap44xx_aess_sysc,
 314 };
 315
 316 /* aess */
 317 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 318         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 319         { .irq = -1 }
 320 };
 321
 322 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 323         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 324         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 325         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 331         { .dma_req = -1 }
 332 };
 333
 334 static struct omap_hwmod omap44xx_aess_hwmod = {
 335         .name           = "aess",
 336         .class          = &omap44xx_aess_hwmod_class,
 337         .clkdm_name     = "abe_clkdm",
 338         .mpu_irqs       = omap44xx_aess_irqs,
 339         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 340         .main_clk       = "aess_fck",
 341         .prcm = {
 342                 .omap4 = {
 343                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 344                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 345                         .modulemode   = MODULEMODE_SWCTRL,
 346                 },
 347         },
 348 };
 349
 350 /*
 351  * 'c2c' class
 352  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 353  * soc
 354  */
 355
 356 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 357         .name   = "c2c",
 358 };
 359
 360 /* c2c */
 361 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 362         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 363         { .irq = -1 }
 364 };
 365
 366 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 367         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 368         { .dma_req = -1 }
 369 };
 370
 371 static struct omap_hwmod omap44xx_c2c_hwmod = {
 372         .name           = "c2c",
 373         .class          = &omap44xx_c2c_hwmod_class,
 374         .clkdm_name     = "d2d_clkdm",
 375         .mpu_irqs       = omap44xx_c2c_irqs,
 376         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 377         .prcm = {
 378                 .omap4 = {
 379                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 380                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 381                 },
 382         },
 383 };
 384
 385 /*
 386  * 'counter' class
 387  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 388  */
 389
 390 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 391         .rev_offs       = 0x0000,
 392         .sysc_offs      = 0x0004,
 393         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 394         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 395         .sysc_fields    = &omap_hwmod_sysc_type1,
 396 };
 397
 398 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 399         .name   = "counter",
 400         .sysc   = &omap44xx_counter_sysc,
 401 };
 402
 403 /* counter_32k */
 404 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 405         .name           = "counter_32k",
 406         .class          = &omap44xx_counter_hwmod_class,
 407         .clkdm_name     = "l4_wkup_clkdm",
 408         .flags          = HWMOD_SWSUP_SIDLE,
 409         .main_clk       = "sys_32k_ck",
 410         .prcm = {
 411                 .omap4 = {
 412                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 413                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 414                 },
 415         },
 416 };
 417
 418 /*
 419  * 'ctrl_module' class
 420  * attila core control module + core pad control module + wkup pad control
 421  * module + attila wkup control module
 422  */
 423
 424 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 425         .rev_offs       = 0x0000,
 426         .sysc_offs      = 0x0010,
 427         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 428         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 429                            SIDLE_SMART_WKUP),
 430         .sysc_fields    = &omap_hwmod_sysc_type2,
 431 };
 432
 433 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 434         .name   = "ctrl_module",
 435         .sysc   = &omap44xx_ctrl_module_sysc,
 436 };
 437
 438 /* ctrl_module_core */
 439 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 440         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 441         { .irq = -1 }
 442 };
 443
 444 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 445         .name           = "ctrl_module_core",
 446         .class          = &omap44xx_ctrl_module_hwmod_class,
 447         .clkdm_name     = "l4_cfg_clkdm",
 448         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 449 };
 450
 451 /* ctrl_module_pad_core */
 452 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 453         .name           = "ctrl_module_pad_core",
 454         .class          = &omap44xx_ctrl_module_hwmod_class,
 455         .clkdm_name     = "l4_cfg_clkdm",
 456 };
 457
 458 /* ctrl_module_wkup */
 459 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 460         .name           = "ctrl_module_wkup",
 461         .class          = &omap44xx_ctrl_module_hwmod_class,
 462         .clkdm_name     = "l4_wkup_clkdm",
 463 };
 464
 465 /* ctrl_module_pad_wkup */
 466 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 467         .name           = "ctrl_module_pad_wkup",
 468         .class          = &omap44xx_ctrl_module_hwmod_class,
 469         .clkdm_name     = "l4_wkup_clkdm",
 470 };
 471
 472 /*
 473  * 'debugss' class
 474  * debug and emulation sub system
 475  */
 476
 477 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 478         .name   = "debugss",
 479 };
 480
 481 /* debugss */
 482 static struct omap_hwmod omap44xx_debugss_hwmod = {
 483         .name           = "debugss",
 484         .class          = &omap44xx_debugss_hwmod_class,
 485         .clkdm_name     = "emu_sys_clkdm",
 486         .main_clk       = "trace_clk_div_ck",
 487         .prcm = {
 488                 .omap4 = {
 489                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 490                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 491                 },
 492         },
 493 };
 494
 495 /*
 496  * 'dma' class
 497  * dma controller for data exchange between memory to memory (i.e. internal or
 498  * external memory) and gp peripherals to memory or memory to gp peripherals
 499  */
 500
 501 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 502         .rev_offs       = 0x0000,
 503         .sysc_offs      = 0x002c,
 504         .syss_offs      = 0x0028,
 505         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 506                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 507                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 508                            SYSS_HAS_RESET_STATUS),
 509         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 510                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 511         .sysc_fields    = &omap_hwmod_sysc_type1,
 512 };
 513
 514 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 515         .name   = "dma",
 516         .sysc   = &omap44xx_dma_sysc,
 517 };
 518
 519 /* dma dev_attr */
 520 static struct omap_dma_dev_attr dma_dev_attr = {
 521         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 522                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 523         .lch_count      = 32,
 524 };
 525
 526 /* dma_system */
 527 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 528         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 529         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 530         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 531         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 532         { .irq = -1 }
 533 };
 534
 535 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 536         .name           = "dma_system",
 537         .class          = &omap44xx_dma_hwmod_class,
 538         .clkdm_name     = "l3_dma_clkdm",
 539         .mpu_irqs       = omap44xx_dma_system_irqs,
 540         .main_clk       = "l3_div_ck",
 541         .prcm = {
 542                 .omap4 = {
 543                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 544                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 545                 },
 546         },
 547         .dev_attr       = &dma_dev_attr,
 548 };
 549
 550 /*
 551  * 'dmic' class
 552  * digital microphone controller
 553  */
 554
 555 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 556         .rev_offs       = 0x0000,
 557         .sysc_offs      = 0x0010,
 558         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 559                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 560         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 561                            SIDLE_SMART_WKUP),
 562         .sysc_fields    = &omap_hwmod_sysc_type2,
 563 };
 564
 565 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 566         .name   = "dmic",
 567         .sysc   = &omap44xx_dmic_sysc,
 568 };
 569
 570 /* dmic */
 571 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 572         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 573         { .irq = -1 }
 574 };
 575
 576 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 577         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 578         { .dma_req = -1 }
 579 };
 580
 581 static struct omap_hwmod omap44xx_dmic_hwmod = {
 582         .name           = "dmic",
 583         .class          = &omap44xx_dmic_hwmod_class,
 584         .clkdm_name     = "abe_clkdm",
 585         .mpu_irqs       = omap44xx_dmic_irqs,
 586         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 587         .main_clk       = "dmic_fck",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 592                         .modulemode   = MODULEMODE_SWCTRL,
 593                 },
 594         },
 595 };
 596
 597 /*
 598  * 'dsp' class
 599  * dsp sub-system
 600  */
 601
 602 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 603         .name   = "dsp",
 604 };
 605
 606 /* dsp */
 607 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 608         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 609         { .irq = -1 }
 610 };
 611
 612 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 613         { .name = "dsp", .rst_shift = 0 },
 614         { .name = "mmu_cache", .rst_shift = 1 },
 615 };
 616
 617 static struct omap_hwmod omap44xx_dsp_hwmod = {
 618         .name           = "dsp",
 619         .class          = &omap44xx_dsp_hwmod_class,
 620         .clkdm_name     = "tesla_clkdm",
 621         .mpu_irqs       = omap44xx_dsp_irqs,
 622         .rst_lines      = omap44xx_dsp_resets,
 623         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 624         .main_clk       = "dsp_fck",
 625         .prcm = {
 626                 .omap4 = {
 627                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 628                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 629                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 630                         .modulemode   = MODULEMODE_HWCTRL,
 631                 },
 632         },
 633 };
 634
 635 /*
 636  * 'dss' class
 637  * display sub-system
 638  */
 639
 640 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 641         .rev_offs       = 0x0000,
 642         .syss_offs      = 0x0014,
 643         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 644 };
 645
 646 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 647         .name   = "dss",
 648         .sysc   = &omap44xx_dss_sysc,
 649         .reset  = omap_dss_reset,
 650 };
 651
 652 /* dss */
 653 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 654         { .role = "sys_clk", .clk = "dss_sys_clk" },
 655         { .role = "tv_clk", .clk = "dss_tv_clk" },
 656         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 657 };
 658
 659 static struct omap_hwmod omap44xx_dss_hwmod = {
 660         .name           = "dss_core",
 661         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 662         .class          = &omap44xx_dss_hwmod_class,
 663         .clkdm_name     = "l3_dss_clkdm",
 664         .main_clk       = "dss_dss_clk",
 665         .prcm = {
 666                 .omap4 = {
 667                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 668                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 669                 },
 670         },
 671         .opt_clks       = dss_opt_clks,
 672         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 673 };
 674
 675 /*
 676  * 'dispc' class
 677  * display controller
 678  */
 679
 680 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 681         .rev_offs       = 0x0000,
 682         .sysc_offs      = 0x0010,
 683         .syss_offs      = 0x0014,
 684         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 685                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 686                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 687                            SYSS_HAS_RESET_STATUS),
 688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 689                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 690         .sysc_fields    = &omap_hwmod_sysc_type1,
 691 };
 692
 693 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 694         .name   = "dispc",
 695         .sysc   = &omap44xx_dispc_sysc,
 696 };
 697
 698 /* dss_dispc */
 699 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 700         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 701         { .irq = -1 }
 702 };
 703
 704 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 705         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 706         { .dma_req = -1 }
 707 };
 708
 709 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 710         .manager_count          = 3,
 711         .has_framedonetv_irq    = 1
 712 };
 713
 714 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 715         .name           = "dss_dispc",
 716         .class          = &omap44xx_dispc_hwmod_class,
 717         .clkdm_name     = "l3_dss_clkdm",
 718         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 719         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 720         .main_clk       = "dss_dss_clk",
 721         .prcm = {
 722                 .omap4 = {
 723                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 724                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 725                 },
 726         },
 727         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 728 };
 729
 730 /*
 731  * 'dsi' class
 732  * display serial interface controller
 733  */
 734
 735 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 736         .rev_offs       = 0x0000,
 737         .sysc_offs      = 0x0010,
 738         .syss_offs      = 0x0014,
 739         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 740                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 741                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 742         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 743         .sysc_fields    = &omap_hwmod_sysc_type1,
 744 };
 745
 746 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 747         .name   = "dsi",
 748         .sysc   = &omap44xx_dsi_sysc,
 749 };
 750
 751 /* dss_dsi1 */
 752 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 753         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 754         { .irq = -1 }
 755 };
 756
 757 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 758         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 759         { .dma_req = -1 }
 760 };
 761
 762 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 763         { .role = "sys_clk", .clk = "dss_sys_clk" },
 764 };
 765
 766 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 767         .name           = "dss_dsi1",
 768         .class          = &omap44xx_dsi_hwmod_class,
 769         .clkdm_name     = "l3_dss_clkdm",
 770         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 771         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 772         .main_clk       = "dss_dss_clk",
 773         .prcm = {
 774                 .omap4 = {
 775                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 776                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 777                 },
 778         },
 779         .opt_clks       = dss_dsi1_opt_clks,
 780         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 781 };
 782
 783 /* dss_dsi2 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 785         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 790         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 799         .name           = "dss_dsi2",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi2_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 813 };
 814
 815 /*
 816  * 'hdmi' class
 817  * hdmi controller
 818  */
 819
 820 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 821         .rev_offs       = 0x0000,
 822         .sysc_offs      = 0x0010,
 823         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 824                            SYSC_HAS_SOFTRESET),
 825         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 826                            SIDLE_SMART_WKUP),
 827         .sysc_fields    = &omap_hwmod_sysc_type2,
 828 };
 829
 830 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 831         .name   = "hdmi",
 832         .sysc   = &omap44xx_hdmi_sysc,
 833 };
 834
 835 /* dss_hdmi */
 836 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 837         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 838         { .irq = -1 }
 839 };
 840
 841 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 842         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 843         { .dma_req = -1 }
 844 };
 845
 846 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 847         { .role = "sys_clk", .clk = "dss_sys_clk" },
 848 };
 849
 850 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 851         .name           = "dss_hdmi",
 852         .class          = &omap44xx_hdmi_hwmod_class,
 853         .clkdm_name     = "l3_dss_clkdm",
 854         /*
 855          * HDMI audio requires to use no-idle mode. Hence,
 856          * set idle mode by software.
 857          */
 858         .flags          = HWMOD_SWSUP_SIDLE,
 859         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 860         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 861         .main_clk       = "dss_48mhz_clk",
 862         .prcm = {
 863                 .omap4 = {
 864                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 865                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 866                 },
 867         },
 868         .opt_clks       = dss_hdmi_opt_clks,
 869         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 870 };
 871
 872 /*
 873  * 'rfbi' class
 874  * remote frame buffer interface
 875  */
 876
 877 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 878         .rev_offs       = 0x0000,
 879         .sysc_offs      = 0x0010,
 880         .syss_offs      = 0x0014,
 881         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 882                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 883         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 884         .sysc_fields    = &omap_hwmod_sysc_type1,
 885 };
 886
 887 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 888         .name   = "rfbi",
 889         .sysc   = &omap44xx_rfbi_sysc,
 890 };
 891
 892 /* dss_rfbi */
 893 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 894         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 895         { .dma_req = -1 }
 896 };
 897
 898 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 899         { .role = "ick", .clk = "dss_fck" },
 900 };
 901
 902 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 903         .name           = "dss_rfbi",
 904         .class          = &omap44xx_rfbi_hwmod_class,
 905         .clkdm_name     = "l3_dss_clkdm",
 906         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 907         .main_clk       = "dss_dss_clk",
 908         .prcm = {
 909                 .omap4 = {
 910                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 911                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 912                 },
 913         },
 914         .opt_clks       = dss_rfbi_opt_clks,
 915         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 916 };
 917
 918 /*
 919  * 'venc' class
 920  * video encoder
 921  */
 922
 923 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 924         .name   = "venc",
 925 };
 926
 927 /* dss_venc */
 928 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 929         .name           = "dss_venc",
 930         .class          = &omap44xx_venc_hwmod_class,
 931         .clkdm_name     = "l3_dss_clkdm",
 932         .main_clk       = "dss_tv_clk",
 933         .prcm = {
 934                 .omap4 = {
 935                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 936                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 937                 },
 938         },
 939 };
 940
 941 /*
 942  * 'elm' class
 943  * bch error location module
 944  */
 945
 946 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 947         .rev_offs       = 0x0000,
 948         .sysc_offs      = 0x0010,
 949         .syss_offs      = 0x0014,
 950         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 951                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 952                            SYSS_HAS_RESET_STATUS),
 953         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 954         .sysc_fields    = &omap_hwmod_sysc_type1,
 955 };
 956
 957 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 958         .name   = "elm",
 959         .sysc   = &omap44xx_elm_sysc,
 960 };
 961
 962 /* elm */
 963 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 964         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 965         { .irq = -1 }
 966 };
 967
 968 static struct omap_hwmod omap44xx_elm_hwmod = {
 969         .name           = "elm",
 970         .class          = &omap44xx_elm_hwmod_class,
 971         .clkdm_name     = "l4_per_clkdm",
 972         .mpu_irqs       = omap44xx_elm_irqs,
 973         .prcm = {
 974                 .omap4 = {
 975                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 976                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 977                 },
 978         },
 979 };
 980
 981 /*
 982  * 'emif' class
 983  * external memory interface no1
 984  */
 985
 986 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 987         .rev_offs       = 0x0000,
 988 };
 989
 990 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 991         .name   = "emif",
 992         .sysc   = &omap44xx_emif_sysc,
 993 };
 994
 995 /* emif1 */
 996 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 997         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
 998         { .irq = -1 }
 999 };
1000
1001 static struct omap_hwmod omap44xx_emif1_hwmod = {
1002         .name           = "emif1",
1003         .class          = &omap44xx_emif_hwmod_class,
1004         .clkdm_name     = "l3_emif_clkdm",
1005         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1006         .mpu_irqs       = omap44xx_emif1_irqs,
1007         .main_clk       = "ddrphy_ck",
1008         .prcm = {
1009                 .omap4 = {
1010                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1011                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1012                         .modulemode   = MODULEMODE_HWCTRL,
1013                 },
1014         },
1015 };
1016
1017 /* emif2 */
1018 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1019         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1020         { .irq = -1 }
1021 };
1022
1023 static struct omap_hwmod omap44xx_emif2_hwmod = {
1024         .name           = "emif2",
1025         .class          = &omap44xx_emif_hwmod_class,
1026         .clkdm_name     = "l3_emif_clkdm",
1027         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1028         .mpu_irqs       = omap44xx_emif2_irqs,
1029         .main_clk       = "ddrphy_ck",
1030         .prcm = {
1031                 .omap4 = {
1032                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1033                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1034                         .modulemode   = MODULEMODE_HWCTRL,
1035                 },
1036         },
1037 };
1038
1039 /*
1040  * 'fdif' class
1041  * face detection hw accelerator module
1042  */
1043
1044 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1045         .rev_offs       = 0x0000,
1046         .sysc_offs      = 0x0010,
1047         /*
1048          * FDIF needs 100 OCP clk cycles delay after a softreset before
1049          * accessing sysconfig again.
1050          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1051          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1052          *
1053          * TODO: Indicate errata when available.
1054          */
1055         .srst_udelay    = 2,
1056         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1057                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1058         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1059                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1060         .sysc_fields    = &omap_hwmod_sysc_type2,
1061 };
1062
1063 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1064         .name   = "fdif",
1065         .sysc   = &omap44xx_fdif_sysc,
1066 };
1067
1068 /* fdif */
1069 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1070         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1071         { .irq = -1 }
1072 };
1073
1074 static struct omap_hwmod omap44xx_fdif_hwmod = {
1075         .name           = "fdif",
1076         .class          = &omap44xx_fdif_hwmod_class,
1077         .clkdm_name     = "iss_clkdm",
1078         .mpu_irqs       = omap44xx_fdif_irqs,
1079         .main_clk       = "fdif_fck",
1080         .prcm = {
1081                 .omap4 = {
1082                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1083                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1084                         .modulemode   = MODULEMODE_SWCTRL,
1085                 },
1086         },
1087 };
1088
1089 /*
1090  * 'gpio' class
1091  * general purpose io module
1092  */
1093
1094 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1095         .rev_offs       = 0x0000,
1096         .sysc_offs      = 0x0010,
1097         .syss_offs      = 0x0114,
1098         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1099                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1100                            SYSS_HAS_RESET_STATUS),
1101         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1102                            SIDLE_SMART_WKUP),
1103         .sysc_fields    = &omap_hwmod_sysc_type1,
1104 };
1105
1106 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1107         .name   = "gpio",
1108         .sysc   = &omap44xx_gpio_sysc,
1109         .rev    = 2,
1110 };
1111
1112 /* gpio dev_attr */
1113 static struct omap_gpio_dev_attr gpio_dev_attr = {
1114         .bank_width     = 32,
1115         .dbck_flag      = true,
1116 };
1117
1118 /* gpio1 */
1119 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1120         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1121         { .irq = -1 }
1122 };
1123
1124 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1125         { .role = "dbclk", .clk = "gpio1_dbclk" },
1126 };
1127
1128 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1129         .name           = "gpio1",
1130         .class          = &omap44xx_gpio_hwmod_class,
1131         .clkdm_name     = "l4_wkup_clkdm",
1132         .mpu_irqs       = omap44xx_gpio1_irqs,
1133         .main_clk       = "gpio1_ick",
1134         .prcm = {
1135                 .omap4 = {
1136                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1137                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1138                         .modulemode   = MODULEMODE_HWCTRL,
1139                 },
1140         },
1141         .opt_clks       = gpio1_opt_clks,
1142         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1143         .dev_attr       = &gpio_dev_attr,
1144 };
1145
1146 /* gpio2 */
1147 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1148         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1149         { .irq = -1 }
1150 };
1151
1152 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1153         { .role = "dbclk", .clk = "gpio2_dbclk" },
1154 };
1155
1156 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1157         .name           = "gpio2",
1158         .class          = &omap44xx_gpio_hwmod_class,
1159         .clkdm_name     = "l4_per_clkdm",
1160         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1161         .mpu_irqs       = omap44xx_gpio2_irqs,
1162         .main_clk       = "gpio2_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .opt_clks       = gpio2_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio3 */
1176 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1177         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1178         { .irq = -1 }
1179 };
1180
1181 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1182         { .role = "dbclk", .clk = "gpio3_dbclk" },
1183 };
1184
1185 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1186         .name           = "gpio3",
1187         .class          = &omap44xx_gpio_hwmod_class,
1188         .clkdm_name     = "l4_per_clkdm",
1189         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190         .mpu_irqs       = omap44xx_gpio3_irqs,
1191         .main_clk       = "gpio3_ick",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199         .opt_clks       = gpio3_opt_clks,
1200         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1201         .dev_attr       = &gpio_dev_attr,
1202 };
1203
1204 /* gpio4 */
1205 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1206         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1207         { .irq = -1 }
1208 };
1209
1210 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1211         { .role = "dbclk", .clk = "gpio4_dbclk" },
1212 };
1213
1214 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1215         .name           = "gpio4",
1216         .class          = &omap44xx_gpio_hwmod_class,
1217         .clkdm_name     = "l4_per_clkdm",
1218         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219         .mpu_irqs       = omap44xx_gpio4_irqs,
1220         .main_clk       = "gpio4_ick",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_HWCTRL,
1226                 },
1227         },
1228         .opt_clks       = gpio4_opt_clks,
1229         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1230         .dev_attr       = &gpio_dev_attr,
1231 };
1232
1233 /* gpio5 */
1234 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1235         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1236         { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1240         { .role = "dbclk", .clk = "gpio5_dbclk" },
1241 };
1242
1243 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1244         .name           = "gpio5",
1245         .class          = &omap44xx_gpio_hwmod_class,
1246         .clkdm_name     = "l4_per_clkdm",
1247         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248         .mpu_irqs       = omap44xx_gpio5_irqs,
1249         .main_clk       = "gpio5_ick",
1250         .prcm = {
1251                 .omap4 = {
1252                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1253                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1254                         .modulemode   = MODULEMODE_HWCTRL,
1255                 },
1256         },
1257         .opt_clks       = gpio5_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1259         .dev_attr       = &gpio_dev_attr,
1260 };
1261
1262 /* gpio6 */
1263 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1264         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1265         { .irq = -1 }
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1269         { .role = "dbclk", .clk = "gpio6_dbclk" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1273         .name           = "gpio6",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .clkdm_name     = "l4_per_clkdm",
1276         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277         .mpu_irqs       = omap44xx_gpio6_irqs,
1278         .main_clk       = "gpio6_ick",
1279         .prcm = {
1280                 .omap4 = {
1281                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1282                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1283                         .modulemode   = MODULEMODE_HWCTRL,
1284                 },
1285         },
1286         .opt_clks       = gpio6_opt_clks,
1287         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1288         .dev_attr       = &gpio_dev_attr,
1289 };
1290
1291 /*
1292  * 'gpmc' class
1293  * general purpose memory controller
1294  */
1295
1296 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1297         .rev_offs       = 0x0000,
1298         .sysc_offs      = 0x0010,
1299         .syss_offs      = 0x0014,
1300         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1301                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1302         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1303         .sysc_fields    = &omap_hwmod_sysc_type1,
1304 };
1305
1306 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1307         .name   = "gpmc",
1308         .sysc   = &omap44xx_gpmc_sysc,
1309 };
1310
1311 /* gpmc */
1312 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1313         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1314         { .irq = -1 }
1315 };
1316
1317 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1318         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1319         { .dma_req = -1 }
1320 };
1321
1322 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1323         .name           = "gpmc",
1324         .class          = &omap44xx_gpmc_hwmod_class,
1325         .clkdm_name     = "l3_2_clkdm",
1326         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1327         .mpu_irqs       = omap44xx_gpmc_irqs,
1328         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1332                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1333                         .modulemode   = MODULEMODE_HWCTRL,
1334                 },
1335         },
1336 };
1337
1338 /*
1339  * 'gpu' class
1340  * 2d/3d graphics accelerator
1341  */
1342
1343 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1344         .rev_offs       = 0x1fc00,
1345         .sysc_offs      = 0x1fc10,
1346         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1347         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1348                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1349                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1350         .sysc_fields    = &omap_hwmod_sysc_type2,
1351 };
1352
1353 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1354         .name   = "gpu",
1355         .sysc   = &omap44xx_gpu_sysc,
1356 };
1357
1358 /* gpu */
1359 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1360         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1361         { .irq = -1 }
1362 };
1363
1364 static struct omap_hwmod omap44xx_gpu_hwmod = {
1365         .name           = "gpu",
1366         .class          = &omap44xx_gpu_hwmod_class,
1367         .clkdm_name     = "l3_gfx_clkdm",
1368         .mpu_irqs       = omap44xx_gpu_irqs,
1369         .main_clk       = "gpu_fck",
1370         .prcm = {
1371                 .omap4 = {
1372                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1373                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1374                         .modulemode   = MODULEMODE_SWCTRL,
1375                 },
1376         },
1377 };
1378
1379 /*
1380  * 'hdq1w' class
1381  * hdq / 1-wire serial interface controller
1382  */
1383
1384 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1385         .rev_offs       = 0x0000,
1386         .sysc_offs      = 0x0014,
1387         .syss_offs      = 0x0018,
1388         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1389                            SYSS_HAS_RESET_STATUS),
1390         .sysc_fields    = &omap_hwmod_sysc_type1,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1394         .name   = "hdq1w",
1395         .sysc   = &omap44xx_hdq1w_sysc,
1396 };
1397
1398 /* hdq1w */
1399 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1400         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1405         .name           = "hdq1w",
1406         .class          = &omap44xx_hdq1w_hwmod_class,
1407         .clkdm_name     = "l4_per_clkdm",
1408         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1409         .mpu_irqs       = omap44xx_hdq1w_irqs,
1410         .main_clk       = "hdq1w_fck",
1411         .prcm = {
1412                 .omap4 = {
1413                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1414                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1415                         .modulemode   = MODULEMODE_SWCTRL,
1416                 },
1417         },
1418 };
1419
1420 /*
1421  * 'hsi' class
1422  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1423  * serial if)
1424  */
1425
1426 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1427         .rev_offs       = 0x0000,
1428         .sysc_offs      = 0x0010,
1429         .syss_offs      = 0x0014,
1430         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1431                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1432                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1433         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1434                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1435                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1436         .sysc_fields    = &omap_hwmod_sysc_type1,
1437 };
1438
1439 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1440         .name   = "hsi",
1441         .sysc   = &omap44xx_hsi_sysc,
1442 };
1443
1444 /* hsi */
1445 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1446         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1447         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1448         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1449         { .irq = -1 }
1450 };
1451
1452 static struct omap_hwmod omap44xx_hsi_hwmod = {
1453         .name           = "hsi",
1454         .class          = &omap44xx_hsi_hwmod_class,
1455         .clkdm_name     = "l3_init_clkdm",
1456         .mpu_irqs       = omap44xx_hsi_irqs,
1457         .main_clk       = "hsi_fck",
1458         .prcm = {
1459                 .omap4 = {
1460                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1461                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1462                         .modulemode   = MODULEMODE_HWCTRL,
1463                 },
1464         },
1465 };
1466
1467 /*
1468  * 'i2c' class
1469  * multimaster high-speed i2c controller
1470  */
1471
1472 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1473         .sysc_offs      = 0x0010,
1474         .syss_offs      = 0x0090,
1475         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1476                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1477                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1478         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1479                            SIDLE_SMART_WKUP),
1480         .clockact       = CLOCKACT_TEST_ICLK,
1481         .sysc_fields    = &omap_hwmod_sysc_type1,
1482 };
1483
1484 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1485         .name   = "i2c",
1486         .sysc   = &omap44xx_i2c_sysc,
1487         .rev    = OMAP_I2C_IP_VERSION_2,
1488         .reset  = &omap_i2c_reset,
1489 };
1490
1491 static struct omap_i2c_dev_attr i2c_dev_attr = {
1492         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1493                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1494 };
1495
1496 /* i2c1 */
1497 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1498         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1499         { .irq = -1 }
1500 };
1501
1502 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1503         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1504         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1505         { .dma_req = -1 }
1506 };
1507
1508 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1509         .name           = "i2c1",
1510         .class          = &omap44xx_i2c_hwmod_class,
1511         .clkdm_name     = "l4_per_clkdm",
1512         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1513         .mpu_irqs       = omap44xx_i2c1_irqs,
1514         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1515         .main_clk       = "i2c1_fck",
1516         .prcm = {
1517                 .omap4 = {
1518                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1519                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1520                         .modulemode   = MODULEMODE_SWCTRL,
1521                 },
1522         },
1523         .dev_attr       = &i2c_dev_attr,
1524 };
1525
1526 /* i2c2 */
1527 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1528         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1529         { .irq = -1 }
1530 };
1531
1532 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1533         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1534         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1535         { .dma_req = -1 }
1536 };
1537
1538 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1539         .name           = "i2c2",
1540         .class          = &omap44xx_i2c_hwmod_class,
1541         .clkdm_name     = "l4_per_clkdm",
1542         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1543         .mpu_irqs       = omap44xx_i2c2_irqs,
1544         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1545         .main_clk       = "i2c2_fck",
1546         .prcm = {
1547                 .omap4 = {
1548                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1549                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1550                         .modulemode   = MODULEMODE_SWCTRL,
1551                 },
1552         },
1553         .dev_attr       = &i2c_dev_attr,
1554 };
1555
1556 /* i2c3 */
1557 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1558         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1559         { .irq = -1 }
1560 };
1561
1562 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1563         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1564         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1565         { .dma_req = -1 }
1566 };
1567
1568 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1569         .name           = "i2c3",
1570         .class          = &omap44xx_i2c_hwmod_class,
1571         .clkdm_name     = "l4_per_clkdm",
1572         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1573         .mpu_irqs       = omap44xx_i2c3_irqs,
1574         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1575         .main_clk       = "i2c3_fck",
1576         .prcm = {
1577                 .omap4 = {
1578                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1579                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1580                         .modulemode   = MODULEMODE_SWCTRL,
1581                 },
1582         },
1583         .dev_attr       = &i2c_dev_attr,
1584 };
1585
1586 /* i2c4 */
1587 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1588         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1589         { .irq = -1 }
1590 };
1591
1592 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1593         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1594         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1595         { .dma_req = -1 }
1596 };
1597
1598 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1599         .name           = "i2c4",
1600         .class          = &omap44xx_i2c_hwmod_class,
1601         .clkdm_name     = "l4_per_clkdm",
1602         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1603         .mpu_irqs       = omap44xx_i2c4_irqs,
1604         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1605         .main_clk       = "i2c4_fck",
1606         .prcm = {
1607                 .omap4 = {
1608                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1609                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1610                         .modulemode   = MODULEMODE_SWCTRL,
1611                 },
1612         },
1613         .dev_attr       = &i2c_dev_attr,
1614 };
1615
1616 /*
1617  * 'ipu' class
1618  * imaging processor unit
1619  */
1620
1621 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1622         .name   = "ipu",
1623 };
1624
1625 /* ipu */
1626 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1627         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1632         { .name = "cpu0", .rst_shift = 0 },
1633         { .name = "cpu1", .rst_shift = 1 },
1634         { .name = "mmu_cache", .rst_shift = 2 },
1635 };
1636
1637 static struct omap_hwmod omap44xx_ipu_hwmod = {
1638         .name           = "ipu",
1639         .class          = &omap44xx_ipu_hwmod_class,
1640         .clkdm_name     = "ducati_clkdm",
1641         .mpu_irqs       = omap44xx_ipu_irqs,
1642         .rst_lines      = omap44xx_ipu_resets,
1643         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1644         .main_clk       = "ipu_fck",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1648                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1649                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1650                         .modulemode   = MODULEMODE_HWCTRL,
1651                 },
1652         },
1653 };
1654
1655 /*
1656  * 'iss' class
1657  * external images sensor pixel data processor
1658  */
1659
1660 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1661         .rev_offs       = 0x0000,
1662         .sysc_offs      = 0x0010,
1663         /*
1664          * ISS needs 100 OCP clk cycles delay after a softreset before
1665          * accessing sysconfig again.
1666          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1667          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1668          *
1669          * TODO: Indicate errata when available.
1670          */
1671         .srst_udelay    = 2,
1672         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1673                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1674         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1675                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1676                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1677         .sysc_fields    = &omap_hwmod_sysc_type2,
1678 };
1679
1680 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1681         .name   = "iss",
1682         .sysc   = &omap44xx_iss_sysc,
1683 };
1684
1685 /* iss */
1686 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1687         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1688         { .irq = -1 }
1689 };
1690
1691 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1692         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1693         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1694         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1695         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1696         { .dma_req = -1 }
1697 };
1698
1699 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1700         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1701 };
1702
1703 static struct omap_hwmod omap44xx_iss_hwmod = {
1704         .name           = "iss",
1705         .class          = &omap44xx_iss_hwmod_class,
1706         .clkdm_name     = "iss_clkdm",
1707         .mpu_irqs       = omap44xx_iss_irqs,
1708         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1709         .main_clk       = "iss_fck",
1710         .prcm = {
1711                 .omap4 = {
1712                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1713                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1714                         .modulemode   = MODULEMODE_SWCTRL,
1715                 },
1716         },
1717         .opt_clks       = iss_opt_clks,
1718         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1719 };
1720
1721 /*
1722  * 'iva' class
1723  * multi-standard video encoder/decoder hardware accelerator
1724  */
1725
1726 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1727         .name   = "iva",
1728 };
1729
1730 /* iva */
1731 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1732         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1733         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1734         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1735         { .irq = -1 }
1736 };
1737
1738 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1739         { .name = "seq0", .rst_shift = 0 },
1740         { .name = "seq1", .rst_shift = 1 },
1741         { .name = "logic", .rst_shift = 2 },
1742 };
1743
1744 static struct omap_hwmod omap44xx_iva_hwmod = {
1745         .name           = "iva",
1746         .class          = &omap44xx_iva_hwmod_class,
1747         .clkdm_name     = "ivahd_clkdm",
1748         .mpu_irqs       = omap44xx_iva_irqs,
1749         .rst_lines      = omap44xx_iva_resets,
1750         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1751         .main_clk       = "iva_fck",
1752         .prcm = {
1753                 .omap4 = {
1754                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1755                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1756                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1757                         .modulemode   = MODULEMODE_HWCTRL,
1758                 },
1759         },
1760 };
1761
1762 /*
1763  * 'kbd' class
1764  * keyboard controller
1765  */
1766
1767 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1768         .rev_offs       = 0x0000,
1769         .sysc_offs      = 0x0010,
1770         .syss_offs      = 0x0014,
1771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1772                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1773                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1774                            SYSS_HAS_RESET_STATUS),
1775         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1776         .sysc_fields    = &omap_hwmod_sysc_type1,
1777 };
1778
1779 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1780         .name   = "kbd",
1781         .sysc   = &omap44xx_kbd_sysc,
1782 };
1783
1784 /* kbd */
1785 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1786         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1787         { .irq = -1 }
1788 };
1789
1790 static struct omap_hwmod omap44xx_kbd_hwmod = {
1791         .name           = "kbd",
1792         .class          = &omap44xx_kbd_hwmod_class,
1793         .clkdm_name     = "l4_wkup_clkdm",
1794         .mpu_irqs       = omap44xx_kbd_irqs,
1795         .main_clk       = "kbd_fck",
1796         .prcm = {
1797                 .omap4 = {
1798                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1799                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1800                         .modulemode   = MODULEMODE_SWCTRL,
1801                 },
1802         },
1803 };
1804
1805 /*
1806  * 'mailbox' class
1807  * mailbox module allowing communication between the on-chip processors using a
1808  * queued mailbox-interrupt mechanism.
1809  */
1810
1811 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1812         .rev_offs       = 0x0000,
1813         .sysc_offs      = 0x0010,
1814         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1815                            SYSC_HAS_SOFTRESET),
1816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1817         .sysc_fields    = &omap_hwmod_sysc_type2,
1818 };
1819
1820 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1821         .name   = "mailbox",
1822         .sysc   = &omap44xx_mailbox_sysc,
1823 };
1824
1825 /* mailbox */
1826 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1827         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1828         { .irq = -1 }
1829 };
1830
1831 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1832         .name           = "mailbox",
1833         .class          = &omap44xx_mailbox_hwmod_class,
1834         .clkdm_name     = "l4_cfg_clkdm",
1835         .mpu_irqs       = omap44xx_mailbox_irqs,
1836         .prcm = {
1837                 .omap4 = {
1838                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1839                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1840                 },
1841         },
1842 };
1843
1844 /*
1845  * 'mcasp' class
1846  * multi-channel audio serial port controller
1847  */
1848
1849 /* The IP is not compliant to type1 / type2 scheme */
1850 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1851         .sidle_shift    = 0,
1852 };
1853
1854 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1855         .sysc_offs      = 0x0004,
1856         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1858                            SIDLE_SMART_WKUP),
1859         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1860 };
1861
1862 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1863         .name   = "mcasp",
1864         .sysc   = &omap44xx_mcasp_sysc,
1865 };
1866
1867 /* mcasp */
1868 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1869         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1870         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1871         { .irq = -1 }
1872 };
1873
1874 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1875         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1876         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1877         { .dma_req = -1 }
1878 };
1879
1880 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1881         .name           = "mcasp",
1882         .class          = &omap44xx_mcasp_hwmod_class,
1883         .clkdm_name     = "abe_clkdm",
1884         .mpu_irqs       = omap44xx_mcasp_irqs,
1885         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1886         .main_clk       = "mcasp_fck",
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1890                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1891                         .modulemode   = MODULEMODE_SWCTRL,
1892                 },
1893         },
1894 };
1895
1896 /*
1897  * 'mcbsp' class
1898  * multi channel buffered serial port controller
1899  */
1900
1901 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1902         .sysc_offs      = 0x008c,
1903         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1904                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1905         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1906         .sysc_fields    = &omap_hwmod_sysc_type1,
1907 };
1908
1909 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1910         .name   = "mcbsp",
1911         .sysc   = &omap44xx_mcbsp_sysc,
1912         .rev    = MCBSP_CONFIG_TYPE4,
1913 };
1914
1915 /* mcbsp1 */
1916 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1917         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1918         { .irq = -1 }
1919 };
1920
1921 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1922         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1923         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1924         { .dma_req = -1 }
1925 };
1926
1927 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1928         { .role = "pad_fck", .clk = "pad_clks_ck" },
1929         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1930 };
1931
1932 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1933         .name           = "mcbsp1",
1934         .class          = &omap44xx_mcbsp_hwmod_class,
1935         .clkdm_name     = "abe_clkdm",
1936         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1937         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1938         .main_clk       = "mcbsp1_fck",
1939         .prcm = {
1940                 .omap4 = {
1941                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1942                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1943                         .modulemode   = MODULEMODE_SWCTRL,
1944                 },
1945         },
1946         .opt_clks       = mcbsp1_opt_clks,
1947         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1948 };
1949
1950 /* mcbsp2 */
1951 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1952         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1953         { .irq = -1 }
1954 };
1955
1956 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1957         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1958         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1959         { .dma_req = -1 }
1960 };
1961
1962 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1963         { .role = "pad_fck", .clk = "pad_clks_ck" },
1964         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1965 };
1966
1967 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1968         .name           = "mcbsp2",
1969         .class          = &omap44xx_mcbsp_hwmod_class,
1970         .clkdm_name     = "abe_clkdm",
1971         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1972         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1973         .main_clk       = "mcbsp2_fck",
1974         .prcm = {
1975                 .omap4 = {
1976                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1977                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1978                         .modulemode   = MODULEMODE_SWCTRL,
1979                 },
1980         },
1981         .opt_clks       = mcbsp2_opt_clks,
1982         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1983 };
1984
1985 /* mcbsp3 */
1986 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1987         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1988         { .irq = -1 }
1989 };
1990
1991 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1992         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1993         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1994         { .dma_req = -1 }
1995 };
1996
1997 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1998         { .role = "pad_fck", .clk = "pad_clks_ck" },
1999         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2000 };
2001
2002 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2003         .name           = "mcbsp3",
2004         .class          = &omap44xx_mcbsp_hwmod_class,
2005         .clkdm_name     = "abe_clkdm",
2006         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2007         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2008         .main_clk       = "mcbsp3_fck",
2009         .prcm = {
2010                 .omap4 = {
2011                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2012                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2013                         .modulemode   = MODULEMODE_SWCTRL,
2014                 },
2015         },
2016         .opt_clks       = mcbsp3_opt_clks,
2017         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2018 };
2019
2020 /* mcbsp4 */
2021 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2022         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2023         { .irq = -1 }
2024 };
2025
2026 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2027         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2028         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2029         { .dma_req = -1 }
2030 };
2031
2032 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2033         { .role = "pad_fck", .clk = "pad_clks_ck" },
2034         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2035 };
2036
2037 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2038         .name           = "mcbsp4",
2039         .class          = &omap44xx_mcbsp_hwmod_class,
2040         .clkdm_name     = "l4_per_clkdm",
2041         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2042         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2043         .main_clk       = "mcbsp4_fck",
2044         .prcm = {
2045                 .omap4 = {
2046                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2047                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2048                         .modulemode   = MODULEMODE_SWCTRL,
2049                 },
2050         },
2051         .opt_clks       = mcbsp4_opt_clks,
2052         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2053 };
2054
2055 /*
2056  * 'mcpdm' class
2057  * multi channel pdm controller (proprietary interface with phoenix power
2058  * ic)
2059  */
2060
2061 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2062         .rev_offs       = 0x0000,
2063         .sysc_offs      = 0x0010,
2064         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2065                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2067                            SIDLE_SMART_WKUP),
2068         .sysc_fields    = &omap_hwmod_sysc_type2,
2069 };
2070
2071 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2072         .name   = "mcpdm",
2073         .sysc   = &omap44xx_mcpdm_sysc,
2074 };
2075
2076 /* mcpdm */
2077 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2078         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2079         { .irq = -1 }
2080 };
2081
2082 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2083         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2084         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2085         { .dma_req = -1 }
2086 };
2087
2088 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2089         .name           = "mcpdm",
2090         .class          = &omap44xx_mcpdm_hwmod_class,
2091         .clkdm_name     = "abe_clkdm",
2092         .mpu_irqs       = omap44xx_mcpdm_irqs,
2093         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2094         .main_clk       = "mcpdm_fck",
2095         .prcm = {
2096                 .omap4 = {
2097                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2098                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2099                         .modulemode   = MODULEMODE_SWCTRL,
2100                 },
2101         },
2102 };
2103
2104 /*
2105  * 'mcspi' class
2106  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2107  * bus
2108  */
2109
2110 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2111         .rev_offs       = 0x0000,
2112         .sysc_offs      = 0x0010,
2113         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2114                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2115         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2116                            SIDLE_SMART_WKUP),
2117         .sysc_fields    = &omap_hwmod_sysc_type2,
2118 };
2119
2120 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2121         .name   = "mcspi",
2122         .sysc   = &omap44xx_mcspi_sysc,
2123         .rev    = OMAP4_MCSPI_REV,
2124 };
2125
2126 /* mcspi1 */
2127 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2128         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2129         { .irq = -1 }
2130 };
2131
2132 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2133         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2134         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2135         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2136         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2137         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2138         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2139         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2140         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2141         { .dma_req = -1 }
2142 };
2143
2144 /* mcspi1 dev_attr */
2145 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2146         .num_chipselect = 4,
2147 };
2148
2149 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2150         .name           = "mcspi1",
2151         .class          = &omap44xx_mcspi_hwmod_class,
2152         .clkdm_name     = "l4_per_clkdm",
2153         .mpu_irqs       = omap44xx_mcspi1_irqs,
2154         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2155         .main_clk       = "mcspi1_fck",
2156         .prcm = {
2157                 .omap4 = {
2158                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2159                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2160                         .modulemode   = MODULEMODE_SWCTRL,
2161                 },
2162         },
2163         .dev_attr       = &mcspi1_dev_attr,
2164 };
2165
2166 /* mcspi2 */
2167 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2168         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2169         { .irq = -1 }
2170 };
2171
2172 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2173         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2174         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2175         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2176         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2177         { .dma_req = -1 }
2178 };
2179
2180 /* mcspi2 dev_attr */
2181 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2182         .num_chipselect = 2,
2183 };
2184
2185 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2186         .name           = "mcspi2",
2187         .class          = &omap44xx_mcspi_hwmod_class,
2188         .clkdm_name     = "l4_per_clkdm",
2189         .mpu_irqs       = omap44xx_mcspi2_irqs,
2190         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2191         .main_clk       = "mcspi2_fck",
2192         .prcm = {
2193                 .omap4 = {
2194                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2195                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2196                         .modulemode   = MODULEMODE_SWCTRL,
2197                 },
2198         },
2199         .dev_attr       = &mcspi2_dev_attr,
2200 };
2201
2202 /* mcspi3 */
2203 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2204         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2205         { .irq = -1 }
2206 };
2207
2208 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2209         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2210         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2211         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2212         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2213         { .dma_req = -1 }
2214 };
2215
2216 /* mcspi3 dev_attr */
2217 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2218         .num_chipselect = 2,
2219 };
2220
2221 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2222         .name           = "mcspi3",
2223         .class          = &omap44xx_mcspi_hwmod_class,
2224         .clkdm_name     = "l4_per_clkdm",
2225         .mpu_irqs       = omap44xx_mcspi3_irqs,
2226         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2227         .main_clk       = "mcspi3_fck",
2228         .prcm = {
2229                 .omap4 = {
2230                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2231                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2232                         .modulemode   = MODULEMODE_SWCTRL,
2233                 },
2234         },
2235         .dev_attr       = &mcspi3_dev_attr,
2236 };
2237
2238 /* mcspi4 */
2239 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2240         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2241         { .irq = -1 }
2242 };
2243
2244 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2245         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2246         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2247         { .dma_req = -1 }
2248 };
2249
2250 /* mcspi4 dev_attr */
2251 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2252         .num_chipselect = 1,
2253 };
2254
2255 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2256         .name           = "mcspi4",
2257         .class          = &omap44xx_mcspi_hwmod_class,
2258         .clkdm_name     = "l4_per_clkdm",
2259         .mpu_irqs       = omap44xx_mcspi4_irqs,
2260         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2261         .main_clk       = "mcspi4_fck",
2262         .prcm = {
2263                 .omap4 = {
2264                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2265                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2266                         .modulemode   = MODULEMODE_SWCTRL,
2267                 },
2268         },
2269         .dev_attr       = &mcspi4_dev_attr,
2270 };
2271
2272 /*
2273  * 'mmc' class
2274  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2275  */
2276
2277 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2278         .rev_offs       = 0x0000,
2279         .sysc_offs      = 0x0010,
2280         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2281                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2282                            SYSC_HAS_SOFTRESET),
2283         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2284                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2285                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2286         .sysc_fields    = &omap_hwmod_sysc_type2,
2287 };
2288
2289 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2290         .name   = "mmc",
2291         .sysc   = &omap44xx_mmc_sysc,
2292 };
2293
2294 /* mmc1 */
2295 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2296         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2297         { .irq = -1 }
2298 };
2299
2300 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2301         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2302         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2303         { .dma_req = -1 }
2304 };
2305
2306 /* mmc1 dev_attr */
2307 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2308         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2309 };
2310
2311 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2312         .name           = "mmc1",
2313         .class          = &omap44xx_mmc_hwmod_class,
2314         .clkdm_name     = "l3_init_clkdm",
2315         .mpu_irqs       = omap44xx_mmc1_irqs,
2316         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2317         .main_clk       = "mmc1_fck",
2318         .prcm = {
2319                 .omap4 = {
2320                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2321                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2322                         .modulemode   = MODULEMODE_SWCTRL,
2323                 },
2324         },
2325         .dev_attr       = &mmc1_dev_attr,
2326 };
2327
2328 /* mmc2 */
2329 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2330         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2331         { .irq = -1 }
2332 };
2333
2334 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2335         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2336         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2337         { .dma_req = -1 }
2338 };
2339
2340 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2341         .name           = "mmc2",
2342         .class          = &omap44xx_mmc_hwmod_class,
2343         .clkdm_name     = "l3_init_clkdm",
2344         .mpu_irqs       = omap44xx_mmc2_irqs,
2345         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2346         .main_clk       = "mmc2_fck",
2347         .prcm = {
2348                 .omap4 = {
2349                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2350                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2351                         .modulemode   = MODULEMODE_SWCTRL,
2352                 },
2353         },
2354 };
2355
2356 /* mmc3 */
2357 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2358         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2359         { .irq = -1 }
2360 };
2361
2362 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2363         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2364         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2365         { .dma_req = -1 }
2366 };
2367
2368 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2369         .name           = "mmc3",
2370         .class          = &omap44xx_mmc_hwmod_class,
2371         .clkdm_name     = "l4_per_clkdm",
2372         .mpu_irqs       = omap44xx_mmc3_irqs,
2373         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2374         .main_clk       = "mmc3_fck",
2375         .prcm = {
2376                 .omap4 = {
2377                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2378                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2379                         .modulemode   = MODULEMODE_SWCTRL,
2380                 },
2381         },
2382 };
2383
2384 /* mmc4 */
2385 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2386         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2387         { .irq = -1 }
2388 };
2389
2390 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2391         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2392         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2393         { .dma_req = -1 }
2394 };
2395
2396 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2397         .name           = "mmc4",
2398         .class          = &omap44xx_mmc_hwmod_class,
2399         .clkdm_name     = "l4_per_clkdm",
2400         .mpu_irqs       = omap44xx_mmc4_irqs,
2401         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2402         .main_clk       = "mmc4_fck",
2403         .prcm = {
2404                 .omap4 = {
2405                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2406                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2407                         .modulemode   = MODULEMODE_SWCTRL,
2408                 },
2409         },
2410 };
2411
2412 /* mmc5 */
2413 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2414         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2415         { .irq = -1 }
2416 };
2417
2418 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2419         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2420         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2421         { .dma_req = -1 }
2422 };
2423
2424 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2425         .name           = "mmc5",
2426         .class          = &omap44xx_mmc_hwmod_class,
2427         .clkdm_name     = "l4_per_clkdm",
2428         .mpu_irqs       = omap44xx_mmc5_irqs,
2429         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2430         .main_clk       = "mmc5_fck",
2431         .prcm = {
2432                 .omap4 = {
2433                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2434                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2435                         .modulemode   = MODULEMODE_SWCTRL,
2436                 },
2437         },
2438 };
2439
2440 /*
2441  * 'mpu' class
2442  * mpu sub-system
2443  */
2444
2445 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2446         .name   = "mpu",
2447 };
2448
2449 /* mpu */
2450 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2451         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2452         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2453         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2454         { .irq = -1 }
2455 };
2456
2457 static struct omap_hwmod omap44xx_mpu_hwmod = {
2458         .name           = "mpu",
2459         .class          = &omap44xx_mpu_hwmod_class,
2460         .clkdm_name     = "mpuss_clkdm",
2461         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2462         .mpu_irqs       = omap44xx_mpu_irqs,
2463         .main_clk       = "dpll_mpu_m2_ck",
2464         .prcm = {
2465                 .omap4 = {
2466                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2467                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2468                 },
2469         },
2470 };
2471
2472 /*
2473  * 'ocmc_ram' class
2474  * top-level core on-chip ram
2475  */
2476
2477 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2478         .name   = "ocmc_ram",
2479 };
2480
2481 /* ocmc_ram */
2482 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2483         .name           = "ocmc_ram",
2484         .class          = &omap44xx_ocmc_ram_hwmod_class,
2485         .clkdm_name     = "l3_2_clkdm",
2486         .prcm = {
2487                 .omap4 = {
2488                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2489                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2490                 },
2491         },
2492 };
2493
2494 /*
2495  * 'ocp2scp' class
2496  * bridge to transform ocp interface protocol to scp (serial control port)
2497  * protocol
2498  */
2499
2500 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2501         .name   = "ocp2scp",
2502 };
2503
2504 /* ocp2scp_usb_phy */
2505 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2506         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2507 };
2508
2509 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2510         .name           = "ocp2scp_usb_phy",
2511         .class          = &omap44xx_ocp2scp_hwmod_class,
2512         .clkdm_name     = "l3_init_clkdm",
2513         .prcm = {
2514                 .omap4 = {
2515                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2516                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2517                         .modulemode   = MODULEMODE_HWCTRL,
2518                 },
2519         },
2520         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2521         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2522 };
2523
2524 /*
2525  * 'prcm' class
2526  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2527  * + clock manager 1 (in always on power domain) + local prm in mpu
2528  */
2529
2530 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2531         .name   = "prcm",
2532 };
2533
2534 /* prcm_mpu */
2535 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2536         .name           = "prcm_mpu",
2537         .class          = &omap44xx_prcm_hwmod_class,
2538         .clkdm_name     = "l4_wkup_clkdm",
2539 };
2540
2541 /* cm_core_aon */
2542 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2543         .name           = "cm_core_aon",
2544         .class          = &omap44xx_prcm_hwmod_class,
2545 };
2546
2547 /* cm_core */
2548 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2549         .name           = "cm_core",
2550         .class          = &omap44xx_prcm_hwmod_class,
2551 };
2552
2553 /* prm */
2554 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2555         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2556         { .irq = -1 }
2557 };
2558
2559 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2560         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2561         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2562 };
2563
2564 static struct omap_hwmod omap44xx_prm_hwmod = {
2565         .name           = "prm",
2566         .class          = &omap44xx_prcm_hwmod_class,
2567         .mpu_irqs       = omap44xx_prm_irqs,
2568         .rst_lines      = omap44xx_prm_resets,
2569         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2570 };
2571
2572 /*
2573  * 'scrm' class
2574  * system clock and reset manager
2575  */
2576
2577 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2578         .name   = "scrm",
2579 };
2580
2581 /* scrm */
2582 static struct omap_hwmod omap44xx_scrm_hwmod = {
2583         .name           = "scrm",
2584         .class          = &omap44xx_scrm_hwmod_class,
2585         .clkdm_name     = "l4_wkup_clkdm",
2586 };
2587
2588 /*
2589  * 'sl2if' class
2590  * shared level 2 memory interface
2591  */
2592
2593 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2594         .name   = "sl2if",
2595 };
2596
2597 /* sl2if */
2598 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2599         .name           = "sl2if",
2600         .class          = &omap44xx_sl2if_hwmod_class,
2601         .clkdm_name     = "ivahd_clkdm",
2602         .prcm = {
2603                 .omap4 = {
2604                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2605                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2606                         .modulemode   = MODULEMODE_HWCTRL,
2607                 },
2608         },
2609 };
2610
2611 /*
2612  * 'slimbus' class
2613  * bidirectional, multi-drop, multi-channel two-line serial interface between
2614  * the device and external components
2615  */
2616
2617 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2618         .rev_offs       = 0x0000,
2619         .sysc_offs      = 0x0010,
2620         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2621                            SYSC_HAS_SOFTRESET),
2622         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2623                            SIDLE_SMART_WKUP),
2624         .sysc_fields    = &omap_hwmod_sysc_type2,
2625 };
2626
2627 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2628         .name   = "slimbus",
2629         .sysc   = &omap44xx_slimbus_sysc,
2630 };
2631
2632 /* slimbus1 */
2633 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2634         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2635         { .irq = -1 }
2636 };
2637
2638 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2639         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2640         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2641         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2642         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2643         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2644         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2645         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2647         { .dma_req = -1 }
2648 };
2649
2650 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2651         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2652         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2653         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2654         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2655 };
2656
2657 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2658         .name           = "slimbus1",
2659         .class          = &omap44xx_slimbus_hwmod_class,
2660         .clkdm_name     = "abe_clkdm",
2661         .mpu_irqs       = omap44xx_slimbus1_irqs,
2662         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2663         .prcm = {
2664                 .omap4 = {
2665                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2666                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2667                         .modulemode   = MODULEMODE_SWCTRL,
2668                 },
2669         },
2670         .opt_clks       = slimbus1_opt_clks,
2671         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2672 };
2673
2674 /* slimbus2 */
2675 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2676         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2677         { .irq = -1 }
2678 };
2679
2680 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2681         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2682         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2683         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2684         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2685         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2686         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2687         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2689         { .dma_req = -1 }
2690 };
2691
2692 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2693         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2694         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2695         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2696 };
2697
2698 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2699         .name           = "slimbus2",
2700         .class          = &omap44xx_slimbus_hwmod_class,
2701         .clkdm_name     = "l4_per_clkdm",
2702         .mpu_irqs       = omap44xx_slimbus2_irqs,
2703         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2704         .prcm = {
2705                 .omap4 = {
2706                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2707                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2708                         .modulemode   = MODULEMODE_SWCTRL,
2709                 },
2710         },
2711         .opt_clks       = slimbus2_opt_clks,
2712         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2713 };
2714
2715 /*
2716  * 'smartreflex' class
2717  * smartreflex module (monitor silicon performance and outputs a measure of
2718  * performance error)
2719  */
2720
2721 /* The IP is not compliant to type1 / type2 scheme */
2722 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2723         .sidle_shift    = 24,
2724         .enwkup_shift   = 26,
2725 };
2726
2727 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2728         .sysc_offs      = 0x0038,
2729         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2731                            SIDLE_SMART_WKUP),
2732         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2733 };
2734
2735 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2736         .name   = "smartreflex",
2737         .sysc   = &omap44xx_smartreflex_sysc,
2738         .rev    = 2,
2739 };
2740
2741 /* smartreflex_core */
2742 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2743         .sensor_voltdm_name   = "core",
2744 };
2745
2746 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2747         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2748         { .irq = -1 }
2749 };
2750
2751 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2752         .name           = "smartreflex_core",
2753         .class          = &omap44xx_smartreflex_hwmod_class,
2754         .clkdm_name     = "l4_ao_clkdm",
2755         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2756
2757         .main_clk       = "smartreflex_core_fck",
2758         .prcm = {
2759                 .omap4 = {
2760                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2761                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2762                         .modulemode   = MODULEMODE_SWCTRL,
2763                 },
2764         },
2765         .dev_attr       = &smartreflex_core_dev_attr,
2766 };
2767
2768 /* smartreflex_iva */
2769 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2770         .sensor_voltdm_name     = "iva",
2771 };
2772
2773 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2774         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2775         { .irq = -1 }
2776 };
2777
2778 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2779         .name           = "smartreflex_iva",
2780         .class          = &omap44xx_smartreflex_hwmod_class,
2781         .clkdm_name     = "l4_ao_clkdm",
2782         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2783         .main_clk       = "smartreflex_iva_fck",
2784         .prcm = {
2785                 .omap4 = {
2786                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2787                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2788                         .modulemode   = MODULEMODE_SWCTRL,
2789                 },
2790         },
2791         .dev_attr       = &smartreflex_iva_dev_attr,
2792 };
2793
2794 /* smartreflex_mpu */
2795 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2796         .sensor_voltdm_name     = "mpu",
2797 };
2798
2799 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2800         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2801         { .irq = -1 }
2802 };
2803
2804 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2805         .name           = "smartreflex_mpu",
2806         .class          = &omap44xx_smartreflex_hwmod_class,
2807         .clkdm_name     = "l4_ao_clkdm",
2808         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2809         .main_clk       = "smartreflex_mpu_fck",
2810         .prcm = {
2811                 .omap4 = {
2812                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2813                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2814                         .modulemode   = MODULEMODE_SWCTRL,
2815                 },
2816         },
2817         .dev_attr       = &smartreflex_mpu_dev_attr,
2818 };
2819
2820 /*
2821  * 'spinlock' class
2822  * spinlock provides hardware assistance for synchronizing the processes
2823  * running on multiple processors
2824  */
2825
2826 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2827         .rev_offs       = 0x0000,
2828         .sysc_offs      = 0x0010,
2829         .syss_offs      = 0x0014,
2830         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2831                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2832                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2833         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2834                            SIDLE_SMART_WKUP),
2835         .sysc_fields    = &omap_hwmod_sysc_type1,
2836 };
2837
2838 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2839         .name   = "spinlock",
2840         .sysc   = &omap44xx_spinlock_sysc,
2841 };
2842
2843 /* spinlock */
2844 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2845         .name           = "spinlock",
2846         .class          = &omap44xx_spinlock_hwmod_class,
2847         .clkdm_name     = "l4_cfg_clkdm",
2848         .prcm = {
2849                 .omap4 = {
2850                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2851                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2852                 },
2853         },
2854 };
2855
2856 /*
2857  * 'timer' class
2858  * general purpose timer module with accurate 1ms tick
2859  * This class contains several variants: ['timer_1ms', 'timer']
2860  */
2861
2862 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2863         .rev_offs       = 0x0000,
2864         .sysc_offs      = 0x0010,
2865         .syss_offs      = 0x0014,
2866         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2867                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2868                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2869                            SYSS_HAS_RESET_STATUS),
2870         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2871         .sysc_fields    = &omap_hwmod_sysc_type1,
2872 };
2873
2874 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2875         .name   = "timer",
2876         .sysc   = &omap44xx_timer_1ms_sysc,
2877 };
2878
2879 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2880         .rev_offs       = 0x0000,
2881         .sysc_offs      = 0x0010,
2882         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2883                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2884         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2885                            SIDLE_SMART_WKUP),
2886         .sysc_fields    = &omap_hwmod_sysc_type2,
2887 };
2888
2889 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2890         .name   = "timer",
2891         .sysc   = &omap44xx_timer_sysc,
2892 };
2893
2894 /* always-on timers dev attribute */
2895 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2896         .timer_capability       = OMAP_TIMER_ALWON,
2897 };
2898
2899 /* pwm timers dev attribute */
2900 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2901         .timer_capability       = OMAP_TIMER_HAS_PWM,
2902 };
2903
2904 /* timer1 */
2905 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2906         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2907         { .irq = -1 }
2908 };
2909
2910 static struct omap_hwmod omap44xx_timer1_hwmod = {
2911         .name           = "timer1",
2912         .class          = &omap44xx_timer_1ms_hwmod_class,
2913         .clkdm_name     = "l4_wkup_clkdm",
2914         .mpu_irqs       = omap44xx_timer1_irqs,
2915         .main_clk       = "timer1_fck",
2916         .prcm = {
2917                 .omap4 = {
2918                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2919                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2920                         .modulemode   = MODULEMODE_SWCTRL,
2921                 },
2922         },
2923         .dev_attr       = &capability_alwon_dev_attr,
2924 };
2925
2926 /* timer2 */
2927 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2928         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2929         { .irq = -1 }
2930 };
2931
2932 static struct omap_hwmod omap44xx_timer2_hwmod = {
2933         .name           = "timer2",
2934         .class          = &omap44xx_timer_1ms_hwmod_class,
2935         .clkdm_name     = "l4_per_clkdm",
2936         .mpu_irqs       = omap44xx_timer2_irqs,
2937         .main_clk       = "timer2_fck",
2938         .prcm = {
2939                 .omap4 = {
2940                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2941                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2942                         .modulemode   = MODULEMODE_SWCTRL,
2943                 },
2944         },
2945 };
2946
2947 /* timer3 */
2948 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2949         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2950         { .irq = -1 }
2951 };
2952
2953 static struct omap_hwmod omap44xx_timer3_hwmod = {
2954         .name           = "timer3",
2955         .class          = &omap44xx_timer_hwmod_class,
2956         .clkdm_name     = "l4_per_clkdm",
2957         .mpu_irqs       = omap44xx_timer3_irqs,
2958         .main_clk       = "timer3_fck",
2959         .prcm = {
2960                 .omap4 = {
2961                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2962                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2963                         .modulemode   = MODULEMODE_SWCTRL,
2964                 },
2965         },
2966 };
2967
2968 /* timer4 */
2969 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2970         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2971         { .irq = -1 }
2972 };
2973
2974 static struct omap_hwmod omap44xx_timer4_hwmod = {
2975         .name           = "timer4",
2976         .class          = &omap44xx_timer_hwmod_class,
2977         .clkdm_name     = "l4_per_clkdm",
2978         .mpu_irqs       = omap44xx_timer4_irqs,
2979         .main_clk       = "timer4_fck",
2980         .prcm = {
2981                 .omap4 = {
2982                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2983                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2984                         .modulemode   = MODULEMODE_SWCTRL,
2985                 },
2986         },
2987 };
2988
2989 /* timer5 */
2990 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2991         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2992         { .irq = -1 }
2993 };
2994
2995 static struct omap_hwmod omap44xx_timer5_hwmod = {
2996         .name           = "timer5",
2997         .class          = &omap44xx_timer_hwmod_class,
2998         .clkdm_name     = "abe_clkdm",
2999         .mpu_irqs       = omap44xx_timer5_irqs,
3000         .main_clk       = "timer5_fck",
3001         .prcm = {
3002                 .omap4 = {
3003                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3004                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3005                         .modulemode   = MODULEMODE_SWCTRL,
3006                 },
3007         },
3008 };
3009
3010 /* timer6 */
3011 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3012         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3013         { .irq = -1 }
3014 };
3015
3016 static struct omap_hwmod omap44xx_timer6_hwmod = {
3017         .name           = "timer6",
3018         .class          = &omap44xx_timer_hwmod_class,
3019         .clkdm_name     = "abe_clkdm",
3020         .mpu_irqs       = omap44xx_timer6_irqs,
3021
3022         .main_clk       = "timer6_fck",
3023         .prcm = {
3024                 .omap4 = {
3025                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3026                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3027                         .modulemode   = MODULEMODE_SWCTRL,
3028                 },
3029         },
3030 };
3031
3032 /* timer7 */
3033 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3034         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3035         { .irq = -1 }
3036 };
3037
3038 static struct omap_hwmod omap44xx_timer7_hwmod = {
3039         .name           = "timer7",
3040         .class          = &omap44xx_timer_hwmod_class,
3041         .clkdm_name     = "abe_clkdm",
3042         .mpu_irqs       = omap44xx_timer7_irqs,
3043         .main_clk       = "timer7_fck",
3044         .prcm = {
3045                 .omap4 = {
3046                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3047                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3048                         .modulemode   = MODULEMODE_SWCTRL,
3049                 },
3050         },
3051 };
3052
3053 /* timer8 */
3054 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3055         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3056         { .irq = -1 }
3057 };
3058
3059 static struct omap_hwmod omap44xx_timer8_hwmod = {
3060         .name           = "timer8",
3061         .class          = &omap44xx_timer_hwmod_class,
3062         .clkdm_name     = "abe_clkdm",
3063         .mpu_irqs       = omap44xx_timer8_irqs,
3064         .main_clk       = "timer8_fck",
3065         .prcm = {
3066                 .omap4 = {
3067                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3068                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3069                         .modulemode   = MODULEMODE_SWCTRL,
3070                 },
3071         },
3072         .dev_attr       = &capability_pwm_dev_attr,
3073 };
3074
3075 /* timer9 */
3076 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3077         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3078         { .irq = -1 }
3079 };
3080
3081 static struct omap_hwmod omap44xx_timer9_hwmod = {
3082         .name           = "timer9",
3083         .class          = &omap44xx_timer_hwmod_class,
3084         .clkdm_name     = "l4_per_clkdm",
3085         .mpu_irqs       = omap44xx_timer9_irqs,
3086         .main_clk       = "timer9_fck",
3087         .prcm = {
3088                 .omap4 = {
3089                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3090                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3091                         .modulemode   = MODULEMODE_SWCTRL,
3092                 },
3093         },
3094         .dev_attr       = &capability_pwm_dev_attr,
3095 };
3096
3097 /* timer10 */
3098 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3099         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3100         { .irq = -1 }
3101 };
3102
3103 static struct omap_hwmod omap44xx_timer10_hwmod = {
3104         .name           = "timer10",
3105         .class          = &omap44xx_timer_1ms_hwmod_class,
3106         .clkdm_name     = "l4_per_clkdm",
3107         .mpu_irqs       = omap44xx_timer10_irqs,
3108         .main_clk       = "timer10_fck",
3109         .prcm = {
3110                 .omap4 = {
3111                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3112                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3113                         .modulemode   = MODULEMODE_SWCTRL,
3114                 },
3115         },
3116         .dev_attr       = &capability_pwm_dev_attr,
3117 };
3118
3119 /* timer11 */
3120 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3121         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3122         { .irq = -1 }
3123 };
3124
3125 static struct omap_hwmod omap44xx_timer11_hwmod = {
3126         .name           = "timer11",
3127         .class          = &omap44xx_timer_hwmod_class,
3128         .clkdm_name     = "l4_per_clkdm",
3129         .mpu_irqs       = omap44xx_timer11_irqs,
3130         .main_clk       = "timer11_fck",
3131         .prcm = {
3132                 .omap4 = {
3133                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3134                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3135                         .modulemode   = MODULEMODE_SWCTRL,
3136                 },
3137         },
3138         .dev_attr       = &capability_pwm_dev_attr,
3139 };
3140
3141 /*
3142  * 'uart' class
3143  * universal asynchronous receiver/transmitter (uart)
3144  */
3145
3146 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3147         .rev_offs       = 0x0050,
3148         .sysc_offs      = 0x0054,
3149         .syss_offs      = 0x0058,
3150         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3151                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3152                            SYSS_HAS_RESET_STATUS),
3153         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3154                            SIDLE_SMART_WKUP),
3155         .sysc_fields    = &omap_hwmod_sysc_type1,
3156 };
3157
3158 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3159         .name   = "uart",
3160         .sysc   = &omap44xx_uart_sysc,
3161 };
3162
3163 /* uart1 */
3164 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3165         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3166         { .irq = -1 }
3167 };
3168
3169 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3170         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3171         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3172         { .dma_req = -1 }
3173 };
3174
3175 static struct omap_hwmod omap44xx_uart1_hwmod = {
3176         .name           = "uart1",
3177         .class          = &omap44xx_uart_hwmod_class,
3178         .clkdm_name     = "l4_per_clkdm",
3179         .mpu_irqs       = omap44xx_uart1_irqs,
3180         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3181         .main_clk       = "uart1_fck",
3182         .prcm = {
3183                 .omap4 = {
3184                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3185                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3186                         .modulemode   = MODULEMODE_SWCTRL,
3187                 },
3188         },
3189 };
3190
3191 /* uart2 */
3192 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3193         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3194         { .irq = -1 }
3195 };
3196
3197 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3198         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3199         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3200         { .dma_req = -1 }
3201 };
3202
3203 static struct omap_hwmod omap44xx_uart2_hwmod = {
3204         .name           = "uart2",
3205         .class          = &omap44xx_uart_hwmod_class,
3206         .clkdm_name     = "l4_per_clkdm",
3207         .mpu_irqs       = omap44xx_uart2_irqs,
3208         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3209         .main_clk       = "uart2_fck",
3210         .prcm = {
3211                 .omap4 = {
3212                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3213                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3214                         .modulemode   = MODULEMODE_SWCTRL,
3215                 },
3216         },
3217 };
3218
3219 /* uart3 */
3220 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3221         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3222         { .irq = -1 }
3223 };
3224
3225 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3226         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3227         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3228         { .dma_req = -1 }
3229 };
3230
3231 static struct omap_hwmod omap44xx_uart3_hwmod = {
3232         .name           = "uart3",
3233         .class          = &omap44xx_uart_hwmod_class,
3234         .clkdm_name     = "l4_per_clkdm",
3235         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3236         .mpu_irqs       = omap44xx_uart3_irqs,
3237         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3238         .main_clk       = "uart3_fck",
3239         .prcm = {
3240                 .omap4 = {
3241                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3242                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3243                         .modulemode   = MODULEMODE_SWCTRL,
3244                 },
3245         },
3246 };
3247
3248 /* uart4 */
3249 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3250         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3251         { .irq = -1 }
3252 };
3253
3254 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3255         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3256         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3257         { .dma_req = -1 }
3258 };
3259
3260 static struct omap_hwmod omap44xx_uart4_hwmod = {
3261         .name           = "uart4",
3262         .class          = &omap44xx_uart_hwmod_class,
3263         .clkdm_name     = "l4_per_clkdm",
3264         .mpu_irqs       = omap44xx_uart4_irqs,
3265         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3266         .main_clk       = "uart4_fck",
3267         .prcm = {
3268                 .omap4 = {
3269                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3270                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3271                         .modulemode   = MODULEMODE_SWCTRL,
3272                 },
3273         },
3274 };
3275
3276 /*
3277  * 'usb_host_fs' class
3278  * full-speed usb host controller
3279  */
3280
3281 /* The IP is not compliant to type1 / type2 scheme */
3282 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3283         .midle_shift    = 4,
3284         .sidle_shift    = 2,
3285         .srst_shift     = 1,
3286 };
3287
3288 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3289         .rev_offs       = 0x0000,
3290         .sysc_offs      = 0x0210,
3291         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3292                            SYSC_HAS_SOFTRESET),
3293         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3294                            SIDLE_SMART_WKUP),
3295         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3296 };
3297
3298 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3299         .name   = "usb_host_fs",
3300         .sysc   = &omap44xx_usb_host_fs_sysc,
3301 };
3302
3303 /* usb_host_fs */
3304 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3305         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3306         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3307         { .irq = -1 }
3308 };
3309
3310 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3311         .name           = "usb_host_fs",
3312         .class          = &omap44xx_usb_host_fs_hwmod_class,
3313         .clkdm_name     = "l3_init_clkdm",
3314         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3315         .main_clk       = "usb_host_fs_fck",
3316         .prcm = {
3317                 .omap4 = {
3318                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3319                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3320                         .modulemode   = MODULEMODE_SWCTRL,
3321                 },
3322         },
3323 };
3324
3325 /*
3326  * 'usb_host_hs' class
3327  * high-speed multi-port usb host controller
3328  */
3329
3330 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3331         .rev_offs       = 0x0000,
3332         .sysc_offs      = 0x0010,
3333         .syss_offs      = 0x0014,
3334         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3335                            SYSC_HAS_SOFTRESET),
3336         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3337                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3338                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3339         .sysc_fields    = &omap_hwmod_sysc_type2,
3340 };
3341
3342 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3343         .name   = "usb_host_hs",
3344         .sysc   = &omap44xx_usb_host_hs_sysc,
3345 };
3346
3347 /* usb_host_hs */
3348 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3349         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3350         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3351         { .irq = -1 }
3352 };
3353
3354 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3355         .name           = "usb_host_hs",
3356         .class          = &omap44xx_usb_host_hs_hwmod_class,
3357         .clkdm_name     = "l3_init_clkdm",
3358         .main_clk       = "usb_host_hs_fck",
3359         .prcm = {
3360                 .omap4 = {
3361                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3362                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3363                         .modulemode   = MODULEMODE_SWCTRL,
3364                 },
3365         },
3366         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3367
3368         /*
3369          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3370          * id: i660
3371          *
3372          * Description:
3373          * In the following configuration :
3374          * - USBHOST module is set to smart-idle mode
3375          * - PRCM asserts idle_req to the USBHOST module ( This typically
3376          *   happens when the system is going to a low power mode : all ports
3377          *   have been suspended, the master part of the USBHOST module has
3378          *   entered the standby state, and SW has cut the functional clocks)
3379          * - an USBHOST interrupt occurs before the module is able to answer
3380          *   idle_ack, typically a remote wakeup IRQ.
3381          * Then the USB HOST module will enter a deadlock situation where it
3382          * is no more accessible nor functional.
3383          *
3384          * Workaround:
3385          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3386          */
3387
3388         /*
3389          * Errata: USB host EHCI may stall when entering smart-standby mode
3390          * Id: i571
3391          *
3392          * Description:
3393          * When the USBHOST module is set to smart-standby mode, and when it is
3394          * ready to enter the standby state (i.e. all ports are suspended and
3395          * all attached devices are in suspend mode), then it can wrongly assert
3396          * the Mstandby signal too early while there are still some residual OCP
3397          * transactions ongoing. If this condition occurs, the internal state
3398          * machine may go to an undefined state and the USB link may be stuck
3399          * upon the next resume.
3400          *
3401          * Workaround:
3402          * Don't use smart standby; use only force standby,
3403          * hence HWMOD_SWSUP_MSTANDBY
3404          */
3405
3406         /*
3407          * During system boot; If the hwmod framework resets the module
3408          * the module will have smart idle settings; which can lead to deadlock
3409          * (above Errata Id:i660); so, dont reset the module during boot;
3410          * Use HWMOD_INIT_NO_RESET.
3411          */
3412
3413         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3414                           HWMOD_INIT_NO_RESET,
3415 };
3416
3417 /*
3418  * 'usb_otg_hs' class
3419  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3420  */
3421
3422 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3423         .rev_offs       = 0x0400,
3424         .sysc_offs      = 0x0404,
3425         .syss_offs      = 0x0408,
3426         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3427                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3428                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3429         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3430                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3431                            MSTANDBY_SMART),
3432         .sysc_fields    = &omap_hwmod_sysc_type1,
3433 };
3434
3435 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3436         .name   = "usb_otg_hs",
3437         .sysc   = &omap44xx_usb_otg_hs_sysc,
3438 };
3439
3440 /* usb_otg_hs */
3441 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3442         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3443         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3444         { .irq = -1 }
3445 };
3446
3447 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3448         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3449 };
3450
3451 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3452         .name           = "usb_otg_hs",
3453         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3454         .clkdm_name     = "l3_init_clkdm",
3455         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3456         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3457         .main_clk       = "usb_otg_hs_ick",
3458         .prcm = {
3459                 .omap4 = {
3460                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3461                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3462                         .modulemode   = MODULEMODE_HWCTRL,
3463                 },
3464         },
3465         .opt_clks       = usb_otg_hs_opt_clks,
3466         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3467 };
3468
3469 /*
3470  * 'usb_tll_hs' class
3471  * usb_tll_hs module is the adapter on the usb_host_hs ports
3472  */
3473
3474 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3475         .rev_offs       = 0x0000,
3476         .sysc_offs      = 0x0010,
3477         .syss_offs      = 0x0014,
3478         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3479                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3480                            SYSC_HAS_AUTOIDLE),
3481         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3482         .sysc_fields    = &omap_hwmod_sysc_type1,
3483 };
3484
3485 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3486         .name   = "usb_tll_hs",
3487         .sysc   = &omap44xx_usb_tll_hs_sysc,
3488 };
3489
3490 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3491         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3492         { .irq = -1 }
3493 };
3494
3495 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3496         .name           = "usb_tll_hs",
3497         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3498         .clkdm_name     = "l3_init_clkdm",
3499         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3500         .main_clk       = "usb_tll_hs_ick",
3501         .prcm = {
3502                 .omap4 = {
3503                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3504                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3505                         .modulemode   = MODULEMODE_HWCTRL,
3506                 },
3507         },
3508 };
3509
3510 /*
3511  * 'wd_timer' class
3512  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3513  * overflow condition
3514  */
3515
3516 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3517         .rev_offs       = 0x0000,
3518         .sysc_offs      = 0x0010,
3519         .syss_offs      = 0x0014,
3520         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3521                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3522         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3523                            SIDLE_SMART_WKUP),
3524         .sysc_fields    = &omap_hwmod_sysc_type1,
3525 };
3526
3527 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3528         .name           = "wd_timer",
3529         .sysc           = &omap44xx_wd_timer_sysc,
3530         .pre_shutdown   = &omap2_wd_timer_disable,
3531         .reset          = &omap2_wd_timer_reset,
3532 };
3533
3534 /* wd_timer2 */
3535 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3536         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3537         { .irq = -1 }
3538 };
3539
3540 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3541         .name           = "wd_timer2",
3542         .class          = &omap44xx_wd_timer_hwmod_class,
3543         .clkdm_name     = "l4_wkup_clkdm",
3544         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3545         .main_clk       = "wd_timer2_fck",
3546         .prcm = {
3547                 .omap4 = {
3548                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3549                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3550                         .modulemode   = MODULEMODE_SWCTRL,
3551                 },
3552         },
3553 };
3554
3555 /* wd_timer3 */
3556 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3557         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3558         { .irq = -1 }
3559 };
3560
3561 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3562         .name           = "wd_timer3",
3563         .class          = &omap44xx_wd_timer_hwmod_class,
3564         .clkdm_name     = "abe_clkdm",
3565         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3566         .main_clk       = "wd_timer3_fck",
3567         .prcm = {
3568                 .omap4 = {
3569                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3570                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3571                         .modulemode   = MODULEMODE_SWCTRL,
3572                 },
3573         },
3574 };
3575
3576
3577 /*
3578  * interfaces
3579  */
3580
3581 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3582         {
3583                 .pa_start       = 0x4a204000,
3584                 .pa_end         = 0x4a2040ff,
3585                 .flags          = ADDR_TYPE_RT
3586         },
3587         { }
3588 };
3589
3590 /* c2c -> c2c_target_fw */
3591 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3592         .master         = &omap44xx_c2c_hwmod,
3593         .slave          = &omap44xx_c2c_target_fw_hwmod,
3594         .clk            = "div_core_ck",
3595         .addr           = omap44xx_c2c_target_fw_addrs,
3596         .user           = OCP_USER_MPU,
3597 };
3598
3599 /* l4_cfg -> c2c_target_fw */
3600 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3601         .master         = &omap44xx_l4_cfg_hwmod,
3602         .slave          = &omap44xx_c2c_target_fw_hwmod,
3603         .clk            = "l4_div_ck",
3604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3605 };
3606
3607 /* l3_main_1 -> dmm */
3608 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3609         .master         = &omap44xx_l3_main_1_hwmod,
3610         .slave          = &omap44xx_dmm_hwmod,
3611         .clk            = "l3_div_ck",
3612         .user           = OCP_USER_SDMA,
3613 };
3614
3615 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3616         {
3617                 .pa_start       = 0x4e000000,
3618                 .pa_end         = 0x4e0007ff,
3619                 .flags          = ADDR_TYPE_RT
3620         },
3621         { }
3622 };
3623
3624 /* mpu -> dmm */
3625 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3626         .master         = &omap44xx_mpu_hwmod,
3627         .slave          = &omap44xx_dmm_hwmod,
3628         .clk            = "l3_div_ck",
3629         .addr           = omap44xx_dmm_addrs,
3630         .user           = OCP_USER_MPU,
3631 };
3632
3633 /* c2c -> emif_fw */
3634 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3635         .master         = &omap44xx_c2c_hwmod,
3636         .slave          = &omap44xx_emif_fw_hwmod,
3637         .clk            = "div_core_ck",
3638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3640
3641 /* dmm -> emif_fw */
3642 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3643         .master         = &omap44xx_dmm_hwmod,
3644         .slave          = &omap44xx_emif_fw_hwmod,
3645         .clk            = "l3_div_ck",
3646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3648
3649 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3650         {
3651                 .pa_start       = 0x4a20c000,
3652                 .pa_end         = 0x4a20c0ff,
3653                 .flags          = ADDR_TYPE_RT
3654         },
3655         { }
3656 };
3657
3658 /* l4_cfg -> emif_fw */
3659 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3660         .master         = &omap44xx_l4_cfg_hwmod,
3661         .slave          = &omap44xx_emif_fw_hwmod,
3662         .clk            = "l4_div_ck",
3663         .addr           = omap44xx_emif_fw_addrs,
3664         .user           = OCP_USER_MPU,
3665 };
3666
3667 /* iva -> l3_instr */
3668 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3669         .master         = &omap44xx_iva_hwmod,
3670         .slave          = &omap44xx_l3_instr_hwmod,
3671         .clk            = "l3_div_ck",
3672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3673 };
3674
3675 /* l3_main_3 -> l3_instr */
3676 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3677         .master         = &omap44xx_l3_main_3_hwmod,
3678         .slave          = &omap44xx_l3_instr_hwmod,
3679         .clk            = "l3_div_ck",
3680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3681 };
3682
3683 /* ocp_wp_noc -> l3_instr */
3684 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3685         .master         = &omap44xx_ocp_wp_noc_hwmod,
3686         .slave          = &omap44xx_l3_instr_hwmod,
3687         .clk            = "l3_div_ck",
3688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* dsp -> l3_main_1 */
3692 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3693         .master         = &omap44xx_dsp_hwmod,
3694         .slave          = &omap44xx_l3_main_1_hwmod,
3695         .clk            = "l3_div_ck",
3696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3697 };
3698
3699 /* dss -> l3_main_1 */
3700 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3701         .master         = &omap44xx_dss_hwmod,
3702         .slave          = &omap44xx_l3_main_1_hwmod,
3703         .clk            = "l3_div_ck",
3704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* l3_main_2 -> l3_main_1 */
3708 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3709         .master         = &omap44xx_l3_main_2_hwmod,
3710         .slave          = &omap44xx_l3_main_1_hwmod,
3711         .clk            = "l3_div_ck",
3712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 /* l4_cfg -> l3_main_1 */
3716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3717         .master         = &omap44xx_l4_cfg_hwmod,
3718         .slave          = &omap44xx_l3_main_1_hwmod,
3719         .clk            = "l4_div_ck",
3720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3721 };
3722
3723 /* mmc1 -> l3_main_1 */
3724 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3725         .master         = &omap44xx_mmc1_hwmod,
3726         .slave          = &omap44xx_l3_main_1_hwmod,
3727         .clk            = "l3_div_ck",
3728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3729 };
3730
3731 /* mmc2 -> l3_main_1 */
3732 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3733         .master         = &omap44xx_mmc2_hwmod,
3734         .slave          = &omap44xx_l3_main_1_hwmod,
3735         .clk            = "l3_div_ck",
3736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3740         {
3741                 .pa_start       = 0x44000000,
3742                 .pa_end         = 0x44000fff,
3743                 .flags          = ADDR_TYPE_RT
3744         },
3745         { }
3746 };
3747
3748 /* mpu -> l3_main_1 */
3749 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3750         .master         = &omap44xx_mpu_hwmod,
3751         .slave          = &omap44xx_l3_main_1_hwmod,
3752         .clk            = "l3_div_ck",
3753         .addr           = omap44xx_l3_main_1_addrs,
3754         .user           = OCP_USER_MPU,
3755 };
3756
3757 /* c2c_target_fw -> l3_main_2 */
3758 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3759         .master         = &omap44xx_c2c_target_fw_hwmod,
3760         .slave          = &omap44xx_l3_main_2_hwmod,
3761         .clk            = "l3_div_ck",
3762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3764
3765 /* debugss -> l3_main_2 */
3766 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3767         .master         = &omap44xx_debugss_hwmod,
3768         .slave          = &omap44xx_l3_main_2_hwmod,
3769         .clk            = "dbgclk_mux_ck",
3770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3772
3773 /* dma_system -> l3_main_2 */
3774 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3775         .master         = &omap44xx_dma_system_hwmod,
3776         .slave          = &omap44xx_l3_main_2_hwmod,
3777         .clk            = "l3_div_ck",
3778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3780
3781 /* fdif -> l3_main_2 */
3782 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3783         .master         = &omap44xx_fdif_hwmod,
3784         .slave          = &omap44xx_l3_main_2_hwmod,
3785         .clk            = "l3_div_ck",
3786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3788
3789 /* gpu -> l3_main_2 */
3790 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3791         .master         = &omap44xx_gpu_hwmod,
3792         .slave          = &omap44xx_l3_main_2_hwmod,
3793         .clk            = "l3_div_ck",
3794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3796
3797 /* hsi -> l3_main_2 */
3798 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3799         .master         = &omap44xx_hsi_hwmod,
3800         .slave          = &omap44xx_l3_main_2_hwmod,
3801         .clk            = "l3_div_ck",
3802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3803 };
3804
3805 /* ipu -> l3_main_2 */
3806 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3807         .master         = &omap44xx_ipu_hwmod,
3808         .slave          = &omap44xx_l3_main_2_hwmod,
3809         .clk            = "l3_div_ck",
3810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3811 };
3812
3813 /* iss -> l3_main_2 */
3814 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3815         .master         = &omap44xx_iss_hwmod,
3816         .slave          = &omap44xx_l3_main_2_hwmod,
3817         .clk            = "l3_div_ck",
3818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3819 };
3820
3821 /* iva -> l3_main_2 */
3822 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3823         .master         = &omap44xx_iva_hwmod,
3824         .slave          = &omap44xx_l3_main_2_hwmod,
3825         .clk            = "l3_div_ck",
3826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3827 };
3828
3829 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3830         {
3831                 .pa_start       = 0x44800000,
3832                 .pa_end         = 0x44801fff,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835         { }
3836 };
3837
3838 /* l3_main_1 -> l3_main_2 */
3839 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3840         .master         = &omap44xx_l3_main_1_hwmod,
3841         .slave          = &omap44xx_l3_main_2_hwmod,
3842         .clk            = "l3_div_ck",
3843         .addr           = omap44xx_l3_main_2_addrs,
3844         .user           = OCP_USER_MPU,
3845 };
3846
3847 /* l4_cfg -> l3_main_2 */
3848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3849         .master         = &omap44xx_l4_cfg_hwmod,
3850         .slave          = &omap44xx_l3_main_2_hwmod,
3851         .clk            = "l4_div_ck",
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* usb_host_fs -> l3_main_2 */
3856 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3857         .master         = &omap44xx_usb_host_fs_hwmod,
3858         .slave          = &omap44xx_l3_main_2_hwmod,
3859         .clk            = "l3_div_ck",
3860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3861 };
3862
3863 /* usb_host_hs -> l3_main_2 */
3864 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3865         .master         = &omap44xx_usb_host_hs_hwmod,
3866         .slave          = &omap44xx_l3_main_2_hwmod,
3867         .clk            = "l3_div_ck",
3868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3870
3871 /* usb_otg_hs -> l3_main_2 */
3872 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3873         .master         = &omap44xx_usb_otg_hs_hwmod,
3874         .slave          = &omap44xx_l3_main_2_hwmod,
3875         .clk            = "l3_div_ck",
3876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3877 };
3878
3879 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3880         {
3881                 .pa_start       = 0x45000000,
3882                 .pa_end         = 0x45000fff,
3883                 .flags          = ADDR_TYPE_RT
3884         },
3885         { }
3886 };
3887
3888 /* l3_main_1 -> l3_main_3 */
3889 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3890         .master         = &omap44xx_l3_main_1_hwmod,
3891         .slave          = &omap44xx_l3_main_3_hwmod,
3892         .clk            = "l3_div_ck",
3893         .addr           = omap44xx_l3_main_3_addrs,
3894         .user           = OCP_USER_MPU,
3895 };
3896
3897 /* l3_main_2 -> l3_main_3 */
3898 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3899         .master         = &omap44xx_l3_main_2_hwmod,
3900         .slave          = &omap44xx_l3_main_3_hwmod,
3901         .clk            = "l3_div_ck",
3902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3903 };
3904
3905 /* l4_cfg -> l3_main_3 */
3906 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3907         .master         = &omap44xx_l4_cfg_hwmod,
3908         .slave          = &omap44xx_l3_main_3_hwmod,
3909         .clk            = "l4_div_ck",
3910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 /* aess -> l4_abe */
3914 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3915         .master         = &omap44xx_aess_hwmod,
3916         .slave          = &omap44xx_l4_abe_hwmod,
3917         .clk            = "ocp_abe_iclk",
3918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3919 };
3920
3921 /* dsp -> l4_abe */
3922 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3923         .master         = &omap44xx_dsp_hwmod,
3924         .slave          = &omap44xx_l4_abe_hwmod,
3925         .clk            = "ocp_abe_iclk",
3926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3927 };
3928
3929 /* l3_main_1 -> l4_abe */
3930 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3931         .master         = &omap44xx_l3_main_1_hwmod,
3932         .slave          = &omap44xx_l4_abe_hwmod,
3933         .clk            = "l3_div_ck",
3934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 /* mpu -> l4_abe */
3938 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3939         .master         = &omap44xx_mpu_hwmod,
3940         .slave          = &omap44xx_l4_abe_hwmod,
3941         .clk            = "ocp_abe_iclk",
3942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3944
3945 /* l3_main_1 -> l4_cfg */
3946 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3947         .master         = &omap44xx_l3_main_1_hwmod,
3948         .slave          = &omap44xx_l4_cfg_hwmod,
3949         .clk            = "l3_div_ck",
3950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3951 };
3952
3953 /* l3_main_2 -> l4_per */
3954 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3955         .master         = &omap44xx_l3_main_2_hwmod,
3956         .slave          = &omap44xx_l4_per_hwmod,
3957         .clk            = "l3_div_ck",
3958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* l4_cfg -> l4_wkup */
3962 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3963         .master         = &omap44xx_l4_cfg_hwmod,
3964         .slave          = &omap44xx_l4_wkup_hwmod,
3965         .clk            = "l4_div_ck",
3966         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3967 };
3968
3969 /* mpu -> mpu_private */
3970 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3971         .master         = &omap44xx_mpu_hwmod,
3972         .slave          = &omap44xx_mpu_private_hwmod,
3973         .clk            = "l3_div_ck",
3974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3978         {
3979                 .pa_start       = 0x4a102000,
3980                 .pa_end         = 0x4a10207f,
3981                 .flags          = ADDR_TYPE_RT
3982         },
3983         { }
3984 };
3985
3986 /* l4_cfg -> ocp_wp_noc */
3987 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3988         .master         = &omap44xx_l4_cfg_hwmod,
3989         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3990         .clk            = "l4_div_ck",
3991         .addr           = omap44xx_ocp_wp_noc_addrs,
3992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3994
3995 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3996         {
3997                 .pa_start       = 0x401f1000,
3998                 .pa_end         = 0x401f13ff,
3999                 .flags          = ADDR_TYPE_RT
4000         },
4001         { }
4002 };
4003
4004 /* l4_abe -> aess */
4005 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4006         .master         = &omap44xx_l4_abe_hwmod,
4007         .slave          = &omap44xx_aess_hwmod,
4008         .clk            = "ocp_abe_iclk",
4009         .addr           = omap44xx_aess_addrs,
4010         .user           = OCP_USER_MPU,
4011 };
4012
4013 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4014         {
4015                 .pa_start       = 0x490f1000,
4016                 .pa_end         = 0x490f13ff,
4017                 .flags          = ADDR_TYPE_RT
4018         },
4019         { }
4020 };
4021
4022 /* l4_abe -> aess (dma) */
4023 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4024         .master         = &omap44xx_l4_abe_hwmod,
4025         .slave          = &omap44xx_aess_hwmod,
4026         .clk            = "ocp_abe_iclk",
4027         .addr           = omap44xx_aess_dma_addrs,
4028         .user           = OCP_USER_SDMA,
4029 };
4030
4031 /* l3_main_2 -> c2c */
4032 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4033         .master         = &omap44xx_l3_main_2_hwmod,
4034         .slave          = &omap44xx_c2c_hwmod,
4035         .clk            = "l3_div_ck",
4036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4040         {
4041                 .pa_start       = 0x4a304000,
4042                 .pa_end         = 0x4a30401f,
4043                 .flags          = ADDR_TYPE_RT
4044         },
4045         { }
4046 };
4047
4048 /* l4_wkup -> counter_32k */
4049 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4050         .master         = &omap44xx_l4_wkup_hwmod,
4051         .slave          = &omap44xx_counter_32k_hwmod,
4052         .clk            = "l4_wkup_clk_mux_ck",
4053         .addr           = omap44xx_counter_32k_addrs,
4054         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4055 };
4056
4057 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4058         {
4059                 .pa_start       = 0x4a002000,
4060                 .pa_end         = 0x4a0027ff,
4061                 .flags          = ADDR_TYPE_RT
4062         },
4063         { }
4064 };
4065
4066 /* l4_cfg -> ctrl_module_core */
4067 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4068         .master         = &omap44xx_l4_cfg_hwmod,
4069         .slave          = &omap44xx_ctrl_module_core_hwmod,
4070         .clk            = "l4_div_ck",
4071         .addr           = omap44xx_ctrl_module_core_addrs,
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4076         {
4077                 .pa_start       = 0x4a100000,
4078                 .pa_end         = 0x4a1007ff,
4079                 .flags          = ADDR_TYPE_RT
4080         },
4081         { }
4082 };
4083
4084 /* l4_cfg -> ctrl_module_pad_core */
4085 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4086         .master         = &omap44xx_l4_cfg_hwmod,
4087         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4088         .clk            = "l4_div_ck",
4089         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4091 };
4092
4093 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4094         {
4095                 .pa_start       = 0x4a30c000,
4096                 .pa_end         = 0x4a30c7ff,
4097                 .flags          = ADDR_TYPE_RT
4098         },
4099         { }
4100 };
4101
4102 /* l4_wkup -> ctrl_module_wkup */
4103 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4104         .master         = &omap44xx_l4_wkup_hwmod,
4105         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4106         .clk            = "l4_wkup_clk_mux_ck",
4107         .addr           = omap44xx_ctrl_module_wkup_addrs,
4108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4109 };
4110
4111 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4112         {
4113                 .pa_start       = 0x4a31e000,
4114                 .pa_end         = 0x4a31e7ff,
4115                 .flags          = ADDR_TYPE_RT
4116         },
4117         { }
4118 };
4119
4120 /* l4_wkup -> ctrl_module_pad_wkup */
4121 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4122         .master         = &omap44xx_l4_wkup_hwmod,
4123         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4124         .clk            = "l4_wkup_clk_mux_ck",
4125         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4130         {
4131                 .pa_start       = 0x54160000,
4132                 .pa_end         = 0x54167fff,
4133                 .flags          = ADDR_TYPE_RT
4134         },
4135         { }
4136 };
4137
4138 /* l3_instr -> debugss */
4139 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4140         .master         = &omap44xx_l3_instr_hwmod,
4141         .slave          = &omap44xx_debugss_hwmod,
4142         .clk            = "l3_div_ck",
4143         .addr           = omap44xx_debugss_addrs,
4144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4145 };
4146
4147 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4148         {
4149                 .pa_start       = 0x4a056000,
4150                 .pa_end         = 0x4a056fff,
4151                 .flags          = ADDR_TYPE_RT
4152         },
4153         { }
4154 };
4155
4156 /* l4_cfg -> dma_system */
4157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4158         .master         = &omap44xx_l4_cfg_hwmod,
4159         .slave          = &omap44xx_dma_system_hwmod,
4160         .clk            = "l4_div_ck",
4161         .addr           = omap44xx_dma_system_addrs,
4162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4163 };
4164
4165 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4166         {
4167                 .name           = "mpu",
4168                 .pa_start       = 0x4012e000,
4169                 .pa_end         = 0x4012e07f,
4170                 .flags          = ADDR_TYPE_RT
4171         },
4172         { }
4173 };
4174
4175 /* l4_abe -> dmic */
4176 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4177         .master         = &omap44xx_l4_abe_hwmod,
4178         .slave          = &omap44xx_dmic_hwmod,
4179         .clk            = "ocp_abe_iclk",
4180         .addr           = omap44xx_dmic_addrs,
4181         .user           = OCP_USER_MPU,
4182 };
4183
4184 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4185         {
4186                 .name           = "dma",
4187                 .pa_start       = 0x4902e000,
4188                 .pa_end         = 0x4902e07f,
4189                 .flags          = ADDR_TYPE_RT
4190         },
4191         { }
4192 };
4193
4194 /* l4_abe -> dmic (dma) */
4195 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4196         .master         = &omap44xx_l4_abe_hwmod,
4197         .slave          = &omap44xx_dmic_hwmod,
4198         .clk            = "ocp_abe_iclk",
4199         .addr           = omap44xx_dmic_dma_addrs,
4200         .user           = OCP_USER_SDMA,
4201 };
4202
4203 /* dsp -> iva */
4204 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4205         .master         = &omap44xx_dsp_hwmod,
4206         .slave          = &omap44xx_iva_hwmod,
4207         .clk            = "dpll_iva_m5x2_ck",
4208         .user           = OCP_USER_DSP,
4209 };
4210
4211 /* dsp -> sl2if */
4212 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4213         .master         = &omap44xx_dsp_hwmod,
4214         .slave          = &omap44xx_sl2if_hwmod,
4215         .clk            = "dpll_iva_m5x2_ck",
4216         .user           = OCP_USER_DSP,
4217 };
4218
4219 /* l4_cfg -> dsp */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4221         .master         = &omap44xx_l4_cfg_hwmod,
4222         .slave          = &omap44xx_dsp_hwmod,
4223         .clk            = "l4_div_ck",
4224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4225 };
4226
4227 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4228         {
4229                 .pa_start       = 0x58000000,
4230                 .pa_end         = 0x5800007f,
4231                 .flags          = ADDR_TYPE_RT
4232         },
4233         { }
4234 };
4235
4236 /* l3_main_2 -> dss */
4237 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4238         .master         = &omap44xx_l3_main_2_hwmod,
4239         .slave          = &omap44xx_dss_hwmod,
4240         .clk            = "dss_fck",
4241         .addr           = omap44xx_dss_dma_addrs,
4242         .user           = OCP_USER_SDMA,
4243 };
4244
4245 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4246         {
4247                 .pa_start       = 0x48040000,
4248                 .pa_end         = 0x4804007f,
4249                 .flags          = ADDR_TYPE_RT
4250         },
4251         { }
4252 };
4253
4254 /* l4_per -> dss */
4255 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4256         .master         = &omap44xx_l4_per_hwmod,
4257         .slave          = &omap44xx_dss_hwmod,
4258         .clk            = "l4_div_ck",
4259         .addr           = omap44xx_dss_addrs,
4260         .user           = OCP_USER_MPU,
4261 };
4262
4263 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4264         {
4265                 .pa_start       = 0x58001000,
4266                 .pa_end         = 0x58001fff,
4267                 .flags          = ADDR_TYPE_RT
4268         },
4269         { }
4270 };
4271
4272 /* l3_main_2 -> dss_dispc */
4273 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4274         .master         = &omap44xx_l3_main_2_hwmod,
4275         .slave          = &omap44xx_dss_dispc_hwmod,
4276         .clk            = "dss_fck",
4277         .addr           = omap44xx_dss_dispc_dma_addrs,
4278         .user           = OCP_USER_SDMA,
4279 };
4280
4281 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4282         {
4283                 .pa_start       = 0x48041000,
4284                 .pa_end         = 0x48041fff,
4285                 .flags          = ADDR_TYPE_RT
4286         },
4287         { }
4288 };
4289
4290 /* l4_per -> dss_dispc */
4291 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4292         .master         = &omap44xx_l4_per_hwmod,
4293         .slave          = &omap44xx_dss_dispc_hwmod,
4294         .clk            = "l4_div_ck",
4295         .addr           = omap44xx_dss_dispc_addrs,
4296         .user           = OCP_USER_MPU,
4297 };
4298
4299 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4300         {
4301                 .pa_start       = 0x58004000,
4302                 .pa_end         = 0x580041ff,
4303                 .flags          = ADDR_TYPE_RT
4304         },
4305         { }
4306 };
4307
4308 /* l3_main_2 -> dss_dsi1 */
4309 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4310         .master         = &omap44xx_l3_main_2_hwmod,
4311         .slave          = &omap44xx_dss_dsi1_hwmod,
4312         .clk            = "dss_fck",
4313         .addr           = omap44xx_dss_dsi1_dma_addrs,
4314         .user           = OCP_USER_SDMA,
4315 };
4316
4317 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4318         {
4319                 .pa_start       = 0x48044000,
4320                 .pa_end         = 0x480441ff,
4321                 .flags          = ADDR_TYPE_RT
4322         },
4323         { }
4324 };
4325
4326 /* l4_per -> dss_dsi1 */
4327 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4328         .master         = &omap44xx_l4_per_hwmod,
4329         .slave          = &omap44xx_dss_dsi1_hwmod,
4330         .clk            = "l4_div_ck",
4331         .addr           = omap44xx_dss_dsi1_addrs,
4332         .user           = OCP_USER_MPU,
4333 };
4334
4335 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4336         {
4337                 .pa_start       = 0x58005000,
4338                 .pa_end         = 0x580051ff,
4339                 .flags          = ADDR_TYPE_RT
4340         },
4341         { }
4342 };
4343
4344 /* l3_main_2 -> dss_dsi2 */
4345 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4346         .master         = &omap44xx_l3_main_2_hwmod,
4347         .slave          = &omap44xx_dss_dsi2_hwmod,
4348         .clk            = "dss_fck",
4349         .addr           = omap44xx_dss_dsi2_dma_addrs,
4350         .user           = OCP_USER_SDMA,
4351 };
4352
4353 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4354         {
4355                 .pa_start       = 0x48045000,
4356                 .pa_end         = 0x480451ff,
4357                 .flags          = ADDR_TYPE_RT
4358         },
4359         { }
4360 };
4361
4362 /* l4_per -> dss_dsi2 */
4363 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4364         .master         = &omap44xx_l4_per_hwmod,
4365         .slave          = &omap44xx_dss_dsi2_hwmod,
4366         .clk            = "l4_div_ck",
4367         .addr           = omap44xx_dss_dsi2_addrs,
4368         .user           = OCP_USER_MPU,
4369 };
4370
4371 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4372         {
4373                 .pa_start       = 0x58006000,
4374                 .pa_end         = 0x58006fff,
4375                 .flags          = ADDR_TYPE_RT
4376         },
4377         { }
4378 };
4379
4380 /* l3_main_2 -> dss_hdmi */
4381 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4382         .master         = &omap44xx_l3_main_2_hwmod,
4383         .slave          = &omap44xx_dss_hdmi_hwmod,
4384         .clk            = "dss_fck",
4385         .addr           = omap44xx_dss_hdmi_dma_addrs,
4386         .user           = OCP_USER_SDMA,
4387 };
4388
4389 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4390         {
4391                 .pa_start       = 0x48046000,
4392                 .pa_end         = 0x48046fff,
4393                 .flags          = ADDR_TYPE_RT
4394         },
4395         { }
4396 };
4397
4398 /* l4_per -> dss_hdmi */
4399 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4400         .master         = &omap44xx_l4_per_hwmod,
4401         .slave          = &omap44xx_dss_hdmi_hwmod,
4402         .clk            = "l4_div_ck",
4403         .addr           = omap44xx_dss_hdmi_addrs,
4404         .user           = OCP_USER_MPU,
4405 };
4406
4407 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4408         {
4409                 .pa_start       = 0x58002000,
4410                 .pa_end         = 0x580020ff,
4411                 .flags          = ADDR_TYPE_RT
4412         },
4413         { }
4414 };
4415
4416 /* l3_main_2 -> dss_rfbi */
4417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4418         .master         = &omap44xx_l3_main_2_hwmod,
4419         .slave          = &omap44xx_dss_rfbi_hwmod,
4420         .clk            = "dss_fck",
4421         .addr           = omap44xx_dss_rfbi_dma_addrs,
4422         .user           = OCP_USER_SDMA,
4423 };
4424
4425 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4426         {
4427                 .pa_start       = 0x48042000,
4428                 .pa_end         = 0x480420ff,
4429                 .flags          = ADDR_TYPE_RT
4430         },
4431         { }
4432 };
4433
4434 /* l4_per -> dss_rfbi */
4435 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4436         .master         = &omap44xx_l4_per_hwmod,
4437         .slave          = &omap44xx_dss_rfbi_hwmod,
4438         .clk            = "l4_div_ck",
4439         .addr           = omap44xx_dss_rfbi_addrs,
4440         .user           = OCP_USER_MPU,
4441 };
4442
4443 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4444         {
4445                 .pa_start       = 0x58003000,
4446                 .pa_end         = 0x580030ff,
4447                 .flags          = ADDR_TYPE_RT
4448         },
4449         { }
4450 };
4451
4452 /* l3_main_2 -> dss_venc */
4453 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4454         .master         = &omap44xx_l3_main_2_hwmod,
4455         .slave          = &omap44xx_dss_venc_hwmod,
4456         .clk            = "dss_fck",
4457         .addr           = omap44xx_dss_venc_dma_addrs,
4458         .user           = OCP_USER_SDMA,
4459 };
4460
4461 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4462         {
4463                 .pa_start       = 0x48043000,
4464                 .pa_end         = 0x480430ff,
4465                 .flags          = ADDR_TYPE_RT
4466         },
4467         { }
4468 };
4469
4470 /* l4_per -> dss_venc */
4471 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4472         .master         = &omap44xx_l4_per_hwmod,
4473         .slave          = &omap44xx_dss_venc_hwmod,
4474         .clk            = "l4_div_ck",
4475         .addr           = omap44xx_dss_venc_addrs,
4476         .user           = OCP_USER_MPU,
4477 };
4478
4479 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4480         {
4481                 .pa_start       = 0x48078000,
4482                 .pa_end         = 0x48078fff,
4483                 .flags          = ADDR_TYPE_RT
4484         },
4485         { }
4486 };
4487
4488 /* l4_per -> elm */
4489 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4490         .master         = &omap44xx_l4_per_hwmod,
4491         .slave          = &omap44xx_elm_hwmod,
4492         .clk            = "l4_div_ck",
4493         .addr           = omap44xx_elm_addrs,
4494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4495 };
4496
4497 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4498         {
4499                 .pa_start       = 0x4c000000,
4500                 .pa_end         = 0x4c0000ff,
4501                 .flags          = ADDR_TYPE_RT
4502         },
4503         { }
4504 };
4505
4506 /* emif_fw -> emif1 */
4507 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4508         .master         = &omap44xx_emif_fw_hwmod,
4509         .slave          = &omap44xx_emif1_hwmod,
4510         .clk            = "l3_div_ck",
4511         .addr           = omap44xx_emif1_addrs,
4512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4513 };
4514
4515 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4516         {
4517                 .pa_start       = 0x4d000000,
4518                 .pa_end         = 0x4d0000ff,
4519                 .flags          = ADDR_TYPE_RT
4520         },
4521         { }
4522 };
4523
4524 /* emif_fw -> emif2 */
4525 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4526         .master         = &omap44xx_emif_fw_hwmod,
4527         .slave          = &omap44xx_emif2_hwmod,
4528         .clk            = "l3_div_ck",
4529         .addr           = omap44xx_emif2_addrs,
4530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4531 };
4532
4533 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4534         {
4535                 .pa_start       = 0x4a10a000,
4536                 .pa_end         = 0x4a10a1ff,
4537                 .flags          = ADDR_TYPE_RT
4538         },
4539         { }
4540 };
4541
4542 /* l4_cfg -> fdif */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4544         .master         = &omap44xx_l4_cfg_hwmod,
4545         .slave          = &omap44xx_fdif_hwmod,
4546         .clk            = "l4_div_ck",
4547         .addr           = omap44xx_fdif_addrs,
4548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4549 };
4550
4551 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4552         {
4553                 .pa_start       = 0x4a310000,
4554                 .pa_end         = 0x4a3101ff,
4555                 .flags          = ADDR_TYPE_RT
4556         },
4557         { }
4558 };
4559
4560 /* l4_wkup -> gpio1 */
4561 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4562         .master         = &omap44xx_l4_wkup_hwmod,
4563         .slave          = &omap44xx_gpio1_hwmod,
4564         .clk            = "l4_wkup_clk_mux_ck",
4565         .addr           = omap44xx_gpio1_addrs,
4566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4567 };
4568
4569 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4570         {
4571                 .pa_start       = 0x48055000,
4572                 .pa_end         = 0x480551ff,
4573                 .flags          = ADDR_TYPE_RT
4574         },
4575         { }
4576 };
4577
4578 /* l4_per -> gpio2 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4580         .master         = &omap44xx_l4_per_hwmod,
4581         .slave          = &omap44xx_gpio2_hwmod,
4582         .clk            = "l4_div_ck",
4583         .addr           = omap44xx_gpio2_addrs,
4584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4585 };
4586
4587 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4588         {
4589                 .pa_start       = 0x48057000,
4590                 .pa_end         = 0x480571ff,
4591                 .flags          = ADDR_TYPE_RT
4592         },
4593         { }
4594 };
4595
4596 /* l4_per -> gpio3 */
4597 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4598         .master         = &omap44xx_l4_per_hwmod,
4599         .slave          = &omap44xx_gpio3_hwmod,
4600         .clk            = "l4_div_ck",
4601         .addr           = omap44xx_gpio3_addrs,
4602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4603 };
4604
4605 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4606         {
4607                 .pa_start       = 0x48059000,
4608                 .pa_end         = 0x480591ff,
4609                 .flags          = ADDR_TYPE_RT
4610         },
4611         { }
4612 };
4613
4614 /* l4_per -> gpio4 */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4616         .master         = &omap44xx_l4_per_hwmod,
4617         .slave          = &omap44xx_gpio4_hwmod,
4618         .clk            = "l4_div_ck",
4619         .addr           = omap44xx_gpio4_addrs,
4620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4621 };
4622
4623 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4624         {
4625                 .pa_start       = 0x4805b000,
4626                 .pa_end         = 0x4805b1ff,
4627                 .flags          = ADDR_TYPE_RT
4628         },
4629         { }
4630 };
4631
4632 /* l4_per -> gpio5 */
4633 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4634         .master         = &omap44xx_l4_per_hwmod,
4635         .slave          = &omap44xx_gpio5_hwmod,
4636         .clk            = "l4_div_ck",
4637         .addr           = omap44xx_gpio5_addrs,
4638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4639 };
4640
4641 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4642         {
4643                 .pa_start       = 0x4805d000,
4644                 .pa_end         = 0x4805d1ff,
4645                 .flags          = ADDR_TYPE_RT
4646         },
4647         { }
4648 };
4649
4650 /* l4_per -> gpio6 */
4651 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4652         .master         = &omap44xx_l4_per_hwmod,
4653         .slave          = &omap44xx_gpio6_hwmod,
4654         .clk            = "l4_div_ck",
4655         .addr           = omap44xx_gpio6_addrs,
4656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4657 };
4658
4659 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4660         {
4661                 .pa_start       = 0x50000000,
4662                 .pa_end         = 0x500003ff,
4663                 .flags          = ADDR_TYPE_RT
4664         },
4665         { }
4666 };
4667
4668 /* l3_main_2 -> gpmc */
4669 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4670         .master         = &omap44xx_l3_main_2_hwmod,
4671         .slave          = &omap44xx_gpmc_hwmod,
4672         .clk            = "l3_div_ck",
4673         .addr           = omap44xx_gpmc_addrs,
4674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4675 };
4676
4677 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4678         {
4679                 .pa_start       = 0x56000000,
4680                 .pa_end         = 0x5600ffff,
4681                 .flags          = ADDR_TYPE_RT
4682         },
4683         { }
4684 };
4685
4686 /* l3_main_2 -> gpu */
4687 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4688         .master         = &omap44xx_l3_main_2_hwmod,
4689         .slave          = &omap44xx_gpu_hwmod,
4690         .clk            = "l3_div_ck",
4691         .addr           = omap44xx_gpu_addrs,
4692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4693 };
4694
4695 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4696         {
4697                 .pa_start       = 0x480b2000,
4698                 .pa_end         = 0x480b201f,
4699                 .flags          = ADDR_TYPE_RT
4700         },
4701         { }
4702 };
4703
4704 /* l4_per -> hdq1w */
4705 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4706         .master         = &omap44xx_l4_per_hwmod,
4707         .slave          = &omap44xx_hdq1w_hwmod,
4708         .clk            = "l4_div_ck",
4709         .addr           = omap44xx_hdq1w_addrs,
4710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4711 };
4712
4713 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4714         {
4715                 .pa_start       = 0x4a058000,
4716                 .pa_end         = 0x4a05bfff,
4717                 .flags          = ADDR_TYPE_RT
4718         },
4719         { }
4720 };
4721
4722 /* l4_cfg -> hsi */
4723 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4724         .master         = &omap44xx_l4_cfg_hwmod,
4725         .slave          = &omap44xx_hsi_hwmod,
4726         .clk            = "l4_div_ck",
4727         .addr           = omap44xx_hsi_addrs,
4728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4729 };
4730
4731 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4732         {
4733                 .pa_start       = 0x48070000,
4734                 .pa_end         = 0x480700ff,
4735                 .flags          = ADDR_TYPE_RT
4736         },
4737         { }
4738 };
4739
4740 /* l4_per -> i2c1 */
4741 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4742         .master         = &omap44xx_l4_per_hwmod,
4743         .slave          = &omap44xx_i2c1_hwmod,
4744         .clk            = "l4_div_ck",
4745         .addr           = omap44xx_i2c1_addrs,
4746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4747 };
4748
4749 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4750         {
4751                 .pa_start       = 0x48072000,
4752                 .pa_end         = 0x480720ff,
4753                 .flags          = ADDR_TYPE_RT
4754         },
4755         { }
4756 };
4757
4758 /* l4_per -> i2c2 */
4759 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4760         .master         = &omap44xx_l4_per_hwmod,
4761         .slave          = &omap44xx_i2c2_hwmod,
4762         .clk            = "l4_div_ck",
4763         .addr           = omap44xx_i2c2_addrs,
4764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4765 };
4766
4767 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4768         {
4769                 .pa_start       = 0x48060000,
4770                 .pa_end         = 0x480600ff,
4771                 .flags          = ADDR_TYPE_RT
4772         },
4773         { }
4774 };
4775
4776 /* l4_per -> i2c3 */
4777 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4778         .master         = &omap44xx_l4_per_hwmod,
4779         .slave          = &omap44xx_i2c3_hwmod,
4780         .clk            = "l4_div_ck",
4781         .addr           = omap44xx_i2c3_addrs,
4782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4783 };
4784
4785 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4786         {
4787                 .pa_start       = 0x48350000,
4788                 .pa_end         = 0x483500ff,
4789                 .flags          = ADDR_TYPE_RT
4790         },
4791         { }
4792 };
4793
4794 /* l4_per -> i2c4 */
4795 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4796         .master         = &omap44xx_l4_per_hwmod,
4797         .slave          = &omap44xx_i2c4_hwmod,
4798         .clk            = "l4_div_ck",
4799         .addr           = omap44xx_i2c4_addrs,
4800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4801 };
4802
4803 /* l3_main_2 -> ipu */
4804 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4805         .master         = &omap44xx_l3_main_2_hwmod,
4806         .slave          = &omap44xx_ipu_hwmod,
4807         .clk            = "l3_div_ck",
4808         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4809 };
4810
4811 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4812         {
4813                 .pa_start       = 0x52000000,
4814                 .pa_end         = 0x520000ff,
4815                 .flags          = ADDR_TYPE_RT
4816         },
4817         { }
4818 };
4819
4820 /* l3_main_2 -> iss */
4821 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4822         .master         = &omap44xx_l3_main_2_hwmod,
4823         .slave          = &omap44xx_iss_hwmod,
4824         .clk            = "l3_div_ck",
4825         .addr           = omap44xx_iss_addrs,
4826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4827 };
4828
4829 /* iva -> sl2if */
4830 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4831         .master         = &omap44xx_iva_hwmod,
4832         .slave          = &omap44xx_sl2if_hwmod,
4833         .clk            = "dpll_iva_m5x2_ck",
4834         .user           = OCP_USER_IVA,
4835 };
4836
4837 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4838         {
4839                 .pa_start       = 0x5a000000,
4840                 .pa_end         = 0x5a07ffff,
4841                 .flags          = ADDR_TYPE_RT
4842         },
4843         { }
4844 };
4845
4846 /* l3_main_2 -> iva */
4847 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4848         .master         = &omap44xx_l3_main_2_hwmod,
4849         .slave          = &omap44xx_iva_hwmod,
4850         .clk            = "l3_div_ck",
4851         .addr           = omap44xx_iva_addrs,
4852         .user           = OCP_USER_MPU,
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4856         {
4857                 .pa_start       = 0x4a31c000,
4858                 .pa_end         = 0x4a31c07f,
4859                 .flags          = ADDR_TYPE_RT
4860         },
4861         { }
4862 };
4863
4864 /* l4_wkup -> kbd */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4866         .master         = &omap44xx_l4_wkup_hwmod,
4867         .slave          = &omap44xx_kbd_hwmod,
4868         .clk            = "l4_wkup_clk_mux_ck",
4869         .addr           = omap44xx_kbd_addrs,
4870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4874         {
4875                 .pa_start       = 0x4a0f4000,
4876                 .pa_end         = 0x4a0f41ff,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879         { }
4880 };
4881
4882 /* l4_cfg -> mailbox */
4883 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4884         .master         = &omap44xx_l4_cfg_hwmod,
4885         .slave          = &omap44xx_mailbox_hwmod,
4886         .clk            = "l4_div_ck",
4887         .addr           = omap44xx_mailbox_addrs,
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4892         {
4893                 .pa_start       = 0x40128000,
4894                 .pa_end         = 0x401283ff,
4895                 .flags          = ADDR_TYPE_RT
4896         },
4897         { }
4898 };
4899
4900 /* l4_abe -> mcasp */
4901 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4902         .master         = &omap44xx_l4_abe_hwmod,
4903         .slave          = &omap44xx_mcasp_hwmod,
4904         .clk            = "ocp_abe_iclk",
4905         .addr           = omap44xx_mcasp_addrs,
4906         .user           = OCP_USER_MPU,
4907 };
4908
4909 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4910         {
4911                 .pa_start       = 0x49028000,
4912                 .pa_end         = 0x490283ff,
4913                 .flags          = ADDR_TYPE_RT
4914         },
4915         { }
4916 };
4917
4918 /* l4_abe -> mcasp (dma) */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4920         .master         = &omap44xx_l4_abe_hwmod,
4921         .slave          = &omap44xx_mcasp_hwmod,
4922         .clk            = "ocp_abe_iclk",
4923         .addr           = omap44xx_mcasp_dma_addrs,
4924         .user           = OCP_USER_SDMA,
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4928         {
4929                 .name           = "mpu",
4930                 .pa_start       = 0x40122000,
4931                 .pa_end         = 0x401220ff,
4932                 .flags          = ADDR_TYPE_RT
4933         },
4934         { }
4935 };
4936
4937 /* l4_abe -> mcbsp1 */
4938 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4939         .master         = &omap44xx_l4_abe_hwmod,
4940         .slave          = &omap44xx_mcbsp1_hwmod,
4941         .clk            = "ocp_abe_iclk",
4942         .addr           = omap44xx_mcbsp1_addrs,
4943         .user           = OCP_USER_MPU,
4944 };
4945
4946 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4947         {
4948                 .name           = "dma",
4949                 .pa_start       = 0x49022000,
4950                 .pa_end         = 0x490220ff,
4951                 .flags          = ADDR_TYPE_RT
4952         },
4953         { }
4954 };
4955
4956 /* l4_abe -> mcbsp1 (dma) */
4957 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4958         .master         = &omap44xx_l4_abe_hwmod,
4959         .slave          = &omap44xx_mcbsp1_hwmod,
4960         .clk            = "ocp_abe_iclk",
4961         .addr           = omap44xx_mcbsp1_dma_addrs,
4962         .user           = OCP_USER_SDMA,
4963 };
4964
4965 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4966         {
4967                 .name           = "mpu",
4968                 .pa_start       = 0x40124000,
4969                 .pa_end         = 0x401240ff,
4970                 .flags          = ADDR_TYPE_RT
4971         },
4972         { }
4973 };
4974
4975 /* l4_abe -> mcbsp2 */
4976 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4977         .master         = &omap44xx_l4_abe_hwmod,
4978         .slave          = &omap44xx_mcbsp2_hwmod,
4979         .clk            = "ocp_abe_iclk",
4980         .addr           = omap44xx_mcbsp2_addrs,
4981         .user           = OCP_USER_MPU,
4982 };
4983
4984 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4985         {
4986                 .name           = "dma",
4987                 .pa_start       = 0x49024000,
4988                 .pa_end         = 0x490240ff,
4989                 .flags          = ADDR_TYPE_RT
4990         },
4991         { }
4992 };
4993
4994 /* l4_abe -> mcbsp2 (dma) */
4995 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4996         .master         = &omap44xx_l4_abe_hwmod,
4997         .slave          = &omap44xx_mcbsp2_hwmod,
4998         .clk            = "ocp_abe_iclk",
4999         .addr           = omap44xx_mcbsp2_dma_addrs,
5000         .user           = OCP_USER_SDMA,
5001 };
5002
5003 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5004         {
5005                 .name           = "mpu",
5006                 .pa_start       = 0x40126000,
5007                 .pa_end         = 0x401260ff,
5008                 .flags          = ADDR_TYPE_RT
5009         },
5010         { }
5011 };
5012
5013 /* l4_abe -> mcbsp3 */
5014 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5015         .master         = &omap44xx_l4_abe_hwmod,
5016         .slave          = &omap44xx_mcbsp3_hwmod,
5017         .clk            = "ocp_abe_iclk",
5018         .addr           = omap44xx_mcbsp3_addrs,
5019         .user           = OCP_USER_MPU,
5020 };
5021
5022 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5023         {
5024                 .name           = "dma",
5025                 .pa_start       = 0x49026000,
5026                 .pa_end         = 0x490260ff,
5027                 .flags          = ADDR_TYPE_RT
5028         },
5029         { }
5030 };
5031
5032 /* l4_abe -> mcbsp3 (dma) */
5033 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5034         .master         = &omap44xx_l4_abe_hwmod,
5035         .slave          = &omap44xx_mcbsp3_hwmod,
5036         .clk            = "ocp_abe_iclk",
5037         .addr           = omap44xx_mcbsp3_dma_addrs,
5038         .user           = OCP_USER_SDMA,
5039 };
5040
5041 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5042         {
5043                 .pa_start       = 0x48096000,
5044                 .pa_end         = 0x480960ff,
5045                 .flags          = ADDR_TYPE_RT
5046         },
5047         { }
5048 };
5049
5050 /* l4_per -> mcbsp4 */
5051 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5052         .master         = &omap44xx_l4_per_hwmod,
5053         .slave          = &omap44xx_mcbsp4_hwmod,
5054         .clk            = "l4_div_ck",
5055         .addr           = omap44xx_mcbsp4_addrs,
5056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5057 };
5058
5059 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5060         {
5061                 .pa_start       = 0x40132000,
5062                 .pa_end         = 0x4013207f,
5063                 .flags          = ADDR_TYPE_RT
5064         },
5065         { }
5066 };
5067
5068 /* l4_abe -> mcpdm */
5069 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5070         .master         = &omap44xx_l4_abe_hwmod,
5071         .slave          = &omap44xx_mcpdm_hwmod,
5072         .clk            = "ocp_abe_iclk",
5073         .addr           = omap44xx_mcpdm_addrs,
5074         .user           = OCP_USER_MPU,
5075 };
5076
5077 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5078         {
5079                 .pa_start       = 0x49032000,
5080                 .pa_end         = 0x4903207f,
5081                 .flags          = ADDR_TYPE_RT
5082         },
5083         { }
5084 };
5085
5086 /* l4_abe -> mcpdm (dma) */
5087 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5088         .master         = &omap44xx_l4_abe_hwmod,
5089         .slave          = &omap44xx_mcpdm_hwmod,
5090         .clk            = "ocp_abe_iclk",
5091         .addr           = omap44xx_mcpdm_dma_addrs,
5092         .user           = OCP_USER_SDMA,
5093 };
5094
5095 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5096         {
5097                 .pa_start       = 0x48098000,
5098                 .pa_end         = 0x480981ff,
5099                 .flags          = ADDR_TYPE_RT
5100         },
5101         { }
5102 };
5103
5104 /* l4_per -> mcspi1 */
5105 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5106         .master         = &omap44xx_l4_per_hwmod,
5107         .slave          = &omap44xx_mcspi1_hwmod,
5108         .clk            = "l4_div_ck",
5109         .addr           = omap44xx_mcspi1_addrs,
5110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5111 };
5112
5113 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5114         {
5115                 .pa_start       = 0x4809a000,
5116                 .pa_end         = 0x4809a1ff,
5117                 .flags          = ADDR_TYPE_RT
5118         },
5119         { }
5120 };
5121
5122 /* l4_per -> mcspi2 */
5123 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5124         .master         = &omap44xx_l4_per_hwmod,
5125         .slave          = &omap44xx_mcspi2_hwmod,
5126         .clk            = "l4_div_ck",
5127         .addr           = omap44xx_mcspi2_addrs,
5128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5129 };
5130
5131 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5132         {
5133                 .pa_start       = 0x480b8000,
5134                 .pa_end         = 0x480b81ff,
5135                 .flags          = ADDR_TYPE_RT
5136         },
5137         { }
5138 };
5139
5140 /* l4_per -> mcspi3 */
5141 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5142         .master         = &omap44xx_l4_per_hwmod,
5143         .slave          = &omap44xx_mcspi3_hwmod,
5144         .clk            = "l4_div_ck",
5145         .addr           = omap44xx_mcspi3_addrs,
5146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5147 };
5148
5149 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5150         {
5151                 .pa_start       = 0x480ba000,
5152                 .pa_end         = 0x480ba1ff,
5153                 .flags          = ADDR_TYPE_RT
5154         },
5155         { }
5156 };
5157
5158 /* l4_per -> mcspi4 */
5159 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5160         .master         = &omap44xx_l4_per_hwmod,
5161         .slave          = &omap44xx_mcspi4_hwmod,
5162         .clk            = "l4_div_ck",
5163         .addr           = omap44xx_mcspi4_addrs,
5164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5165 };
5166
5167 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5168         {
5169                 .pa_start       = 0x4809c000,
5170                 .pa_end         = 0x4809c3ff,
5171                 .flags          = ADDR_TYPE_RT
5172         },
5173         { }
5174 };
5175
5176 /* l4_per -> mmc1 */
5177 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5178         .master         = &omap44xx_l4_per_hwmod,
5179         .slave          = &omap44xx_mmc1_hwmod,
5180         .clk            = "l4_div_ck",
5181         .addr           = omap44xx_mmc1_addrs,
5182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5183 };
5184
5185 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5186         {
5187                 .pa_start       = 0x480b4000,
5188                 .pa_end         = 0x480b43ff,
5189                 .flags          = ADDR_TYPE_RT
5190         },
5191         { }
5192 };
5193
5194 /* l4_per -> mmc2 */
5195 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5196         .master         = &omap44xx_l4_per_hwmod,
5197         .slave          = &omap44xx_mmc2_hwmod,
5198         .clk            = "l4_div_ck",
5199         .addr           = omap44xx_mmc2_addrs,
5200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5201 };
5202
5203 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5204         {
5205                 .pa_start       = 0x480ad000,
5206                 .pa_end         = 0x480ad3ff,
5207                 .flags          = ADDR_TYPE_RT
5208         },
5209         { }
5210 };
5211
5212 /* l4_per -> mmc3 */
5213 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5214         .master         = &omap44xx_l4_per_hwmod,
5215         .slave          = &omap44xx_mmc3_hwmod,
5216         .clk            = "l4_div_ck",
5217         .addr           = omap44xx_mmc3_addrs,
5218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5219 };
5220
5221 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5222         {
5223                 .pa_start       = 0x480d1000,
5224                 .pa_end         = 0x480d13ff,
5225                 .flags          = ADDR_TYPE_RT
5226         },
5227         { }
5228 };
5229
5230 /* l4_per -> mmc4 */
5231 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5232         .master         = &omap44xx_l4_per_hwmod,
5233         .slave          = &omap44xx_mmc4_hwmod,
5234         .clk            = "l4_div_ck",
5235         .addr           = omap44xx_mmc4_addrs,
5236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5237 };
5238
5239 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5240         {
5241                 .pa_start       = 0x480d5000,
5242                 .pa_end         = 0x480d53ff,
5243                 .flags          = ADDR_TYPE_RT
5244         },
5245         { }
5246 };
5247
5248 /* l4_per -> mmc5 */
5249 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5250         .master         = &omap44xx_l4_per_hwmod,
5251         .slave          = &omap44xx_mmc5_hwmod,
5252         .clk            = "l4_div_ck",
5253         .addr           = omap44xx_mmc5_addrs,
5254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5255 };
5256
5257 /* l3_main_2 -> ocmc_ram */
5258 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5259         .master         = &omap44xx_l3_main_2_hwmod,
5260         .slave          = &omap44xx_ocmc_ram_hwmod,
5261         .clk            = "l3_div_ck",
5262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5263 };
5264
5265 /* l4_cfg -> ocp2scp_usb_phy */
5266 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5267         .master         = &omap44xx_l4_cfg_hwmod,
5268         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5269         .clk            = "l4_div_ck",
5270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5271 };
5272
5273 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5274         {
5275                 .pa_start       = 0x48243000,
5276                 .pa_end         = 0x48243fff,
5277                 .flags          = ADDR_TYPE_RT
5278         },
5279         { }
5280 };
5281
5282 /* mpu_private -> prcm_mpu */
5283 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5284         .master         = &omap44xx_mpu_private_hwmod,
5285         .slave          = &omap44xx_prcm_mpu_hwmod,
5286         .clk            = "l3_div_ck",
5287         .addr           = omap44xx_prcm_mpu_addrs,
5288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5289 };
5290
5291 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5292         {
5293                 .pa_start       = 0x4a004000,
5294                 .pa_end         = 0x4a004fff,
5295                 .flags          = ADDR_TYPE_RT
5296         },
5297         { }
5298 };
5299
5300 /* l4_wkup -> cm_core_aon */
5301 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5302         .master         = &omap44xx_l4_wkup_hwmod,
5303         .slave          = &omap44xx_cm_core_aon_hwmod,
5304         .clk            = "l4_wkup_clk_mux_ck",
5305         .addr           = omap44xx_cm_core_aon_addrs,
5306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5307 };
5308
5309 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5310         {
5311                 .pa_start       = 0x4a008000,
5312                 .pa_end         = 0x4a009fff,
5313                 .flags          = ADDR_TYPE_RT
5314         },
5315         { }
5316 };
5317
5318 /* l4_cfg -> cm_core */
5319 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5320         .master         = &omap44xx_l4_cfg_hwmod,
5321         .slave          = &omap44xx_cm_core_hwmod,
5322         .clk            = "l4_div_ck",
5323         .addr           = omap44xx_cm_core_addrs,
5324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5325 };
5326
5327 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5328         {
5329                 .pa_start       = 0x4a306000,
5330                 .pa_end         = 0x4a307fff,
5331                 .flags          = ADDR_TYPE_RT
5332         },
5333         { }
5334 };
5335
5336 /* l4_wkup -> prm */
5337 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5338         .master         = &omap44xx_l4_wkup_hwmod,
5339         .slave          = &omap44xx_prm_hwmod,
5340         .clk            = "l4_wkup_clk_mux_ck",
5341         .addr           = omap44xx_prm_addrs,
5342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5343 };
5344
5345 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5346         {
5347                 .pa_start       = 0x4a30a000,
5348                 .pa_end         = 0x4a30a7ff,
5349                 .flags          = ADDR_TYPE_RT
5350         },
5351         { }
5352 };
5353
5354 /* l4_wkup -> scrm */
5355 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5356         .master         = &omap44xx_l4_wkup_hwmod,
5357         .slave          = &omap44xx_scrm_hwmod,
5358         .clk            = "l4_wkup_clk_mux_ck",
5359         .addr           = omap44xx_scrm_addrs,
5360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5361 };
5362
5363 /* l3_main_2 -> sl2if */
5364 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5365         .master         = &omap44xx_l3_main_2_hwmod,
5366         .slave          = &omap44xx_sl2if_hwmod,
5367         .clk            = "l3_div_ck",
5368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5369 };
5370
5371 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5372         {
5373                 .pa_start       = 0x4012c000,
5374                 .pa_end         = 0x4012c3ff,
5375                 .flags          = ADDR_TYPE_RT
5376         },
5377         { }
5378 };
5379
5380 /* l4_abe -> slimbus1 */
5381 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5382         .master         = &omap44xx_l4_abe_hwmod,
5383         .slave          = &omap44xx_slimbus1_hwmod,
5384         .clk            = "ocp_abe_iclk",
5385         .addr           = omap44xx_slimbus1_addrs,
5386         .user           = OCP_USER_MPU,
5387 };
5388
5389 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5390         {
5391                 .pa_start       = 0x4902c000,
5392                 .pa_end         = 0x4902c3ff,
5393                 .flags          = ADDR_TYPE_RT
5394         },
5395         { }
5396 };
5397
5398 /* l4_abe -> slimbus1 (dma) */
5399 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5400         .master         = &omap44xx_l4_abe_hwmod,
5401         .slave          = &omap44xx_slimbus1_hwmod,
5402         .clk            = "ocp_abe_iclk",
5403         .addr           = omap44xx_slimbus1_dma_addrs,
5404         .user           = OCP_USER_SDMA,
5405 };
5406
5407 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5408         {
5409                 .pa_start       = 0x48076000,
5410                 .pa_end         = 0x480763ff,
5411                 .flags          = ADDR_TYPE_RT
5412         },
5413         { }
5414 };
5415
5416 /* l4_per -> slimbus2 */
5417 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5418         .master         = &omap44xx_l4_per_hwmod,
5419         .slave          = &omap44xx_slimbus2_hwmod,
5420         .clk            = "l4_div_ck",
5421         .addr           = omap44xx_slimbus2_addrs,
5422         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5423 };
5424
5425 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5426         {
5427                 .pa_start       = 0x4a0dd000,
5428                 .pa_end         = 0x4a0dd03f,
5429                 .flags          = ADDR_TYPE_RT
5430         },
5431         { }
5432 };
5433
5434 /* l4_cfg -> smartreflex_core */
5435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5436         .master         = &omap44xx_l4_cfg_hwmod,
5437         .slave          = &omap44xx_smartreflex_core_hwmod,
5438         .clk            = "l4_div_ck",
5439         .addr           = omap44xx_smartreflex_core_addrs,
5440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5441 };
5442
5443 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5444         {
5445                 .pa_start       = 0x4a0db000,
5446                 .pa_end         = 0x4a0db03f,
5447                 .flags          = ADDR_TYPE_RT
5448         },
5449         { }
5450 };
5451
5452 /* l4_cfg -> smartreflex_iva */
5453 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5454         .master         = &omap44xx_l4_cfg_hwmod,
5455         .slave          = &omap44xx_smartreflex_iva_hwmod,
5456         .clk            = "l4_div_ck",
5457         .addr           = omap44xx_smartreflex_iva_addrs,
5458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5459 };
5460
5461 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5462         {
5463                 .pa_start       = 0x4a0d9000,
5464                 .pa_end         = 0x4a0d903f,
5465                 .flags          = ADDR_TYPE_RT
5466         },
5467         { }
5468 };
5469
5470 /* l4_cfg -> smartreflex_mpu */
5471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5472         .master         = &omap44xx_l4_cfg_hwmod,
5473         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5474         .clk            = "l4_div_ck",
5475         .addr           = omap44xx_smartreflex_mpu_addrs,
5476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5477 };
5478
5479 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5480         {
5481                 .pa_start       = 0x4a0f6000,
5482                 .pa_end         = 0x4a0f6fff,
5483                 .flags          = ADDR_TYPE_RT
5484         },
5485         { }
5486 };
5487
5488 /* l4_cfg -> spinlock */
5489 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5490         .master         = &omap44xx_l4_cfg_hwmod,
5491         .slave          = &omap44xx_spinlock_hwmod,
5492         .clk            = "l4_div_ck",
5493         .addr           = omap44xx_spinlock_addrs,
5494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5495 };
5496
5497 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5498         {
5499                 .pa_start       = 0x4a318000,
5500                 .pa_end         = 0x4a31807f,
5501                 .flags          = ADDR_TYPE_RT
5502         },
5503         { }
5504 };
5505
5506 /* l4_wkup -> timer1 */
5507 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5508         .master         = &omap44xx_l4_wkup_hwmod,
5509         .slave          = &omap44xx_timer1_hwmod,
5510         .clk            = "l4_wkup_clk_mux_ck",
5511         .addr           = omap44xx_timer1_addrs,
5512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5513 };
5514
5515 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5516         {
5517                 .pa_start       = 0x48032000,
5518                 .pa_end         = 0x4803207f,
5519                 .flags          = ADDR_TYPE_RT
5520         },
5521         { }
5522 };
5523
5524 /* l4_per -> timer2 */
5525 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5526         .master         = &omap44xx_l4_per_hwmod,
5527         .slave          = &omap44xx_timer2_hwmod,
5528         .clk            = "l4_div_ck",
5529         .addr           = omap44xx_timer2_addrs,
5530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5531 };
5532
5533 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5534         {
5535                 .pa_start       = 0x48034000,
5536                 .pa_end         = 0x4803407f,
5537                 .flags          = ADDR_TYPE_RT
5538         },
5539         { }
5540 };
5541
5542 /* l4_per -> timer3 */
5543 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5544         .master         = &omap44xx_l4_per_hwmod,
5545         .slave          = &omap44xx_timer3_hwmod,
5546         .clk            = "l4_div_ck",
5547         .addr           = omap44xx_timer3_addrs,
5548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5549 };
5550
5551 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5552         {
5553                 .pa_start       = 0x48036000,
5554                 .pa_end         = 0x4803607f,
5555                 .flags          = ADDR_TYPE_RT
5556         },
5557         { }
5558 };
5559
5560 /* l4_per -> timer4 */
5561 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5562         .master         = &omap44xx_l4_per_hwmod,
5563         .slave          = &omap44xx_timer4_hwmod,
5564         .clk            = "l4_div_ck",
5565         .addr           = omap44xx_timer4_addrs,
5566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5567 };
5568
5569 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5570         {
5571                 .pa_start       = 0x40138000,
5572                 .pa_end         = 0x4013807f,
5573                 .flags          = ADDR_TYPE_RT
5574         },
5575         { }
5576 };
5577
5578 /* l4_abe -> timer5 */
5579 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5580         .master         = &omap44xx_l4_abe_hwmod,
5581         .slave          = &omap44xx_timer5_hwmod,
5582         .clk            = "ocp_abe_iclk",
5583         .addr           = omap44xx_timer5_addrs,
5584         .user           = OCP_USER_MPU,
5585 };
5586
5587 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5588         {
5589                 .pa_start       = 0x49038000,
5590                 .pa_end         = 0x4903807f,
5591                 .flags          = ADDR_TYPE_RT
5592         },
5593         { }
5594 };
5595
5596 /* l4_abe -> timer5 (dma) */
5597 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5598         .master         = &omap44xx_l4_abe_hwmod,
5599         .slave          = &omap44xx_timer5_hwmod,
5600         .clk            = "ocp_abe_iclk",
5601         .addr           = omap44xx_timer5_dma_addrs,
5602         .user           = OCP_USER_SDMA,
5603 };
5604
5605 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5606         {
5607                 .pa_start       = 0x4013a000,
5608                 .pa_end         = 0x4013a07f,
5609                 .flags          = ADDR_TYPE_RT
5610         },
5611         { }
5612 };
5613
5614 /* l4_abe -> timer6 */
5615 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5616         .master         = &omap44xx_l4_abe_hwmod,
5617         .slave          = &omap44xx_timer6_hwmod,
5618         .clk            = "ocp_abe_iclk",
5619         .addr           = omap44xx_timer6_addrs,
5620         .user           = OCP_USER_MPU,
5621 };
5622
5623 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5624         {
5625                 .pa_start       = 0x4903a000,
5626                 .pa_end         = 0x4903a07f,
5627                 .flags          = ADDR_TYPE_RT
5628         },
5629         { }
5630 };
5631
5632 /* l4_abe -> timer6 (dma) */
5633 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5634         .master         = &omap44xx_l4_abe_hwmod,
5635         .slave          = &omap44xx_timer6_hwmod,
5636         .clk            = "ocp_abe_iclk",
5637         .addr           = omap44xx_timer6_dma_addrs,
5638         .user           = OCP_USER_SDMA,
5639 };
5640
5641 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5642         {
5643                 .pa_start       = 0x4013c000,
5644                 .pa_end         = 0x4013c07f,
5645                 .flags          = ADDR_TYPE_RT
5646         },
5647         { }
5648 };
5649
5650 /* l4_abe -> timer7 */
5651 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5652         .master         = &omap44xx_l4_abe_hwmod,
5653         .slave          = &omap44xx_timer7_hwmod,
5654         .clk            = "ocp_abe_iclk",
5655         .addr           = omap44xx_timer7_addrs,
5656         .user           = OCP_USER_MPU,
5657 };
5658
5659 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5660         {
5661                 .pa_start       = 0x4903c000,
5662                 .pa_end         = 0x4903c07f,
5663                 .flags          = ADDR_TYPE_RT
5664         },
5665         { }
5666 };
5667
5668 /* l4_abe -> timer7 (dma) */
5669 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5670         .master         = &omap44xx_l4_abe_hwmod,
5671         .slave          = &omap44xx_timer7_hwmod,
5672         .clk            = "ocp_abe_iclk",
5673         .addr           = omap44xx_timer7_dma_addrs,
5674         .user           = OCP_USER_SDMA,
5675 };
5676
5677 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5678         {
5679                 .pa_start       = 0x4013e000,
5680                 .pa_end         = 0x4013e07f,
5681                 .flags          = ADDR_TYPE_RT
5682         },
5683         { }
5684 };
5685
5686 /* l4_abe -> timer8 */
5687 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5688         .master         = &omap44xx_l4_abe_hwmod,
5689         .slave          = &omap44xx_timer8_hwmod,
5690         .clk            = "ocp_abe_iclk",
5691         .addr           = omap44xx_timer8_addrs,
5692         .user           = OCP_USER_MPU,
5693 };
5694
5695 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5696         {
5697                 .pa_start       = 0x4903e000,
5698                 .pa_end         = 0x4903e07f,
5699                 .flags          = ADDR_TYPE_RT
5700         },
5701         { }
5702 };
5703
5704 /* l4_abe -> timer8 (dma) */
5705 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5706         .master         = &omap44xx_l4_abe_hwmod,
5707         .slave          = &omap44xx_timer8_hwmod,
5708         .clk            = "ocp_abe_iclk",
5709         .addr           = omap44xx_timer8_dma_addrs,
5710         .user           = OCP_USER_SDMA,
5711 };
5712
5713 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5714         {
5715                 .pa_start       = 0x4803e000,
5716                 .pa_end         = 0x4803e07f,
5717                 .flags          = ADDR_TYPE_RT
5718         },
5719         { }
5720 };
5721
5722 /* l4_per -> timer9 */
5723 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5724         .master         = &omap44xx_l4_per_hwmod,
5725         .slave          = &omap44xx_timer9_hwmod,
5726         .clk            = "l4_div_ck",
5727         .addr           = omap44xx_timer9_addrs,
5728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5729 };
5730
5731 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5732         {
5733                 .pa_start       = 0x48086000,
5734                 .pa_end         = 0x4808607f,
5735                 .flags          = ADDR_TYPE_RT
5736         },
5737         { }
5738 };
5739
5740 /* l4_per -> timer10 */
5741 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5742         .master         = &omap44xx_l4_per_hwmod,
5743         .slave          = &omap44xx_timer10_hwmod,
5744         .clk            = "l4_div_ck",
5745         .addr           = omap44xx_timer10_addrs,
5746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5747 };
5748
5749 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5750         {
5751                 .pa_start       = 0x48088000,
5752                 .pa_end         = 0x4808807f,
5753                 .flags          = ADDR_TYPE_RT
5754         },
5755         { }
5756 };
5757
5758 /* l4_per -> timer11 */
5759 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5760         .master         = &omap44xx_l4_per_hwmod,
5761         .slave          = &omap44xx_timer11_hwmod,
5762         .clk            = "l4_div_ck",
5763         .addr           = omap44xx_timer11_addrs,
5764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5765 };
5766
5767 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5768         {
5769                 .pa_start       = 0x4806a000,
5770                 .pa_end         = 0x4806a0ff,
5771                 .flags          = ADDR_TYPE_RT
5772         },
5773         { }
5774 };
5775
5776 /* l4_per -> uart1 */
5777 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5778         .master         = &omap44xx_l4_per_hwmod,
5779         .slave          = &omap44xx_uart1_hwmod,
5780         .clk            = "l4_div_ck",
5781         .addr           = omap44xx_uart1_addrs,
5782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5783 };
5784
5785 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5786         {
5787                 .pa_start       = 0x4806c000,
5788                 .pa_end         = 0x4806c0ff,
5789                 .flags          = ADDR_TYPE_RT
5790         },
5791         { }
5792 };
5793
5794 /* l4_per -> uart2 */
5795 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5796         .master         = &omap44xx_l4_per_hwmod,
5797         .slave          = &omap44xx_uart2_hwmod,
5798         .clk            = "l4_div_ck",
5799         .addr           = omap44xx_uart2_addrs,
5800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5801 };
5802
5803 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5804         {
5805                 .pa_start       = 0x48020000,
5806                 .pa_end         = 0x480200ff,
5807                 .flags          = ADDR_TYPE_RT
5808         },
5809         { }
5810 };
5811
5812 /* l4_per -> uart3 */
5813 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5814         .master         = &omap44xx_l4_per_hwmod,
5815         .slave          = &omap44xx_uart3_hwmod,
5816         .clk            = "l4_div_ck",
5817         .addr           = omap44xx_uart3_addrs,
5818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5819 };
5820
5821 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5822         {
5823                 .pa_start       = 0x4806e000,
5824                 .pa_end         = 0x4806e0ff,
5825                 .flags          = ADDR_TYPE_RT
5826         },
5827         { }
5828 };
5829
5830 /* l4_per -> uart4 */
5831 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5832         .master         = &omap44xx_l4_per_hwmod,
5833         .slave          = &omap44xx_uart4_hwmod,
5834         .clk            = "l4_div_ck",
5835         .addr           = omap44xx_uart4_addrs,
5836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5837 };
5838
5839 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5840         {
5841                 .pa_start       = 0x4a0a9000,
5842                 .pa_end         = 0x4a0a93ff,
5843                 .flags          = ADDR_TYPE_RT
5844         },
5845         { }
5846 };
5847
5848 /* l4_cfg -> usb_host_fs */
5849 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5850         .master         = &omap44xx_l4_cfg_hwmod,
5851         .slave          = &omap44xx_usb_host_fs_hwmod,
5852         .clk            = "l4_div_ck",
5853         .addr           = omap44xx_usb_host_fs_addrs,
5854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5855 };
5856
5857 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5858         {
5859                 .name           = "uhh",
5860                 .pa_start       = 0x4a064000,
5861                 .pa_end         = 0x4a0647ff,
5862                 .flags          = ADDR_TYPE_RT
5863         },
5864         {
5865                 .name           = "ohci",
5866                 .pa_start       = 0x4a064800,
5867                 .pa_end         = 0x4a064bff,
5868         },
5869         {
5870                 .name           = "ehci",
5871                 .pa_start       = 0x4a064c00,
5872                 .pa_end         = 0x4a064fff,
5873         },
5874         {}
5875 };
5876
5877 /* l4_cfg -> usb_host_hs */
5878 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5879         .master         = &omap44xx_l4_cfg_hwmod,
5880         .slave          = &omap44xx_usb_host_hs_hwmod,
5881         .clk            = "l4_div_ck",
5882         .addr           = omap44xx_usb_host_hs_addrs,
5883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5884 };
5885
5886 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5887         {
5888                 .pa_start       = 0x4a0ab000,
5889                 .pa_end         = 0x4a0ab003,
5890                 .flags          = ADDR_TYPE_RT
5891         },
5892         {
5893                 /* XXX: Remove this once control module driver is in place */
5894                 .pa_start       = 0x4a00233c,
5895                 .pa_end         = 0x4a00233f,
5896                 .flags          = ADDR_TYPE_RT
5897         },
5898         { }
5899 };
5900
5901 /* l4_cfg -> usb_otg_hs */
5902 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5903         .master         = &omap44xx_l4_cfg_hwmod,
5904         .slave          = &omap44xx_usb_otg_hs_hwmod,
5905         .clk            = "l4_div_ck",
5906         .addr           = omap44xx_usb_otg_hs_addrs,
5907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5908 };
5909
5910 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5911         {
5912                 .name           = "tll",
5913                 .pa_start       = 0x4a062000,
5914                 .pa_end         = 0x4a063fff,
5915                 .flags          = ADDR_TYPE_RT
5916         },
5917         {}
5918 };
5919
5920 /* l4_cfg -> usb_tll_hs */
5921 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5922         .master         = &omap44xx_l4_cfg_hwmod,
5923         .slave          = &omap44xx_usb_tll_hs_hwmod,
5924         .clk            = "l4_div_ck",
5925         .addr           = omap44xx_usb_tll_hs_addrs,
5926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5927 };
5928
5929 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5930         {
5931                 .pa_start       = 0x4a314000,
5932                 .pa_end         = 0x4a31407f,
5933                 .flags          = ADDR_TYPE_RT
5934         },
5935         { }
5936 };
5937
5938 /* l4_wkup -> wd_timer2 */
5939 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5940         .master         = &omap44xx_l4_wkup_hwmod,
5941         .slave          = &omap44xx_wd_timer2_hwmod,
5942         .clk            = "l4_wkup_clk_mux_ck",
5943         .addr           = omap44xx_wd_timer2_addrs,
5944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5945 };
5946
5947 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5948         {
5949                 .pa_start       = 0x40130000,
5950                 .pa_end         = 0x4013007f,
5951                 .flags          = ADDR_TYPE_RT
5952         },
5953         { }
5954 };
5955
5956 /* l4_abe -> wd_timer3 */
5957 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5958         .master         = &omap44xx_l4_abe_hwmod,
5959         .slave          = &omap44xx_wd_timer3_hwmod,
5960         .clk            = "ocp_abe_iclk",
5961         .addr           = omap44xx_wd_timer3_addrs,
5962         .user           = OCP_USER_MPU,
5963 };
5964
5965 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5966         {
5967                 .pa_start       = 0x49030000,
5968                 .pa_end         = 0x4903007f,
5969                 .flags          = ADDR_TYPE_RT
5970         },
5971         { }
5972 };
5973
5974 /* l4_abe -> wd_timer3 (dma) */
5975 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5976         .master         = &omap44xx_l4_abe_hwmod,
5977         .slave          = &omap44xx_wd_timer3_hwmod,
5978         .clk            = "ocp_abe_iclk",
5979         .addr           = omap44xx_wd_timer3_dma_addrs,
5980         .user           = OCP_USER_SDMA,
5981 };
5982
5983 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5984         &omap44xx_c2c__c2c_target_fw,
5985         &omap44xx_l4_cfg__c2c_target_fw,
5986         &omap44xx_l3_main_1__dmm,
5987         &omap44xx_mpu__dmm,
5988         &omap44xx_c2c__emif_fw,
5989         &omap44xx_dmm__emif_fw,
5990         &omap44xx_l4_cfg__emif_fw,
5991         &omap44xx_iva__l3_instr,
5992         &omap44xx_l3_main_3__l3_instr,
5993         &omap44xx_ocp_wp_noc__l3_instr,
5994         &omap44xx_dsp__l3_main_1,
5995         &omap44xx_dss__l3_main_1,
5996         &omap44xx_l3_main_2__l3_main_1,
5997         &omap44xx_l4_cfg__l3_main_1,
5998         &omap44xx_mmc1__l3_main_1,
5999         &omap44xx_mmc2__l3_main_1,
6000         &omap44xx_mpu__l3_main_1,
6001         &omap44xx_c2c_target_fw__l3_main_2,
6002         &omap44xx_debugss__l3_main_2,
6003         &omap44xx_dma_system__l3_main_2,
6004         &omap44xx_fdif__l3_main_2,
6005         &omap44xx_gpu__l3_main_2,
6006         &omap44xx_hsi__l3_main_2,
6007         &omap44xx_ipu__l3_main_2,
6008         &omap44xx_iss__l3_main_2,
6009         &omap44xx_iva__l3_main_2,
6010         &omap44xx_l3_main_1__l3_main_2,
6011         &omap44xx_l4_cfg__l3_main_2,
6012         /* &omap44xx_usb_host_fs__l3_main_2, */
6013         &omap44xx_usb_host_hs__l3_main_2,
6014         &omap44xx_usb_otg_hs__l3_main_2,
6015         &omap44xx_l3_main_1__l3_main_3,
6016         &omap44xx_l3_main_2__l3_main_3,
6017         &omap44xx_l4_cfg__l3_main_3,
6018         /* &omap44xx_aess__l4_abe, */
6019         &omap44xx_dsp__l4_abe,
6020         &omap44xx_l3_main_1__l4_abe,
6021         &omap44xx_mpu__l4_abe,
6022         &omap44xx_l3_main_1__l4_cfg,
6023         &omap44xx_l3_main_2__l4_per,
6024         &omap44xx_l4_cfg__l4_wkup,
6025         &omap44xx_mpu__mpu_private,
6026         &omap44xx_l4_cfg__ocp_wp_noc,
6027         /* &omap44xx_l4_abe__aess, */
6028         /* &omap44xx_l4_abe__aess_dma, */
6029         &omap44xx_l3_main_2__c2c,
6030         &omap44xx_l4_wkup__counter_32k,
6031         &omap44xx_l4_cfg__ctrl_module_core,
6032         &omap44xx_l4_cfg__ctrl_module_pad_core,
6033         &omap44xx_l4_wkup__ctrl_module_wkup,
6034         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6035         &omap44xx_l3_instr__debugss,
6036         &omap44xx_l4_cfg__dma_system,
6037         &omap44xx_l4_abe__dmic,
6038         &omap44xx_l4_abe__dmic_dma,
6039         &omap44xx_dsp__iva,
6040         /* &omap44xx_dsp__sl2if, */
6041         &omap44xx_l4_cfg__dsp,
6042         &omap44xx_l3_main_2__dss,
6043         &omap44xx_l4_per__dss,
6044         &omap44xx_l3_main_2__dss_dispc,
6045         &omap44xx_l4_per__dss_dispc,
6046         &omap44xx_l3_main_2__dss_dsi1,
6047         &omap44xx_l4_per__dss_dsi1,
6048         &omap44xx_l3_main_2__dss_dsi2,
6049         &omap44xx_l4_per__dss_dsi2,
6050         &omap44xx_l3_main_2__dss_hdmi,
6051         &omap44xx_l4_per__dss_hdmi,
6052         &omap44xx_l3_main_2__dss_rfbi,
6053         &omap44xx_l4_per__dss_rfbi,
6054         &omap44xx_l3_main_2__dss_venc,
6055         &omap44xx_l4_per__dss_venc,
6056         &omap44xx_l4_per__elm,
6057         &omap44xx_emif_fw__emif1,
6058         &omap44xx_emif_fw__emif2,
6059         &omap44xx_l4_cfg__fdif,
6060         &omap44xx_l4_wkup__gpio1,
6061         &omap44xx_l4_per__gpio2,
6062         &omap44xx_l4_per__gpio3,
6063         &omap44xx_l4_per__gpio4,
6064         &omap44xx_l4_per__gpio5,
6065         &omap44xx_l4_per__gpio6,
6066         &omap44xx_l3_main_2__gpmc,
6067         &omap44xx_l3_main_2__gpu,
6068         &omap44xx_l4_per__hdq1w,
6069         &omap44xx_l4_cfg__hsi,
6070         &omap44xx_l4_per__i2c1,
6071         &omap44xx_l4_per__i2c2,
6072         &omap44xx_l4_per__i2c3,
6073         &omap44xx_l4_per__i2c4,
6074         &omap44xx_l3_main_2__ipu,
6075         &omap44xx_l3_main_2__iss,
6076         /* &omap44xx_iva__sl2if, */
6077         &omap44xx_l3_main_2__iva,
6078         &omap44xx_l4_wkup__kbd,
6079         &omap44xx_l4_cfg__mailbox,
6080         &omap44xx_l4_abe__mcasp,
6081         &omap44xx_l4_abe__mcasp_dma,
6082         &omap44xx_l4_abe__mcbsp1,
6083         &omap44xx_l4_abe__mcbsp1_dma,
6084         &omap44xx_l4_abe__mcbsp2,
6085         &omap44xx_l4_abe__mcbsp2_dma,
6086         &omap44xx_l4_abe__mcbsp3,
6087         &omap44xx_l4_abe__mcbsp3_dma,
6088         &omap44xx_l4_per__mcbsp4,
6089         &omap44xx_l4_abe__mcpdm,
6090         &omap44xx_l4_abe__mcpdm_dma,
6091         &omap44xx_l4_per__mcspi1,
6092         &omap44xx_l4_per__mcspi2,
6093         &omap44xx_l4_per__mcspi3,
6094         &omap44xx_l4_per__mcspi4,
6095         &omap44xx_l4_per__mmc1,
6096         &omap44xx_l4_per__mmc2,
6097         &omap44xx_l4_per__mmc3,
6098         &omap44xx_l4_per__mmc4,
6099         &omap44xx_l4_per__mmc5,
6100         &omap44xx_l3_main_2__ocmc_ram,
6101         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6102         &omap44xx_mpu_private__prcm_mpu,
6103         &omap44xx_l4_wkup__cm_core_aon,
6104         &omap44xx_l4_cfg__cm_core,
6105         &omap44xx_l4_wkup__prm,
6106         &omap44xx_l4_wkup__scrm,
6107         /* &omap44xx_l3_main_2__sl2if, */
6108         &omap44xx_l4_abe__slimbus1,
6109         &omap44xx_l4_abe__slimbus1_dma,
6110         &omap44xx_l4_per__slimbus2,
6111         &omap44xx_l4_cfg__smartreflex_core,
6112         &omap44xx_l4_cfg__smartreflex_iva,
6113         &omap44xx_l4_cfg__smartreflex_mpu,
6114         &omap44xx_l4_cfg__spinlock,
6115         &omap44xx_l4_wkup__timer1,
6116         &omap44xx_l4_per__timer2,
6117         &omap44xx_l4_per__timer3,
6118         &omap44xx_l4_per__timer4,
6119         &omap44xx_l4_abe__timer5,
6120         &omap44xx_l4_abe__timer5_dma,
6121         &omap44xx_l4_abe__timer6,
6122         &omap44xx_l4_abe__timer6_dma,
6123         &omap44xx_l4_abe__timer7,
6124         &omap44xx_l4_abe__timer7_dma,
6125         &omap44xx_l4_abe__timer8,
6126         &omap44xx_l4_abe__timer8_dma,
6127         &omap44xx_l4_per__timer9,
6128         &omap44xx_l4_per__timer10,
6129         &omap44xx_l4_per__timer11,
6130         &omap44xx_l4_per__uart1,
6131         &omap44xx_l4_per__uart2,
6132         &omap44xx_l4_per__uart3,
6133         &omap44xx_l4_per__uart4,
6134         /* &omap44xx_l4_cfg__usb_host_fs, */
6135         &omap44xx_l4_cfg__usb_host_hs,
6136         &omap44xx_l4_cfg__usb_otg_hs,
6137         &omap44xx_l4_cfg__usb_tll_hs,
6138         &omap44xx_l4_wkup__wd_timer2,
6139         &omap44xx_l4_abe__wd_timer3,
6140         &omap44xx_l4_abe__wd_timer3_dma,
6141         NULL,
6142 };
6143
6144 int __init omap44xx_hwmod_init(void)
6145 {
6146         omap_hwmod_init();
6147         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6148 }
6149