4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/platform_data/gpio-omap.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include <linux/platform_data/spi-omap2-mcspi.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod_common_data.h"
29 * DM816X hardware modules integration data
31 * Note: This is incomplete and at present, not generated from h/w database.
35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
68 /* Registers specific to dm814x */
69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
86 /* Registers specific to dm816x */
87 #define DM816X_DM_ALWON_BASE 0x1400
88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
107 #define DM81XX_CM_DEFAULT_OFFSET 0x500
108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
112 .name = "alwon_l3_slow",
113 .clkdm_name = "alwon_l3s_clkdm",
114 .class = &l3_hwmod_class,
115 .flags = HWMOD_NO_IDLEST,
118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
119 .name = "default_l3_slow",
120 .clkdm_name = "default_l3_slow_clkdm",
121 .class = &l3_hwmod_class,
122 .flags = HWMOD_NO_IDLEST,
125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
127 .clkdm_name = "alwon_l3_med_clkdm",
128 .class = &l3_hwmod_class,
129 .flags = HWMOD_NO_IDLEST,
132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
134 .clkdm_name = "alwon_l3_fast_clkdm",
135 .class = &l3_hwmod_class,
136 .flags = HWMOD_NO_IDLEST,
140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
145 .clkdm_name = "alwon_l3s_clkdm",
146 .class = &l4_hwmod_class,
147 .flags = HWMOD_NO_IDLEST,
151 * L4 high-speed peripherals. For devices using this, please see the TRM
152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
153 * table 1-73 for devices using 250MHz SYSCLK5 clock.
155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
157 .clkdm_name = "alwon_l3_med_clkdm",
158 .class = &l4_hwmod_class,
159 .flags = HWMOD_NO_IDLEST,
162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
164 .master = &dm81xx_alwon_l3_slow_hwmod,
165 .slave = &dm81xx_l4_ls_hwmod,
166 .user = OCP_USER_MPU,
169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
171 .master = &dm81xx_alwon_l3_med_hwmod,
172 .slave = &dm81xx_l4_hs_hwmod,
173 .user = OCP_USER_MPU,
177 static struct omap_hwmod dm814x_mpu_hwmod = {
179 .clkdm_name = "alwon_l3s_clkdm",
180 .class = &mpu_hwmod_class,
181 .flags = HWMOD_INIT_NO_IDLE,
182 .main_clk = "mpu_ck",
185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
186 .modulemode = MODULEMODE_SWCTRL,
191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
192 .master = &dm814x_mpu_hwmod,
193 .slave = &dm81xx_alwon_l3_slow_hwmod,
194 .user = OCP_USER_MPU,
197 /* L3 med peripheral interface running at 200MHz */
198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
199 .master = &dm814x_mpu_hwmod,
200 .slave = &dm81xx_alwon_l3_med_hwmod,
201 .user = OCP_USER_MPU,
204 static struct omap_hwmod dm816x_mpu_hwmod = {
206 .clkdm_name = "alwon_mpu_clkdm",
207 .class = &mpu_hwmod_class,
208 .flags = HWMOD_INIT_NO_IDLE,
209 .main_clk = "mpu_ck",
212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
213 .modulemode = MODULEMODE_SWCTRL,
218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
219 .master = &dm816x_mpu_hwmod,
220 .slave = &dm81xx_alwon_l3_slow_hwmod,
221 .user = OCP_USER_MPU,
224 /* L3 med peripheral interface running at 250MHz */
225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
226 .master = &dm816x_mpu_hwmod,
227 .slave = &dm81xx_alwon_l3_med_hwmod,
228 .user = OCP_USER_MPU,
232 static struct omap_hwmod_class_sysconfig uart_sysc = {
236 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
237 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
238 SYSS_HAS_RESET_STATUS,
239 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
241 .sysc_fields = &omap_hwmod_sysc_type1,
244 static struct omap_hwmod_class uart_class = {
249 static struct omap_hwmod dm81xx_uart1_hwmod = {
251 .clkdm_name = "alwon_l3s_clkdm",
252 .main_clk = "sysclk10_ck",
255 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
256 .modulemode = MODULEMODE_SWCTRL,
259 .class = &uart_class,
260 .flags = DEBUG_TI81XXUART1_FLAGS,
263 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
264 .master = &dm81xx_l4_ls_hwmod,
265 .slave = &dm81xx_uart1_hwmod,
267 .user = OCP_USER_MPU,
270 static struct omap_hwmod dm81xx_uart2_hwmod = {
272 .clkdm_name = "alwon_l3s_clkdm",
273 .main_clk = "sysclk10_ck",
276 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
277 .modulemode = MODULEMODE_SWCTRL,
280 .class = &uart_class,
281 .flags = DEBUG_TI81XXUART2_FLAGS,
284 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
285 .master = &dm81xx_l4_ls_hwmod,
286 .slave = &dm81xx_uart2_hwmod,
288 .user = OCP_USER_MPU,
291 static struct omap_hwmod dm81xx_uart3_hwmod = {
293 .clkdm_name = "alwon_l3s_clkdm",
294 .main_clk = "sysclk10_ck",
297 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
298 .modulemode = MODULEMODE_SWCTRL,
301 .class = &uart_class,
302 .flags = DEBUG_TI81XXUART3_FLAGS,
305 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
306 .master = &dm81xx_l4_ls_hwmod,
307 .slave = &dm81xx_uart3_hwmod,
309 .user = OCP_USER_MPU,
312 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
316 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
317 SYSS_HAS_RESET_STATUS,
318 .sysc_fields = &omap_hwmod_sysc_type1,
321 static struct omap_hwmod_class wd_timer_class = {
323 .sysc = &wd_timer_sysc,
324 .pre_shutdown = &omap2_wd_timer_disable,
325 .reset = &omap2_wd_timer_reset,
328 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
330 .clkdm_name = "alwon_l3s_clkdm",
331 .main_clk = "sysclk18_ck",
332 .flags = HWMOD_NO_IDLEST,
335 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
336 .modulemode = MODULEMODE_SWCTRL,
339 .class = &wd_timer_class,
342 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
343 .master = &dm81xx_l4_ls_hwmod,
344 .slave = &dm81xx_wd_timer_hwmod,
346 .user = OCP_USER_MPU,
350 static struct omap_hwmod_class_sysconfig i2c_sysc = {
354 .sysc_flags = SYSC_HAS_SIDLEMODE |
355 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
357 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
358 .sysc_fields = &omap_hwmod_sysc_type1,
361 static struct omap_hwmod_class i2c_class = {
366 static struct omap_hwmod dm81xx_i2c1_hwmod = {
368 .clkdm_name = "alwon_l3s_clkdm",
369 .main_clk = "sysclk10_ck",
372 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
373 .modulemode = MODULEMODE_SWCTRL,
379 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
380 .master = &dm81xx_l4_ls_hwmod,
381 .slave = &dm81xx_i2c1_hwmod,
383 .user = OCP_USER_MPU,
386 static struct omap_hwmod dm81xx_i2c2_hwmod = {
388 .clkdm_name = "alwon_l3s_clkdm",
389 .main_clk = "sysclk10_ck",
392 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
393 .modulemode = MODULEMODE_SWCTRL,
399 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
403 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
405 SYSS_HAS_RESET_STATUS,
406 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
407 .sysc_fields = &omap_hwmod_sysc_type1,
410 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
411 .master = &dm81xx_l4_ls_hwmod,
412 .slave = &dm81xx_i2c2_hwmod,
414 .user = OCP_USER_MPU,
417 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
419 .sysc = &dm81xx_elm_sysc,
422 static struct omap_hwmod dm81xx_elm_hwmod = {
424 .clkdm_name = "alwon_l3s_clkdm",
425 .class = &dm81xx_elm_hwmod_class,
426 .main_clk = "sysclk6_ck",
429 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
430 .master = &dm81xx_l4_ls_hwmod,
431 .slave = &dm81xx_elm_hwmod,
432 .user = OCP_USER_MPU,
435 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
439 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
440 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
441 SYSS_HAS_RESET_STATUS,
442 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
444 .sysc_fields = &omap_hwmod_sysc_type1,
447 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
449 .sysc = &dm81xx_gpio_sysc,
453 static struct omap_gpio_dev_attr gpio_dev_attr = {
458 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
459 { .role = "dbclk", .clk = "sysclk18_ck" },
462 static struct omap_hwmod dm81xx_gpio1_hwmod = {
464 .clkdm_name = "alwon_l3s_clkdm",
465 .class = &dm81xx_gpio_hwmod_class,
466 .main_clk = "sysclk6_ck",
469 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
470 .modulemode = MODULEMODE_SWCTRL,
473 .opt_clks = gpio1_opt_clks,
474 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
475 .dev_attr = &gpio_dev_attr,
478 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
479 .master = &dm81xx_l4_ls_hwmod,
480 .slave = &dm81xx_gpio1_hwmod,
481 .user = OCP_USER_MPU,
484 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
485 { .role = "dbclk", .clk = "sysclk18_ck" },
488 static struct omap_hwmod dm81xx_gpio2_hwmod = {
490 .clkdm_name = "alwon_l3s_clkdm",
491 .class = &dm81xx_gpio_hwmod_class,
492 .main_clk = "sysclk6_ck",
495 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
496 .modulemode = MODULEMODE_SWCTRL,
499 .opt_clks = gpio2_opt_clks,
500 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
501 .dev_attr = &gpio_dev_attr,
504 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
505 .master = &dm81xx_l4_ls_hwmod,
506 .slave = &dm81xx_gpio2_hwmod,
507 .user = OCP_USER_MPU,
510 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
514 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
516 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
517 .sysc_fields = &omap_hwmod_sysc_type1,
520 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
522 .sysc = &dm81xx_gpmc_sysc,
525 static struct omap_hwmod dm81xx_gpmc_hwmod = {
527 .clkdm_name = "alwon_l3s_clkdm",
528 .class = &dm81xx_gpmc_hwmod_class,
529 .main_clk = "sysclk6_ck",
530 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
531 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
534 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
535 .modulemode = MODULEMODE_SWCTRL,
540 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
541 .master = &dm81xx_alwon_l3_slow_hwmod,
542 .slave = &dm81xx_gpmc_hwmod,
543 .user = OCP_USER_MPU,
546 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
549 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
551 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
552 .sysc_fields = &omap_hwmod_sysc_type2,
555 static struct omap_hwmod_class dm81xx_usbotg_class = {
557 .sysc = &dm81xx_usbhsotg_sysc,
560 static struct omap_hwmod dm814x_usbss_hwmod = {
561 .name = "usb_otg_hs",
562 .clkdm_name = "default_l3_slow_clkdm",
563 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */
566 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
567 .modulemode = MODULEMODE_SWCTRL,
570 .class = &dm81xx_usbotg_class,
573 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
574 .master = &dm81xx_default_l3_slow_hwmod,
575 .slave = &dm814x_usbss_hwmod,
577 .user = OCP_USER_MPU,
580 static struct omap_hwmod dm816x_usbss_hwmod = {
581 .name = "usb_otg_hs",
582 .clkdm_name = "default_l3_slow_clkdm",
583 .main_clk = "sysclk6_ck",
586 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
587 .modulemode = MODULEMODE_SWCTRL,
590 .class = &dm81xx_usbotg_class,
593 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
594 .master = &dm81xx_default_l3_slow_hwmod,
595 .slave = &dm816x_usbss_hwmod,
597 .user = OCP_USER_MPU,
600 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
604 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
605 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 .sysc_fields = &omap_hwmod_sysc_type2,
610 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
612 .sysc = &dm816x_timer_sysc,
615 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
616 .timer_capability = OMAP_TIMER_ALWON,
619 static struct omap_hwmod dm814x_timer1_hwmod = {
621 .clkdm_name = "alwon_l3s_clkdm",
622 .main_clk = "timer1_fck",
623 .dev_attr = &capability_alwon_dev_attr,
624 .class = &dm816x_timer_hwmod_class,
625 .flags = HWMOD_NO_IDLEST,
628 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
629 .master = &dm81xx_l4_ls_hwmod,
630 .slave = &dm814x_timer1_hwmod,
632 .user = OCP_USER_MPU,
635 static struct omap_hwmod dm816x_timer1_hwmod = {
637 .clkdm_name = "alwon_l3s_clkdm",
638 .main_clk = "timer1_fck",
641 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
642 .modulemode = MODULEMODE_SWCTRL,
645 .dev_attr = &capability_alwon_dev_attr,
646 .class = &dm816x_timer_hwmod_class,
649 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
650 .master = &dm81xx_l4_ls_hwmod,
651 .slave = &dm816x_timer1_hwmod,
653 .user = OCP_USER_MPU,
656 static struct omap_hwmod dm814x_timer2_hwmod = {
658 .clkdm_name = "alwon_l3s_clkdm",
659 .main_clk = "timer2_fck",
660 .dev_attr = &capability_alwon_dev_attr,
661 .class = &dm816x_timer_hwmod_class,
662 .flags = HWMOD_NO_IDLEST,
665 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
666 .master = &dm81xx_l4_ls_hwmod,
667 .slave = &dm814x_timer2_hwmod,
669 .user = OCP_USER_MPU,
672 static struct omap_hwmod dm816x_timer2_hwmod = {
674 .clkdm_name = "alwon_l3s_clkdm",
675 .main_clk = "timer2_fck",
678 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
679 .modulemode = MODULEMODE_SWCTRL,
682 .dev_attr = &capability_alwon_dev_attr,
683 .class = &dm816x_timer_hwmod_class,
686 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
687 .master = &dm81xx_l4_ls_hwmod,
688 .slave = &dm816x_timer2_hwmod,
690 .user = OCP_USER_MPU,
693 static struct omap_hwmod dm816x_timer3_hwmod = {
695 .clkdm_name = "alwon_l3s_clkdm",
696 .main_clk = "timer3_fck",
699 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
700 .modulemode = MODULEMODE_SWCTRL,
703 .dev_attr = &capability_alwon_dev_attr,
704 .class = &dm816x_timer_hwmod_class,
707 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
708 .master = &dm81xx_l4_ls_hwmod,
709 .slave = &dm816x_timer3_hwmod,
711 .user = OCP_USER_MPU,
714 static struct omap_hwmod dm816x_timer4_hwmod = {
716 .clkdm_name = "alwon_l3s_clkdm",
717 .main_clk = "timer4_fck",
720 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
721 .modulemode = MODULEMODE_SWCTRL,
724 .dev_attr = &capability_alwon_dev_attr,
725 .class = &dm816x_timer_hwmod_class,
728 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
729 .master = &dm81xx_l4_ls_hwmod,
730 .slave = &dm816x_timer4_hwmod,
732 .user = OCP_USER_MPU,
735 static struct omap_hwmod dm816x_timer5_hwmod = {
737 .clkdm_name = "alwon_l3s_clkdm",
738 .main_clk = "timer5_fck",
741 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
742 .modulemode = MODULEMODE_SWCTRL,
745 .dev_attr = &capability_alwon_dev_attr,
746 .class = &dm816x_timer_hwmod_class,
749 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
750 .master = &dm81xx_l4_ls_hwmod,
751 .slave = &dm816x_timer5_hwmod,
753 .user = OCP_USER_MPU,
756 static struct omap_hwmod dm816x_timer6_hwmod = {
758 .clkdm_name = "alwon_l3s_clkdm",
759 .main_clk = "timer6_fck",
762 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
763 .modulemode = MODULEMODE_SWCTRL,
766 .dev_attr = &capability_alwon_dev_attr,
767 .class = &dm816x_timer_hwmod_class,
770 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
771 .master = &dm81xx_l4_ls_hwmod,
772 .slave = &dm816x_timer6_hwmod,
774 .user = OCP_USER_MPU,
777 static struct omap_hwmod dm816x_timer7_hwmod = {
779 .clkdm_name = "alwon_l3s_clkdm",
780 .main_clk = "timer7_fck",
783 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
784 .modulemode = MODULEMODE_SWCTRL,
787 .dev_attr = &capability_alwon_dev_attr,
788 .class = &dm816x_timer_hwmod_class,
791 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
792 .master = &dm81xx_l4_ls_hwmod,
793 .slave = &dm816x_timer7_hwmod,
795 .user = OCP_USER_MPU,
799 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
803 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
804 SYSS_HAS_RESET_STATUS,
805 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
807 .sysc_fields = &omap_hwmod_sysc_type3,
810 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
812 .sysc = &dm814x_cpgmac_sysc,
815 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
817 .class = &dm814x_cpgmac0_hwmod_class,
818 .clkdm_name = "alwon_ethernet_clkdm",
819 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
820 .main_clk = "cpsw_125mhz_gclk",
823 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
824 .modulemode = MODULEMODE_SWCTRL,
829 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
830 .name = "davinci_mdio",
833 static struct omap_hwmod dm814x_mdio_hwmod = {
834 .name = "davinci_mdio",
835 .class = &dm814x_mdio_hwmod_class,
836 .clkdm_name = "alwon_ethernet_clkdm",
837 .main_clk = "cpsw_125mhz_gclk",
840 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
841 .master = &dm81xx_l4_hs_hwmod,
842 .slave = &dm814x_cpgmac0_hwmod,
843 .clk = "cpsw_125mhz_gclk",
844 .user = OCP_USER_MPU,
847 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
848 .master = &dm814x_cpgmac0_hwmod,
849 .slave = &dm814x_mdio_hwmod,
850 .user = OCP_USER_MPU,
851 .flags = HWMOD_NO_IDLEST,
855 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
858 .sysc_flags = SYSC_HAS_SOFTRESET,
859 .sysc_fields = &omap_hwmod_sysc_type2,
862 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
864 .sysc = &dm816x_emac_sysc,
868 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
869 * driver probed before EMAC0, we let MDIO do the clock idling.
871 static struct omap_hwmod dm816x_emac0_hwmod = {
873 .clkdm_name = "alwon_ethernet_clkdm",
874 .class = &dm816x_emac_hwmod_class,
875 .flags = HWMOD_NO_IDLEST,
878 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
879 .master = &dm81xx_l4_hs_hwmod,
880 .slave = &dm816x_emac0_hwmod,
882 .user = OCP_USER_MPU,
885 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
886 .name = "davinci_mdio",
887 .sysc = &dm816x_emac_sysc,
890 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
891 .name = "davinci_mdio",
892 .class = &dm81xx_mdio_hwmod_class,
893 .clkdm_name = "alwon_ethernet_clkdm",
894 .main_clk = "sysclk24_ck",
895 .flags = HWMOD_NO_IDLEST,
897 * REVISIT: This should be moved to the emac0_hwmod
898 * once we have a better way to handle device slaves.
902 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
903 .modulemode = MODULEMODE_SWCTRL,
908 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
909 .master = &dm81xx_l4_hs_hwmod,
910 .slave = &dm81xx_emac0_mdio_hwmod,
911 .user = OCP_USER_MPU,
914 static struct omap_hwmod dm816x_emac1_hwmod = {
916 .clkdm_name = "alwon_ethernet_clkdm",
917 .main_clk = "sysclk24_ck",
918 .flags = HWMOD_NO_IDLEST,
921 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
922 .modulemode = MODULEMODE_SWCTRL,
925 .class = &dm816x_emac_hwmod_class,
928 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
929 .master = &dm81xx_l4_hs_hwmod,
930 .slave = &dm816x_emac1_hwmod,
932 .user = OCP_USER_MPU,
935 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
939 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
940 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
941 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
942 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
943 .sysc_fields = &omap_hwmod_sysc_type1,
946 static struct omap_hwmod_class dm81xx_mmc_class = {
948 .sysc = &dm81xx_mmc_sysc,
951 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
952 { .role = "dbck", .clk = "sysclk18_ck", },
955 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
958 static struct omap_hwmod dm814x_mmc1_hwmod = {
960 .clkdm_name = "alwon_l3s_clkdm",
961 .opt_clks = dm81xx_mmc_opt_clks,
962 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
963 .main_clk = "sysclk8_ck",
966 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
967 .modulemode = MODULEMODE_SWCTRL,
970 .dev_attr = &mmc_dev_attr,
971 .class = &dm81xx_mmc_class,
974 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
975 .master = &dm81xx_l4_ls_hwmod,
976 .slave = &dm814x_mmc1_hwmod,
978 .user = OCP_USER_MPU,
979 .flags = OMAP_FIREWALL_L4
982 static struct omap_hwmod dm814x_mmc2_hwmod = {
984 .clkdm_name = "alwon_l3s_clkdm",
985 .opt_clks = dm81xx_mmc_opt_clks,
986 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
987 .main_clk = "sysclk8_ck",
990 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
991 .modulemode = MODULEMODE_SWCTRL,
994 .dev_attr = &mmc_dev_attr,
995 .class = &dm81xx_mmc_class,
998 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
999 .master = &dm81xx_l4_ls_hwmod,
1000 .slave = &dm814x_mmc2_hwmod,
1001 .clk = "sysclk6_ck",
1002 .user = OCP_USER_MPU,
1003 .flags = OMAP_FIREWALL_L4
1006 static struct omap_hwmod dm814x_mmc3_hwmod = {
1008 .clkdm_name = "alwon_l3_med_clkdm",
1009 .opt_clks = dm81xx_mmc_opt_clks,
1010 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1011 .main_clk = "sysclk8_ck",
1014 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1015 .modulemode = MODULEMODE_SWCTRL,
1018 .dev_attr = &mmc_dev_attr,
1019 .class = &dm81xx_mmc_class,
1022 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1023 .master = &dm81xx_alwon_l3_med_hwmod,
1024 .slave = &dm814x_mmc3_hwmod,
1025 .clk = "sysclk4_ck",
1026 .user = OCP_USER_MPU,
1029 static struct omap_hwmod dm816x_mmc1_hwmod = {
1031 .clkdm_name = "alwon_l3s_clkdm",
1032 .opt_clks = dm81xx_mmc_opt_clks,
1033 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1034 .main_clk = "sysclk10_ck",
1037 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1038 .modulemode = MODULEMODE_SWCTRL,
1041 .dev_attr = &mmc_dev_attr,
1042 .class = &dm81xx_mmc_class,
1045 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1046 .master = &dm81xx_l4_ls_hwmod,
1047 .slave = &dm816x_mmc1_hwmod,
1048 .clk = "sysclk6_ck",
1049 .user = OCP_USER_MPU,
1050 .flags = OMAP_FIREWALL_L4
1053 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1057 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1058 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1059 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1060 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1061 .sysc_fields = &omap_hwmod_sysc_type1,
1064 static struct omap_hwmod_class dm816x_mcspi_class = {
1066 .sysc = &dm816x_mcspi_sysc,
1067 .rev = OMAP3_MCSPI_REV,
1070 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1071 .num_chipselect = 4,
1074 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1076 .clkdm_name = "alwon_l3s_clkdm",
1077 .main_clk = "sysclk10_ck",
1080 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1081 .modulemode = MODULEMODE_SWCTRL,
1084 .class = &dm816x_mcspi_class,
1085 .dev_attr = &dm816x_mcspi1_dev_attr,
1088 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1089 .master = &dm81xx_l4_ls_hwmod,
1090 .slave = &dm81xx_mcspi1_hwmod,
1091 .clk = "sysclk6_ck",
1092 .user = OCP_USER_MPU,
1095 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1099 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1100 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1101 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1102 .sysc_fields = &omap_hwmod_sysc_type1,
1105 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1107 .sysc = &dm81xx_mailbox_sysc,
1110 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1112 .clkdm_name = "alwon_l3s_clkdm",
1113 .class = &dm81xx_mailbox_hwmod_class,
1114 .main_clk = "sysclk6_ck",
1117 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1118 .modulemode = MODULEMODE_SWCTRL,
1123 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1124 .master = &dm81xx_l4_ls_hwmod,
1125 .slave = &dm81xx_mailbox_hwmod,
1126 .user = OCP_USER_MPU,
1129 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1133 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1134 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1135 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1136 .sysc_fields = &omap_hwmod_sysc_type1,
1139 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1141 .sysc = &dm81xx_spinbox_sysc,
1144 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1146 .clkdm_name = "alwon_l3s_clkdm",
1147 .class = &dm81xx_spinbox_hwmod_class,
1148 .main_clk = "sysclk6_ck",
1151 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1152 .modulemode = MODULEMODE_SWCTRL,
1157 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1158 .master = &dm81xx_l4_ls_hwmod,
1159 .slave = &dm81xx_spinbox_hwmod,
1160 .user = OCP_USER_MPU,
1163 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1167 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1169 .class = &dm81xx_tpcc_hwmod_class,
1170 .clkdm_name = "alwon_l3s_clkdm",
1171 .main_clk = "sysclk4_ck",
1174 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1175 .modulemode = MODULEMODE_SWCTRL,
1180 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1181 .master = &dm81xx_alwon_l3_fast_hwmod,
1182 .slave = &dm81xx_tpcc_hwmod,
1183 .clk = "sysclk4_ck",
1184 .user = OCP_USER_MPU,
1187 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
1189 .pa_start = 0x49800000,
1190 .pa_end = 0x49800000 + SZ_8K - 1,
1191 .flags = ADDR_TYPE_RT,
1196 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1200 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1202 .class = &dm81xx_tptc0_hwmod_class,
1203 .clkdm_name = "alwon_l3s_clkdm",
1204 .main_clk = "sysclk4_ck",
1207 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1208 .modulemode = MODULEMODE_SWCTRL,
1213 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1214 .master = &dm81xx_alwon_l3_fast_hwmod,
1215 .slave = &dm81xx_tptc0_hwmod,
1216 .clk = "sysclk4_ck",
1217 .addr = dm81xx_tptc0_addr_space,
1218 .user = OCP_USER_MPU,
1221 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1222 .master = &dm81xx_tptc0_hwmod,
1223 .slave = &dm81xx_alwon_l3_fast_hwmod,
1224 .clk = "sysclk4_ck",
1225 .addr = dm81xx_tptc0_addr_space,
1226 .user = OCP_USER_MPU,
1229 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
1231 .pa_start = 0x49900000,
1232 .pa_end = 0x49900000 + SZ_8K - 1,
1233 .flags = ADDR_TYPE_RT,
1238 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1242 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1244 .class = &dm81xx_tptc1_hwmod_class,
1245 .clkdm_name = "alwon_l3s_clkdm",
1246 .main_clk = "sysclk4_ck",
1249 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1250 .modulemode = MODULEMODE_SWCTRL,
1255 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1256 .master = &dm81xx_alwon_l3_fast_hwmod,
1257 .slave = &dm81xx_tptc1_hwmod,
1258 .clk = "sysclk4_ck",
1259 .addr = dm81xx_tptc1_addr_space,
1260 .user = OCP_USER_MPU,
1263 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1264 .master = &dm81xx_tptc1_hwmod,
1265 .slave = &dm81xx_alwon_l3_fast_hwmod,
1266 .clk = "sysclk4_ck",
1267 .addr = dm81xx_tptc1_addr_space,
1268 .user = OCP_USER_MPU,
1271 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1273 .pa_start = 0x49a00000,
1274 .pa_end = 0x49a00000 + SZ_8K - 1,
1275 .flags = ADDR_TYPE_RT,
1280 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1284 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1286 .class = &dm81xx_tptc2_hwmod_class,
1287 .clkdm_name = "alwon_l3s_clkdm",
1288 .main_clk = "sysclk4_ck",
1291 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1292 .modulemode = MODULEMODE_SWCTRL,
1297 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1298 .master = &dm81xx_alwon_l3_fast_hwmod,
1299 .slave = &dm81xx_tptc2_hwmod,
1300 .clk = "sysclk4_ck",
1301 .addr = dm81xx_tptc2_addr_space,
1302 .user = OCP_USER_MPU,
1305 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1306 .master = &dm81xx_tptc2_hwmod,
1307 .slave = &dm81xx_alwon_l3_fast_hwmod,
1308 .clk = "sysclk4_ck",
1309 .addr = dm81xx_tptc2_addr_space,
1310 .user = OCP_USER_MPU,
1313 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1315 .pa_start = 0x49b00000,
1316 .pa_end = 0x49b00000 + SZ_8K - 1,
1317 .flags = ADDR_TYPE_RT,
1322 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1326 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1328 .class = &dm81xx_tptc3_hwmod_class,
1329 .clkdm_name = "alwon_l3s_clkdm",
1330 .main_clk = "sysclk4_ck",
1333 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1334 .modulemode = MODULEMODE_SWCTRL,
1339 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1340 .master = &dm81xx_alwon_l3_fast_hwmod,
1341 .slave = &dm81xx_tptc3_hwmod,
1342 .clk = "sysclk4_ck",
1343 .addr = dm81xx_tptc3_addr_space,
1344 .user = OCP_USER_MPU,
1347 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1348 .master = &dm81xx_tptc3_hwmod,
1349 .slave = &dm81xx_alwon_l3_fast_hwmod,
1350 .clk = "sysclk4_ck",
1351 .addr = dm81xx_tptc3_addr_space,
1352 .user = OCP_USER_MPU,
1356 * REVISIT: Test and enable the following once clocks work:
1357 * dm81xx_l4_ls__mailbox
1359 * Also note that some devices share a single clkctrl_offs..
1360 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1362 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1363 &dm814x_mpu__alwon_l3_slow,
1364 &dm814x_mpu__alwon_l3_med,
1365 &dm81xx_alwon_l3_slow__l4_ls,
1366 &dm81xx_alwon_l3_slow__l4_hs,
1367 &dm81xx_l4_ls__uart1,
1368 &dm81xx_l4_ls__uart2,
1369 &dm81xx_l4_ls__uart3,
1370 &dm81xx_l4_ls__wd_timer1,
1371 &dm81xx_l4_ls__i2c1,
1372 &dm81xx_l4_ls__i2c2,
1373 &dm81xx_l4_ls__gpio1,
1374 &dm81xx_l4_ls__gpio2,
1376 &dm81xx_l4_ls__mcspi1,
1377 &dm814x_l4_ls__mmc1,
1378 &dm814x_l4_ls__mmc2,
1379 &dm81xx_alwon_l3_fast__tpcc,
1380 &dm81xx_alwon_l3_fast__tptc0,
1381 &dm81xx_alwon_l3_fast__tptc1,
1382 &dm81xx_alwon_l3_fast__tptc2,
1383 &dm81xx_alwon_l3_fast__tptc3,
1384 &dm81xx_tptc0__alwon_l3_fast,
1385 &dm81xx_tptc1__alwon_l3_fast,
1386 &dm81xx_tptc2__alwon_l3_fast,
1387 &dm81xx_tptc3__alwon_l3_fast,
1388 &dm814x_l4_ls__timer1,
1389 &dm814x_l4_ls__timer2,
1390 &dm814x_l4_hs__cpgmac0,
1391 &dm814x_cpgmac0__mdio,
1392 &dm81xx_alwon_l3_slow__gpmc,
1393 &dm814x_default_l3_slow__usbss,
1394 &dm814x_alwon_l3_med__mmc3,
1398 int __init dm814x_hwmod_init(void)
1401 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1404 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1405 &dm816x_mpu__alwon_l3_slow,
1406 &dm816x_mpu__alwon_l3_med,
1407 &dm81xx_alwon_l3_slow__l4_ls,
1408 &dm81xx_alwon_l3_slow__l4_hs,
1409 &dm81xx_l4_ls__uart1,
1410 &dm81xx_l4_ls__uart2,
1411 &dm81xx_l4_ls__uart3,
1412 &dm81xx_l4_ls__wd_timer1,
1413 &dm81xx_l4_ls__i2c1,
1414 &dm81xx_l4_ls__i2c2,
1415 &dm81xx_l4_ls__gpio1,
1416 &dm81xx_l4_ls__gpio2,
1418 &dm816x_l4_ls__mmc1,
1419 &dm816x_l4_ls__timer1,
1420 &dm816x_l4_ls__timer2,
1421 &dm816x_l4_ls__timer3,
1422 &dm816x_l4_ls__timer4,
1423 &dm816x_l4_ls__timer5,
1424 &dm816x_l4_ls__timer6,
1425 &dm816x_l4_ls__timer7,
1426 &dm81xx_l4_ls__mcspi1,
1427 &dm81xx_l4_ls__mailbox,
1428 &dm81xx_l4_ls__spinbox,
1429 &dm81xx_l4_hs__emac0,
1430 &dm81xx_emac0__mdio,
1431 &dm816x_l4_hs__emac1,
1432 &dm81xx_alwon_l3_fast__tpcc,
1433 &dm81xx_alwon_l3_fast__tptc0,
1434 &dm81xx_alwon_l3_fast__tptc1,
1435 &dm81xx_alwon_l3_fast__tptc2,
1436 &dm81xx_alwon_l3_fast__tptc3,
1437 &dm81xx_tptc0__alwon_l3_fast,
1438 &dm81xx_tptc1__alwon_l3_fast,
1439 &dm81xx_tptc2__alwon_l3_fast,
1440 &dm81xx_tptc3__alwon_l3_fast,
1441 &dm81xx_alwon_l3_slow__gpmc,
1442 &dm816x_default_l3_slow__usbss,
1446 int __init dm816x_hwmod_init(void)
1449 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);