arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <plat/clock.h>
  40 #include <plat/sram.h>
  41 #include <plat/dma.h>
  42 #include <plat/board.h>
  43
  44 #include "common.h"
  45 #include "prm2xxx_3xxx.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm2xxx_3xxx.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52
  53 #include "powerdomain.h"
  54 #include "clockdomain.h"
  55
  56 #ifdef CONFIG_SUSPEND
  57 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  58 static inline bool is_suspending(void)
  59 {
  60         return (suspend_state != PM_SUSPEND_ON);
  61 }
  62 #else
  63 static inline bool is_suspending(void)
  64 {
  65         return false;
  66 }
  67 #endif
  68
  69 static void (*omap2_sram_idle)(void);
  70 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  71                                   void __iomem *sdrc_power);
  72
  73 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  74 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  75
  76 static struct clk *osc_ck, *emul_ck;
  77
  78 static int omap2_fclks_active(void)
  79 {
  80         u32 f1, f2;
  81
  82         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  83         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  84
  85         return (f1 | f2) ? 1 : 0;
  86 }
  87
  88 static void omap2_enter_full_retention(void)
  89 {
  90         u32 l;
  91
  92         /* There is 1 reference hold for all children of the oscillator
  93          * clock, the following will remove it. If no one else uses the
  94          * oscillator itself it will be disabled if/when we enter retention
  95          * mode.
  96          */
  97         clk_disable(osc_ck);
  98
  99         /* Clear old wake-up events */
 100         /* REVISIT: These write to reserved bits? */
 101         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 102         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 103         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 104
 105         /*
 106          * Set MPU powerdomain's next power state to RETENTION;
 107          * preserve logic state during retention
 108          */
 109         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 110         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 111
 112         /* Workaround to kill USB */
 113         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 114         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 115
 116         omap2_gpio_prepare_for_idle(0);
 117
 118         /* One last check for pending IRQs to avoid extra latency due
 119          * to sleeping unnecessarily. */
 120         if (omap_irq_pending())
 121                 goto no_sleep;
 122
 123         /* Jump to SRAM suspend code */
 124         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 125                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 126                            OMAP_SDRC_REGADDR(SDRC_POWER));
 127
 128 no_sleep:
 129         omap2_gpio_resume_after_idle();
 130
 131         clk_enable(osc_ck);
 132
 133         /* clear CORE wake-up events */
 134         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 135         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 136
 137         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 138         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 139
 140         /* MPU domain wake events */
 141         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 142         if (l & 0x01)
 143                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 144                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 145         if (l & 0x20)
 146                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 147                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 148
 149         /* Mask future PRCM-to-MPU interrupts */
 150         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 151 }
 152
 153 static int omap2_i2c_active(void)
 154 {
 155         u32 l;
 156
 157         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 158         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 159 }
 160
 161 static int sti_console_enabled;
 162
 163 static int omap2_allow_mpu_retention(void)
 164 {
 165         u32 l;
 166
 167         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 168         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 169         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 170                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 171                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 172                 return 0;
 173         /* Check for UART3. */
 174         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 175         if (l & OMAP24XX_EN_UART3_MASK)
 176                 return 0;
 177         if (sti_console_enabled)
 178                 return 0;
 179
 180         return 1;
 181 }
 182
 183 static void omap2_enter_mpu_retention(void)
 184 {
 185         int only_idle = 0;
 186
 187         /* Putting MPU into the WFI state while a transfer is active
 188          * seems to cause the I2C block to timeout. Why? Good question. */
 189         if (omap2_i2c_active())
 190                 return;
 191
 192         /* The peripherals seem not to be able to wake up the MPU when
 193          * it is in retention mode. */
 194         if (omap2_allow_mpu_retention()) {
 195                 /* REVISIT: These write to reserved bits? */
 196                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 197                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 198                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 199
 200                 /* Try to enter MPU retention */
 201                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 202                                   OMAP_LOGICRETSTATE_MASK,
 203                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 204         } else {
 205                 /* Block MPU retention */
 206
 207                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 208                                                  OMAP2_PM_PWSTCTRL);
 209                 only_idle = 1;
 210         }
 211
 212         omap2_sram_idle();
 213 }
 214
 215 static int omap2_can_sleep(void)
 216 {
 217         if (omap2_fclks_active())
 218                 return 0;
 219         if (osc_ck->usecount > 1)
 220                 return 0;
 221         if (omap_dma_running())
 222                 return 0;
 223
 224         return 1;
 225 }
 226
 227 static void omap2_pm_idle(void)
 228 {
 229         local_irq_disable();
 230         local_fiq_disable();
 231
 232         if (!omap2_can_sleep()) {
 233                 if (omap_irq_pending())
 234                         goto out;
 235                 omap2_enter_mpu_retention();
 236                 goto out;
 237         }
 238
 239         if (omap_irq_pending())
 240                 goto out;
 241
 242         omap2_enter_full_retention();
 243
 244 out:
 245         local_fiq_enable();
 246         local_irq_enable();
 247 }
 248
 249 #ifdef CONFIG_SUSPEND
 250 static int omap2_pm_begin(suspend_state_t state)
 251 {
 252         disable_hlt();
 253         suspend_state = state;
 254         return 0;
 255 }
 256
 257 static int omap2_pm_suspend(void)
 258 {
 259         u32 wken_wkup, mir1;
 260
 261         wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 262         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 263         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 264
 265         /* Mask GPT1 */
 266         mir1 = omap_readl(0x480fe0a4);
 267         omap_writel(1 << 5, 0x480fe0ac);
 268
 269         omap2_enter_full_retention();
 270
 271         omap_writel(mir1, 0x480fe0a4);
 272         omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 273
 274         return 0;
 275 }
 276
 277 static int omap2_pm_enter(suspend_state_t state)
 278 {
 279         int ret = 0;
 280
 281         switch (state) {
 282         case PM_SUSPEND_STANDBY:
 283         case PM_SUSPEND_MEM:
 284                 ret = omap2_pm_suspend();
 285                 break;
 286         default:
 287                 ret = -EINVAL;
 288         }
 289
 290         return ret;
 291 }
 292
 293 static void omap2_pm_end(void)
 294 {
 295         suspend_state = PM_SUSPEND_ON;
 296         enable_hlt();
 297 }
 298
 299 static const struct platform_suspend_ops omap_pm_ops = {
 300         .begin          = omap2_pm_begin,
 301         .enter          = omap2_pm_enter,
 302         .end            = omap2_pm_end,
 303         .valid          = suspend_valid_only_mem,
 304 };
 305 #else
 306 static const struct platform_suspend_ops __initdata omap_pm_ops;
 307 #endif /* CONFIG_SUSPEND */
 308
 309 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 310 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 311 {
 312         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 313                 clkdm_allow_idle(clkdm);
 314         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 315                  atomic_read(&clkdm->usecount) == 0)
 316                 clkdm_sleep(clkdm);
 317         return 0;
 318 }
 319
 320 static void __init prcm_setup_regs(void)
 321 {
 322         int i, num_mem_banks;
 323         struct powerdomain *pwrdm;
 324
 325         /*
 326          * Enable autoidle
 327          * XXX This should be handled by hwmod code or PRCM init code
 328          */
 329         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 330                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 331
 332         /*
 333          * Set CORE powerdomain memory banks to retain their contents
 334          * during RETENTION
 335          */
 336         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 337         for (i = 0; i < num_mem_banks; i++)
 338                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 339
 340         /* Set CORE powerdomain's next power state to RETENTION */
 341         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 342
 343         /*
 344          * Set MPU powerdomain's next power state to RETENTION;
 345          * preserve logic state during retention
 346          */
 347         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 348         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 349
 350         /* Force-power down DSP, GFX powerdomains */
 351
 352         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 353         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 354         clkdm_sleep(dsp_clkdm);
 355
 356         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 357         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 358         clkdm_sleep(gfx_clkdm);
 359
 360         /* Enable hardware-supervised idle for all clkdms */
 361         clkdm_for_each(clkdms_setup, NULL);
 362         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 363
 364         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 365          * stabilisation */
 366         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 367                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 368
 369         /* Configure automatic voltage transition */
 370         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 371                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 372         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 373                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 374                                 OMAP24XX_MEMRETCTRL_MASK |
 375                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 376                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 377                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 378
 379         /* Enable wake-up events */
 380         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 381                                 WKUP_MOD, PM_WKEN);
 382 }
 383
 384 static int __init omap2_pm_init(void)
 385 {
 386         u32 l;
 387
 388         if (!cpu_is_omap24xx())
 389                 return -ENODEV;
 390
 391         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 392         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 393         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 394
 395         /* Look up important powerdomains */
 396
 397         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 398         if (!mpu_pwrdm)
 399                 pr_err("PM: mpu_pwrdm not found\n");
 400
 401         core_pwrdm = pwrdm_lookup("core_pwrdm");
 402         if (!core_pwrdm)
 403                 pr_err("PM: core_pwrdm not found\n");
 404
 405         /* Look up important clockdomains */
 406
 407         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 408         if (!mpu_clkdm)
 409                 pr_err("PM: mpu_clkdm not found\n");
 410
 411         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 412         if (!wkup_clkdm)
 413                 pr_err("PM: wkup_clkdm not found\n");
 414
 415         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 416         if (!dsp_clkdm)
 417                 pr_err("PM: dsp_clkdm not found\n");
 418
 419         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 420         if (!gfx_clkdm)
 421                 pr_err("PM: gfx_clkdm not found\n");
 422
 423
 424         osc_ck = clk_get(NULL, "osc_ck");
 425         if (IS_ERR(osc_ck)) {
 426                 printk(KERN_ERR "could not get osc_ck\n");
 427                 return -ENODEV;
 428         }
 429
 430         if (cpu_is_omap242x()) {
 431                 emul_ck = clk_get(NULL, "emul_ck");
 432                 if (IS_ERR(emul_ck)) {
 433                         printk(KERN_ERR "could not get emul_ck\n");
 434                         clk_put(osc_ck);
 435                         return -ENODEV;
 436                 }
 437         }
 438
 439         prcm_setup_regs();
 440
 441         /* Hack to prevent MPU retention when STI console is enabled. */
 442         {
 443                 const struct omap_sti_console_config *sti;
 444
 445                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 446                                       struct omap_sti_console_config);
 447                 if (sti != NULL && sti->enable)
 448                         sti_console_enabled = 1;
 449         }
 450
 451         /*
 452          * We copy the assembler sleep/wakeup routines to SRAM.
 453          * These routines need to be in SRAM as that's the only
 454          * memory the MPU can see when it wakes up.
 455          */
 456         if (cpu_is_omap24xx()) {
 457                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 458                                                  omap24xx_idle_loop_suspend_sz);
 459
 460                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 461                                                     omap24xx_cpu_suspend_sz);
 462         }
 463
 464         suspend_set_ops(&omap_pm_ops);
 465         pm_idle = omap2_pm_idle;
 466
 467         return 0;
 468 }
 469
 470 late_initcall(omap2_pm_init);