arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44
  45 #include <asm/mach/time.h>
  46 #include <asm/smp_twd.h>
  47 #include <asm/sched_clock.h>
  48
  49 #include <asm/arch_timer.h>
  50 #include "omap_hwmod.h"
  51 #include "omap_device.h"
  52 #include <plat/counter-32k.h>
  53 #include <plat/dmtimer.h>
  54 #include "omap-pm.h"
  55
  56 #include "soc.h"
  57 #include "common.h"
  58 #include "powerdomain.h"
  59
  60 /* Parent clocks, eventually these will come from the clock framework */
  61
  62 #define OMAP2_MPU_SOURCE        "sys_ck"
  63 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  64 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  65 #define OMAP5_MPU_SOURCE        "sys_clkin"
  66 #define OMAP2_32K_SOURCE        "func_32k_ck"
  67 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  68 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  69
  70 #define REALTIME_COUNTER_BASE                           0x48243200
  71 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  72 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  73 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  74
  75 /* Clockevent code */
  76
  77 static struct omap_dm_timer clkev;
  78 static struct clock_event_device clockevent_gpt;
  79
  80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  81 {
  82         struct clock_event_device *evt = &clockevent_gpt;
  83
  84         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  85
  86         evt->event_handler(evt);
  87         return IRQ_HANDLED;
  88 }
  89
  90 static struct irqaction omap2_gp_timer_irq = {
  91         .name           = "gp_timer",
  92         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  93         .handler        = omap2_gp_timer_interrupt,
  94 };
  95
  96 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  97                                          struct clock_event_device *evt)
  98 {
  99         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 100                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 101
 102         return 0;
 103 }
 104
 105 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 106                                     struct clock_event_device *evt)
 107 {
 108         u32 period;
 109
 110         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 111
 112         switch (mode) {
 113         case CLOCK_EVT_MODE_PERIODIC:
 114                 period = clkev.rate / HZ;
 115                 period -= 1;
 116                 /* Looks like we need to first set the load value separately */
 117                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 118                                       0xffffffff - period, OMAP_TIMER_POSTED);
 119                 __omap_dm_timer_load_start(&clkev,
 120                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 121                                         0xffffffff - period, OMAP_TIMER_POSTED);
 122                 break;
 123         case CLOCK_EVT_MODE_ONESHOT:
 124                 break;
 125         case CLOCK_EVT_MODE_UNUSED:
 126         case CLOCK_EVT_MODE_SHUTDOWN:
 127         case CLOCK_EVT_MODE_RESUME:
 128                 break;
 129         }
 130 }
 131
 132 static struct clock_event_device clockevent_gpt = {
 133         .name           = "gp_timer",
 134         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 135         .rating         = 300,
 136         .set_next_event = omap2_gp_timer_set_next_event,
 137         .set_mode       = omap2_gp_timer_set_mode,
 138 };
 139
 140 static struct property device_disabled = {
 141         .name = "status",
 142         .length = sizeof("disabled"),
 143         .value = "disabled",
 144 };
 145
 146 static struct of_device_id omap_timer_match[] __initdata = {
 147         { .compatible = "ti,omap2420-timer", },
 148         { .compatible = "ti,omap3430-timer", },
 149         { .compatible = "ti,omap4430-timer", },
 150         { .compatible = "ti,omap5430-timer", },
 151         { .compatible = "ti,am335x-timer", },
 152         { .compatible = "ti,am335x-timer-1ms", },
 153         { }
 154 };
 155
 156 /**
 157  * omap_get_timer_dt - get a timer using device-tree
 158  * @match       - device-tree match structure for matching a device type
 159  * @property    - optional timer property to match
 160  *
 161  * Helper function to get a timer during early boot using device-tree for use
 162  * as kernel system timer. Optionally, the property argument can be used to
 163  * select a timer with a specific property. Once a timer is found then mark
 164  * the timer node in device-tree as disabled, to prevent the kernel from
 165  * registering this timer as a platform device and so no one else can use it.
 166  */
 167 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
 168                                                      const char *property)
 169 {
 170         struct device_node *np;
 171
 172         for_each_matching_node(np, match) {
 173                 if (!of_device_is_available(np))
 174                         continue;
 175
 176                 if (property && !of_get_property(np, property, NULL))
 177                         continue;
 178
 179                 of_add_property(np, &device_disabled);
 180                 return np;
 181         }
 182
 183         return NULL;
 184 }
 185
 186 /**
 187  * omap_dmtimer_init - initialisation function when device tree is used
 188  *
 189  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
 190  * be used by the kernel as they are reserved. Therefore, to prevent the
 191  * kernel registering these devices remove them dynamically from the device
 192  * tree on boot.
 193  */
 194 static void __init omap_dmtimer_init(void)
 195 {
 196         struct device_node *np;
 197
 198         if (!cpu_is_omap34xx())
 199                 return;
 200
 201         /* If we are a secure device, remove any secure timer nodes */
 202         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 203                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 204                 if (np)
 205                         of_node_put(np);
 206         }
 207 }
 208
 209 /**
 210  * omap_dm_timer_get_errata - get errata flags for a timer
 211  *
 212  * Get the timer errata flags that are specific to the OMAP device being used.
 213  */
 214 static u32 __init omap_dm_timer_get_errata(void)
 215 {
 216         if (cpu_is_omap24xx())
 217                 return 0;
 218
 219         return OMAP_TIMER_ERRATA_I103_I767;
 220 }
 221
 222 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 223                                                 int gptimer_id,
 224                                                 const char *fck_source,
 225                                                 const char *property,
 226                                                 int posted)
 227 {
 228         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 229         const char *oh_name;
 230         struct device_node *np;
 231         struct omap_hwmod *oh;
 232         struct resource irq, mem;
 233         int r = 0;
 234
 235         if (of_have_populated_dt()) {
 236                 np = omap_get_timer_dt(omap_timer_match, property);
 237                 if (!np)
 238                         return -ENODEV;
 239
 240                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 241                 if (!oh_name)
 242                         return -ENODEV;
 243
 244                 timer->irq = irq_of_parse_and_map(np, 0);
 245                 if (!timer->irq)
 246                         return -ENXIO;
 247
 248                 timer->io_base = of_iomap(np, 0);
 249
 250                 of_node_put(np);
 251         } else {
 252                 if (omap_dm_timer_reserve_systimer(gptimer_id))
 253                         return -ENODEV;
 254
 255                 sprintf(name, "timer%d", gptimer_id);
 256                 oh_name = name;
 257         }
 258
 259         oh = omap_hwmod_lookup(oh_name);
 260         if (!oh)
 261                 return -ENODEV;
 262
 263         if (!of_have_populated_dt()) {
 264                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 265                                                    &irq);
 266                 if (r)
 267                         return -ENXIO;
 268                 timer->irq = irq.start;
 269
 270                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 271                                                    &mem);
 272                 if (r)
 273                         return -ENXIO;
 274
 275                 /* Static mapping, never released */
 276                 timer->io_base = ioremap(mem.start, mem.end - mem.start);
 277         }
 278
 279         if (!timer->io_base)
 280                 return -ENXIO;
 281
 282         /* After the dmtimer is using hwmod these clocks won't be needed */
 283         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 284         if (IS_ERR(timer->fclk))
 285                 return -ENODEV;
 286
 287         /* FIXME: Need to remove hard-coded test on timer ID */
 288         if (gptimer_id != 12) {
 289                 struct clk *src;
 290
 291                 src = clk_get(NULL, fck_source);
 292                 if (IS_ERR(src)) {
 293                         r = -EINVAL;
 294                 } else {
 295                         r = clk_set_parent(timer->fclk, src);
 296                         if (IS_ERR_VALUE(r))
 297                                 pr_warn("%s: %s cannot set source\n",
 298                                         __func__, oh->name);
 299                         clk_put(src);
 300                 }
 301         }
 302
 303         omap_hwmod_setup_one(oh_name);
 304         omap_hwmod_enable(oh);
 305         __omap_dm_timer_init_regs(timer);
 306
 307         if (posted)
 308                 __omap_dm_timer_enable_posted(timer);
 309
 310         /* Check that the intended posted configuration matches the actual */
 311         if (posted != timer->posted)
 312                 return -EINVAL;
 313
 314         timer->rate = clk_get_rate(timer->fclk);
 315         timer->reserved = 1;
 316
 317         return r;
 318 }
 319
 320 static void __init omap2_gp_clockevent_init(int gptimer_id,
 321                                                 const char *fck_source,
 322                                                 const char *property)
 323 {
 324         int res;
 325
 326         clkev.errata = omap_dm_timer_get_errata();
 327
 328         /*
 329          * For clock-event timers we never read the timer counter and
 330          * so we are not impacted by errata i103 and i767. Therefore,
 331          * we can safely ignore this errata for clock-event timers.
 332          */
 333         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 334
 335         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
 336                                      OMAP_TIMER_POSTED);
 337         BUG_ON(res);
 338
 339         omap2_gp_timer_irq.dev_id = &clkev;
 340         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 341
 342         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 343
 344         clockevent_gpt.cpumask = cpu_possible_mask;
 345         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 346         clockevents_config_and_register(&clockevent_gpt, clkev.rate,
 347                                         3, /* Timer internal resynch latency */
 348                                         0xffffffff);
 349
 350         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 351                 gptimer_id, clkev.rate);
 352 }
 353
 354 /* Clocksource code */
 355 static struct omap_dm_timer clksrc;
 356 static bool use_gptimer_clksrc;
 357
 358 /*
 359  * clocksource
 360  */
 361 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 362 {
 363         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 364                                                      OMAP_TIMER_NONPOSTED);
 365 }
 366
 367 static struct clocksource clocksource_gpt = {
 368         .name           = "gp_timer",
 369         .rating         = 300,
 370         .read           = clocksource_read_cycles,
 371         .mask           = CLOCKSOURCE_MASK(32),
 372         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 373 };
 374
 375 static u32 notrace dmtimer_read_sched_clock(void)
 376 {
 377         if (clksrc.reserved)
 378                 return __omap_dm_timer_read_counter(&clksrc,
 379                                                     OMAP_TIMER_NONPOSTED);
 380
 381         return 0;
 382 }
 383
 384 static struct of_device_id omap_counter_match[] __initdata = {
 385         { .compatible = "ti,omap-counter32k", },
 386         { }
 387 };
 388
 389 /* Setup free-running counter for clocksource */
 390 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 391 {
 392         int ret;
 393         struct device_node *np = NULL;
 394         struct omap_hwmod *oh;
 395         void __iomem *vbase;
 396         const char *oh_name = "counter_32k";
 397
 398         /*
 399          * If device-tree is present, then search the DT blob
 400          * to see if the 32kHz counter is supported.
 401          */
 402         if (of_have_populated_dt()) {
 403                 np = omap_get_timer_dt(omap_counter_match, NULL);
 404                 if (!np)
 405                         return -ENODEV;
 406
 407                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 408                 if (!oh_name)
 409                         return -ENODEV;
 410         }
 411
 412         /*
 413          * First check hwmod data is available for sync32k counter
 414          */
 415         oh = omap_hwmod_lookup(oh_name);
 416         if (!oh || oh->slaves_cnt == 0)
 417                 return -ENODEV;
 418
 419         omap_hwmod_setup_one(oh_name);
 420
 421         if (np) {
 422                 vbase = of_iomap(np, 0);
 423                 of_node_put(np);
 424         } else {
 425                 vbase = omap_hwmod_get_mpu_rt_va(oh);
 426         }
 427
 428         if (!vbase) {
 429                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 430                 return -ENXIO;
 431         }
 432
 433         ret = omap_hwmod_enable(oh);
 434         if (ret) {
 435                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 436                                                         __func__, ret);
 437                 return ret;
 438         }
 439
 440         ret = omap_init_clocksource_32k(vbase);
 441         if (ret) {
 442                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 443                                                         __func__, ret);
 444                 omap_hwmod_idle(oh);
 445         }
 446
 447         return ret;
 448 }
 449
 450 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 451                                                 const char *fck_source)
 452 {
 453         int res;
 454
 455         clksrc.errata = omap_dm_timer_get_errata();
 456
 457         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
 458                                      OMAP_TIMER_NONPOSTED);
 459         BUG_ON(res);
 460
 461         __omap_dm_timer_load_start(&clksrc,
 462                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 463                                    OMAP_TIMER_NONPOSTED);
 464         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 465
 466         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 467                 pr_err("Could not register clocksource %s\n",
 468                         clocksource_gpt.name);
 469         else
 470                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 471                         gptimer_id, clksrc.rate);
 472 }
 473
 474 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 475 /*
 476  * The realtime counter also called master counter, is a free-running
 477  * counter, which is related to real time. It produces the count used
 478  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 479  * at a rate of 6.144 MHz. Because the device operates on different clocks
 480  * in different power modes, the master counter shifts operation between
 481  * clocks, adjusting the increment per clock in hardware accordingly to
 482  * maintain a constant count rate.
 483  */
 484 static void __init realtime_counter_init(void)
 485 {
 486         void __iomem *base;
 487         static struct clk *sys_clk;
 488         unsigned long rate;
 489         unsigned int reg, num, den;
 490
 491         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 492         if (!base) {
 493                 pr_err("%s: ioremap failed\n", __func__);
 494                 return;
 495         }
 496         sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
 497         if (IS_ERR(sys_clk)) {
 498                 pr_err("%s: failed to get system clock handle\n", __func__);
 499                 iounmap(base);
 500                 return;
 501         }
 502
 503         rate = clk_get_rate(sys_clk);
 504         /* Numerator/denumerator values refer TRM Realtime Counter section */
 505         switch (rate) {
 506         case 1200000:
 507                 num = 64;
 508                 den = 125;
 509                 break;
 510         case 1300000:
 511                 num = 768;
 512                 den = 1625;
 513                 break;
 514         case 19200000:
 515                 num = 8;
 516                 den = 25;
 517                 break;
 518         case 2600000:
 519                 num = 384;
 520                 den = 1625;
 521                 break;
 522         case 2700000:
 523                 num = 256;
 524                 den = 1125;
 525                 break;
 526         case 38400000:
 527         default:
 528                 /* Program it for 38.4 MHz */
 529                 num = 4;
 530                 den = 25;
 531                 break;
 532         }
 533
 534         /* Program numerator and denumerator registers */
 535         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 536                         NUMERATOR_DENUMERATOR_MASK;
 537         reg |= num;
 538         __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 539
 540         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 541                         NUMERATOR_DENUMERATOR_MASK;
 542         reg |= den;
 543         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 544
 545         iounmap(base);
 546 }
 547 #else
 548 static inline void __init realtime_counter_init(void)
 549 {}
 550 #endif
 551
 552 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
 553                                clksrc_nr, clksrc_src)                   \
 554 void __init omap##name##_gptimer_timer_init(void)                       \
 555 {                                                                       \
 556         if (omap_clk_init)                                              \
 557                 omap_clk_init();                                        \
 558         omap_dmtimer_init();                                            \
 559         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 560         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
 561 }
 562
 563 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
 564                                 clksrc_nr, clksrc_src)                  \
 565 void __init omap##name##_sync32k_timer_init(void)               \
 566 {                                                                       \
 567         if (omap_clk_init)                                              \
 568                 omap_clk_init();                                        \
 569         omap_dmtimer_init();                                            \
 570         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 571         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
 572         if (use_gptimer_clksrc)                                         \
 573                 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
 574         else                                                            \
 575                 omap2_sync32k_clocksource_init();                       \
 576 }
 577
 578 #ifdef CONFIG_ARCH_OMAP2
 579 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
 580                         2, OMAP2_MPU_SOURCE);
 581 #endif /* CONFIG_ARCH_OMAP2 */
 582
 583 #ifdef CONFIG_ARCH_OMAP3
 584 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
 585                         2, OMAP3_MPU_SOURCE);
 586 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
 587                         2, OMAP3_MPU_SOURCE);
 588 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
 589                        2, OMAP3_MPU_SOURCE);
 590 #endif /* CONFIG_ARCH_OMAP3 */
 591
 592 #ifdef CONFIG_SOC_AM33XX
 593 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
 594                        2, OMAP4_MPU_SOURCE);
 595 #endif /* CONFIG_SOC_AM33XX */
 596
 597 #ifdef CONFIG_ARCH_OMAP4
 598 OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
 599                         2, OMAP4_MPU_SOURCE);
 600 #ifdef CONFIG_LOCAL_TIMERS
 601 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 602 void __init omap4_local_timer_init(void)
 603 {
 604         omap4_sync32k_timer_init();
 605         /* Local timers are not supprted on OMAP4430 ES1.0 */
 606         if (omap_rev() != OMAP4430_REV_ES1_0) {
 607                 int err;
 608
 609                 if (of_have_populated_dt()) {
 610                         clocksource_of_init();
 611                         return;
 612                 }
 613
 614                 err = twd_local_timer_register(&twd_local_timer);
 615                 if (err)
 616                         pr_err("twd_local_timer_register failed %d\n", err);
 617         }
 618 }
 619 #else /* CONFIG_LOCAL_TIMERS */
 620 void __init omap4_local_timer_init(void)
 621 {
 622         omap4_sync32k_timer_init();
 623 }
 624 #endif /* CONFIG_LOCAL_TIMERS */
 625 #endif /* CONFIG_ARCH_OMAP4 */
 626
 627 #ifdef CONFIG_SOC_OMAP5
 628 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
 629                         2, OMAP5_MPU_SOURCE);
 630 void __init omap5_realtime_timer_init(void)
 631 {
 632         int err;
 633
 634         omap5_sync32k_timer_init();
 635         realtime_counter_init();
 636
 637         err = arch_timer_of_register();
 638         if (err)
 639                 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 640 }
 641 #endif /* CONFIG_SOC_OMAP5 */
 642
 643 /**
 644  * omap_timer_init - build and register timer device with an
 645  * associated timer hwmod
 646  * @oh: timer hwmod pointer to be used to build timer device
 647  * @user:       parameter that can be passed from calling hwmod API
 648  *
 649  * Called by omap_hwmod_for_each_by_class to register each of the timer
 650  * devices present in the system. The number of timer devices is known
 651  * by parsing through the hwmod database for a given class name. At the
 652  * end of function call memory is allocated for timer device and it is
 653  * registered to the framework ready to be proved by the driver.
 654  */
 655 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 656 {
 657         int id;
 658         int ret = 0;
 659         char *name = "omap_timer";
 660         struct dmtimer_platform_data *pdata;
 661         struct platform_device *pdev;
 662         struct omap_timer_capability_dev_attr *timer_dev_attr;
 663
 664         pr_debug("%s: %s\n", __func__, oh->name);
 665
 666         /* on secure device, do not register secure timer */
 667         timer_dev_attr = oh->dev_attr;
 668         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 669                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 670                         return ret;
 671
 672         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 673         if (!pdata) {
 674                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 675                 return -ENOMEM;
 676         }
 677
 678         /*
 679          * Extract the IDs from name field in hwmod database
 680          * and use the same for constructing ids' for the
 681          * timer devices. In a way, we are avoiding usage of
 682          * static variable witin the function to do the same.
 683          * CAUTION: We have to be careful and make sure the
 684          * name in hwmod database does not change in which case
 685          * we might either make corresponding change here or
 686          * switch back static variable mechanism.
 687          */
 688         sscanf(oh->name, "timer%2d", &id);
 689
 690         if (timer_dev_attr)
 691                 pdata->timer_capability = timer_dev_attr->timer_capability;
 692
 693         pdata->timer_errata = omap_dm_timer_get_errata();
 694         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 695
 696         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
 697
 698         if (IS_ERR(pdev)) {
 699                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 700                         __func__, name, oh->name);
 701                 ret = -EINVAL;
 702         }
 703
 704         kfree(pdata);
 705
 706         return ret;
 707 }
 708
 709 /**
 710  * omap2_dm_timer_init - top level regular device initialization
 711  *
 712  * Uses dedicated hwmod api to parse through hwmod database for
 713  * given class name and then build and register the timer device.
 714  */
 715 static int __init omap2_dm_timer_init(void)
 716 {
 717         int ret;
 718
 719         /* If dtb is there, the devices will be created dynamically */
 720         if (of_have_populated_dt())
 721                 return -ENODEV;
 722
 723         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 724         if (unlikely(ret)) {
 725                 pr_err("%s: device registration failed.\n", __func__);
 726                 return -EINVAL;
 727         }
 728
 729         return 0;
 730 }
 731 omap_arch_initcall(omap2_dm_timer_init);
 732
 733 /**
 734  * omap2_override_clocksource - clocksource override with user configuration
 735  *
 736  * Allows user to override default clocksource, using kernel parameter
 737  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 738  *
 739  * Note that, here we are using same standard kernel parameter "clocksource=",
 740  * and not introducing any OMAP specific interface.
 741  */
 742 static int __init omap2_override_clocksource(char *str)
 743 {
 744         if (!str)
 745                 return 0;
 746         /*
 747          * For OMAP architecture, we only have two options
 748          *    - sync_32k (default)
 749          *    - gp_timer (sys_clk based)
 750          */
 751         if (!strcmp(str, "gp_timer"))
 752                 use_gptimer_clksrc = true;
 753
 754         return 0;
 755 }
 756 early_param("clocksource", omap2_override_clocksource);