arch/arm/mach-zynq/timer.c

   1 /*
   2  * This file contains driver for the Xilinx PS Timer Counter IP.
   3  *
   4  *  Copyright (C) 2011 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/types.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/slab.h>
  30 #include <linux/clk-provider.h>
  31
  32 #include <mach/zynq_soc.h>
  33 #include "common.h"
  34
  35 /*
  36  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  37  * and use same offsets for Timer 2
  38  */
  39 #define XTTCPSS_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
  40 #define XTTCPSS_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
  41 #define XTTCPSS_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
  42 #define XTTCPSS_INTR_VAL_OFFSET         0x24 /* Interval Count Reg, RW */
  43 #define XTTCPSS_MATCH_1_OFFSET          0x30 /* Match 1 Value Reg, RW */
  44 #define XTTCPSS_MATCH_2_OFFSET          0x3C /* Match 2 Value Reg, RW */
  45 #define XTTCPSS_MATCH_3_OFFSET          0x48 /* Match 3 Value Reg, RW */
  46 #define XTTCPSS_ISR_OFFSET              0x54 /* Interrupt Status Reg, RO */
  47 #define XTTCPSS_IER_OFFSET              0x60 /* Interrupt Enable Reg, RW */
  48
  49 #define XTTCPSS_CNT_CNTRL_DISABLE_MASK  0x1
  50
  51 /* Setup the timers to use pre-scaling, using a fixed value for now that will
  52  * work across most input frequency, but it may need to be more dynamic
  53  */
  54 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  55 #define PRESCALE                2048    /* The exponent must match this */
  56 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  57 #define CLK_CNTRL_PRESCALE_EN   1
  58 #define CNT_CNTRL_RESET         (1<<4)
  59
  60 /**
  61  * struct xttcpss_timer - This definition defines local timer structure
  62  *
  63  * @base_addr:  Base address of timer
  64  **/
  65 struct xttcpss_timer {
  66         void __iomem    *base_addr;
  67 };
  68
  69 struct xttcpss_timer_clocksource {
  70         struct xttcpss_timer    xttc;
  71         struct clocksource      cs;
  72 };
  73
  74 #define to_xttcpss_timer_clksrc(x) \
  75                 container_of(x, struct xttcpss_timer_clocksource, cs)
  76
  77 struct xttcpss_timer_clockevent {
  78         struct xttcpss_timer            xttc;
  79         struct clock_event_device       ce;
  80         struct clk                      *clk;
  81 };
  82
  83 #define to_xttcpss_timer_clkevent(x) \
  84                 container_of(x, struct xttcpss_timer_clockevent, ce)
  85
  86 /**
  87  * xttcpss_set_interval - Set the timer interval value
  88  *
  89  * @timer:      Pointer to the timer instance
  90  * @cycles:     Timer interval ticks
  91  **/
  92 static void xttcpss_set_interval(struct xttcpss_timer *timer,
  93                                         unsigned long cycles)
  94 {
  95         u32 ctrl_reg;
  96
  97         /* Disable the counter, set the counter value  and re-enable counter */
  98         ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
  99         ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 100         __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 101
 102         __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
 103
 104         /* Reset the counter (0x10) so that it starts from 0, one-shot
 105            mode makes this needed for timing to be right. */
 106         ctrl_reg |= CNT_CNTRL_RESET;
 107         ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 108         __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 109 }
 110
 111 /**
 112  * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
 113  *
 114  * @irq:        IRQ number of the Timer
 115  * @dev_id:     void pointer to the xttcpss_timer instance
 116  *
 117  * returns: Always IRQ_HANDLED - success
 118  **/
 119 static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
 120 {
 121         struct xttcpss_timer_clockevent *xttce = dev_id;
 122         struct xttcpss_timer *timer = &xttce->xttc;
 123
 124         /* Acknowledge the interrupt and call event handler */
 125         __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
 126                         timer->base_addr + XTTCPSS_ISR_OFFSET);
 127
 128         xttce->ce.event_handler(&xttce->ce);
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 /**
 134  * __xttc_clocksource_read - Reads the timer counter register
 135  *
 136  * returns: Current timer counter register value
 137  **/
 138 static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 139 {
 140         struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
 141
 142         return (cycle_t)__raw_readl(timer->base_addr +
 143                                 XTTCPSS_COUNT_VAL_OFFSET);
 144 }
 145
 146 /**
 147  * xttcpss_set_next_event - Sets the time interval for next event
 148  *
 149  * @cycles:     Timer interval ticks
 150  * @evt:        Address of clock event instance
 151  *
 152  * returns: Always 0 - success
 153  **/
 154 static int xttcpss_set_next_event(unsigned long cycles,
 155                                         struct clock_event_device *evt)
 156 {
 157         struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
 158         struct xttcpss_timer *timer = &xttce->xttc;
 159
 160         xttcpss_set_interval(timer, cycles);
 161         return 0;
 162 }
 163
 164 /**
 165  * xttcpss_set_mode - Sets the mode of timer
 166  *
 167  * @mode:       Mode to be set
 168  * @evt:        Address of clock event instance
 169  **/
 170 static void xttcpss_set_mode(enum clock_event_mode mode,
 171                                         struct clock_event_device *evt)
 172 {
 173         struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
 174         struct xttcpss_timer *timer = &xttce->xttc;
 175         u32 ctrl_reg;
 176
 177         switch (mode) {
 178         case CLOCK_EVT_MODE_PERIODIC:
 179                 xttcpss_set_interval(timer,
 180                                      DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
 181                                                        PRESCALE * HZ));
 182                 break;
 183         case CLOCK_EVT_MODE_ONESHOT:
 184         case CLOCK_EVT_MODE_UNUSED:
 185         case CLOCK_EVT_MODE_SHUTDOWN:
 186                 ctrl_reg = __raw_readl(timer->base_addr +
 187                                         XTTCPSS_CNT_CNTRL_OFFSET);
 188                 ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 189                 __raw_writel(ctrl_reg,
 190                                 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 191                 break;
 192         case CLOCK_EVT_MODE_RESUME:
 193                 ctrl_reg = __raw_readl(timer->base_addr +
 194                                         XTTCPSS_CNT_CNTRL_OFFSET);
 195                 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 196                 __raw_writel(ctrl_reg,
 197                                 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 198                 break;
 199         }
 200 }
 201
 202 static void __init zynq_ttc_setup_clocksource(struct device_node *np,
 203                                              void __iomem *base)
 204 {
 205         struct xttcpss_timer_clocksource *ttccs;
 206         struct clk *clk;
 207         int err;
 208         u32 reg;
 209
 210         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 211         if (WARN_ON(!ttccs))
 212                 return;
 213
 214         err = of_property_read_u32(np, "reg", &reg);
 215         if (WARN_ON(err))
 216                 return;
 217
 218         clk = of_clk_get_by_name(np, "cpu_1x");
 219         if (WARN_ON(IS_ERR(clk)))
 220                 return;
 221
 222         err = clk_prepare_enable(clk);
 223         if (WARN_ON(err))
 224                 return;
 225
 226         ttccs->xttc.base_addr = base + reg * 4;
 227
 228         ttccs->cs.name = np->name;
 229         ttccs->cs.rating = 200;
 230         ttccs->cs.read = __xttc_clocksource_read;
 231         ttccs->cs.mask = CLOCKSOURCE_MASK(16);
 232         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 233
 234         __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
 235         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 236                      ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
 237         __raw_writel(CNT_CNTRL_RESET,
 238                      ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 239
 240         err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
 241         if (WARN_ON(err))
 242                 return;
 243 }
 244
 245 static void __init zynq_ttc_setup_clockevent(struct device_node *np,
 246                                             void __iomem *base)
 247 {
 248         struct xttcpss_timer_clockevent *ttcce;
 249         int err, irq;
 250         u32 reg;
 251
 252         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 253         if (WARN_ON(!ttcce))
 254                 return;
 255
 256         err = of_property_read_u32(np, "reg", &reg);
 257         if (WARN_ON(err))
 258                 return;
 259
 260         ttcce->xttc.base_addr = base + reg * 4;
 261
 262         ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
 263         if (WARN_ON(IS_ERR(ttcce->clk)))
 264                 return;
 265
 266         err = clk_prepare_enable(ttcce->clk);
 267         if (WARN_ON(err))
 268                 return;
 269
 270         irq = irq_of_parse_and_map(np, 0);
 271         if (WARN_ON(!irq))
 272                 return;
 273
 274         ttcce->ce.name = np->name;
 275         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 276         ttcce->ce.set_next_event = xttcpss_set_next_event;
 277         ttcce->ce.set_mode = xttcpss_set_mode;
 278         ttcce->ce.rating = 200;
 279         ttcce->ce.irq = irq;
 280
 281         __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 282         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 283                      ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
 284         __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
 285
 286         err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
 287                           np->name, ttcce);
 288         if (WARN_ON(err))
 289                 return;
 290
 291         clockevents_config_and_register(&ttcce->ce,
 292                                         clk_get_rate(ttcce->clk) / PRESCALE,
 293                                         1, 0xfffe);
 294 }
 295
 296 static const __initconst struct of_device_id zynq_ttc_match[] = {
 297         { .compatible = "xlnx,ttc-counter-clocksource",
 298                 .data = zynq_ttc_setup_clocksource, },
 299         { .compatible = "xlnx,ttc-counter-clockevent",
 300                 .data = zynq_ttc_setup_clockevent, },
 301         {}
 302 };
 303
 304 /**
 305  * xttcpss_timer_init - Initialize the timer
 306  *
 307  * Initializes the timer hardware and register the clock source and clock event
 308  * timers with Linux kernal timer framework
 309  **/
 310 void __init xttcpss_timer_init(void)
 311 {
 312         struct device_node *np;
 313
 314         for_each_compatible_node(np, NULL, "xlnx,ttc") {
 315                 struct device_node *np_chld;
 316                 void __iomem *base;
 317
 318                 base = of_iomap(np, 0);
 319                 if (WARN_ON(!base))
 320                         return;
 321
 322                 for_each_available_child_of_node(np, np_chld) {
 323                         int (*cb)(struct device_node *np, void __iomem *base);
 324                         const struct of_device_id *match;
 325
 326                         match = of_match_node(zynq_ttc_match, np_chld);
 327                         if (match) {
 328                                 cb = match->data;
 329                                 cb(np_chld, base);
 330                         }
 331                 }
 332         }
 333 }