arch/arm64/boot/dts/arm/juno-r1.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2015 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12
  13 / {
  14         model = "ARM Juno development board (r1)";
  15         compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &soc_uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu-map {
  38                         cluster0 {
  39                                 core0 {
  40                                         cpu = <&A57_0>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&A57_1>;
  44                                 };
  45                         };
  46
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&A53_0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&A53_1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&A53_2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&A53_3>;
  59                                 };
  60                         };
  61                 };
  62
  63                 A57_0: cpu@0 {
  64                         compatible = "arm,cortex-a57","arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         device_type = "cpu";
  67                         enable-method = "psci";
  68                         next-level-cache = <&A57_L2>;
  69                 };
  70
  71                 A57_1: cpu@1 {
  72                         compatible = "arm,cortex-a57","arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         device_type = "cpu";
  75                         enable-method = "psci";
  76                         next-level-cache = <&A57_L2>;
  77                 };
  78
  79                 A53_0: cpu@100 {
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x100>;
  82                         device_type = "cpu";
  83                         enable-method = "psci";
  84                         next-level-cache = <&A53_L2>;
  85                 };
  86
  87                 A53_1: cpu@101 {
  88                         compatible = "arm,cortex-a53","arm,armv8";
  89                         reg = <0x0 0x101>;
  90                         device_type = "cpu";
  91                         enable-method = "psci";
  92                         next-level-cache = <&A53_L2>;
  93                 };
  94
  95                 A53_2: cpu@102 {
  96                         compatible = "arm,cortex-a53","arm,armv8";
  97                         reg = <0x0 0x102>;
  98                         device_type = "cpu";
  99                         enable-method = "psci";
 100                         next-level-cache = <&A53_L2>;
 101                 };
 102
 103                 A53_3: cpu@103 {
 104                         compatible = "arm,cortex-a53","arm,armv8";
 105                         reg = <0x0 0x103>;
 106                         device_type = "cpu";
 107                         enable-method = "psci";
 108                         next-level-cache = <&A53_L2>;
 109                 };
 110
 111                 A57_L2: l2-cache0 {
 112                         compatible = "cache";
 113                 };
 114
 115                 A53_L2: l2-cache1 {
 116                         compatible = "cache";
 117                 };
 118         };
 119
 120         pmu {
 121                 compatible = "arm,armv8-pmuv3";
 122                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 123                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 127                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 128                 interrupt-affinity = <&A57_0>,
 129                                      <&A57_1>,
 130                                      <&A53_0>,
 131                                      <&A53_1>,
 132                                      <&A53_2>,
 133                                      <&A53_3>;
 134         };
 135
 136         #include "juno-base.dtsi"
 137
 138 };
 139
 140 &memtimer {
 141         status = "okay";
 142 };